JPH043525A - Code error correcting device - Google Patents

Abstract

PURPOSE:To improve the error correction capability by overwriting a corrected data or a data whose error is not detected among the data subjected to inner code/decoding in the data transmitted or recorded and reproduced repetitively for plural number of times into a memory provided for one product code block. CONSTITUTION:The data of a same error correction code block transmitted or recorded and reproduced repetitively for plural number of times is stored in the same address of a memory 6 by a control means 7 and plural pieces of inspection information are stored in different addresses. Moreover, only a block whose error is corrected or in which no error is detected by an inner code decoding circuit 4 is controlled to be written in the memory 6 as to a same error correction code block sent or recorded and reproduced repetitively for 2nd and subsequent times. Thus, when check information generated to an error correction code block is discordant, the inspection means 9 outputs an error flag representing the occurrence of an error. Thus, the error correction capability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a configuration of a code error correction device in a digital information recording/reproducing device and a control method thereof.

[Conventional technology]

A conventional code error correction device for digital signals that has a high correction ability for both random errors and burst errors uses a product code configuration as described in Japanese Patent Application Laid-Open No. 57-10561, and an inner code (second If there are many uncorrectable errors when decoding an error correction block (error correction block), a flag (pointer) indicating an error is added to all words in the inner code block, and then rearranged into the outer code array and the outer code It was configured to decrypt . When decoding this code, the syndrome calculated from the words in the outer code block (first error correction block) and the flag added at the time of decoding the inner code are used as pointers to determine the error correction ability. It was designed to perform error correction using a high pointer laser method.

Furthermore, as a method to improve the correction ability, JP-A-63-3
As described in Japanese Patent No. 17990, a block with the above product code configuration is recorded or transmitted multiple times, and upon playback, after the inner code (first check word) is decoded, the outer code (second check word) is decoded. When performing decoding, the correction ability is improved by selecting data with as few errors as possible each time from the data that has been error-detected and corrected using the inner codes that have been reproduced a plurality of times. Furthermore, with this method, even if no error is detected in the inner code, it is possible to detect an error by comparing multiple pieces of reproduced data, making it possible to improve data reliability.

[Problem to be solved by the invention]

The above-mentioned conventional technology stores each block of the product code structure that has been reproduced multiple times in memory, and then simultaneously reads out data and error flags from each memory, and compares them to create data that is free from uncorrectable errors caused by inner codes as much as possible. is selected, the outer code is decoded, and errors are checked for false detection by data comparison. There is a problem in that when the same block is recorded and reproduced many times, a large number of large-capacity memories are required.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a code error correction device that can improve error correction capability through multiple recording and reproduction and prevent erroneous error detection without increasing memory capacity.

[Means to solve the problem]

In order to achieve the above object, in the present invention, for each block of a product code structure that is repeatedly transmitted or recorded/reproduced multiple times, the inner code for one block is decoded to create block data and each of these inner code blocks. A memory is provided for storing at least one check word for each. Then, check information arithmetically determined from the data and parity contained in each inner code block that has been decoded by the inner code, such as a so-called checksum of the lower byte of the sum of data and parity, is generated.

For the product code block transmitted or reproduced for the first time, the data after decoding each inner code and the test information generated by the inner code block are respectively written to predetermined addresses in the memory. For product code blocks with the same content transmitted or reproduced from the second time onwards, only the inner code blocks for which no errors were detected or were corrected by each inner code decoding are stored at the same memory address as the corresponding first inner code block. The test information is written to a predetermined memory address different from the first time, depending on the number of transmissions or reproductions. After the transmission or reproduction of the product code block is completed a predetermined number of times and the inner code decoding is completed, multiple checks are added to each inner code block and written to the memory for each number of transmissions or reproductions. Read information and compare them. If these pieces of check information do not match, an error flag indicating that there is an error in the inner code block is output so that it can be referenced when decoding the outer code.

Here, the comparison of check information is performed only for blocks without uncorrectable errors, and for this purpose, it is sufficient to refer to the error flag of the inner code decoding result. - When decoding the inner code of a product code block with the same content multiple times, for each block in which no error is detected or is corrected for the first time in decoding of each corresponding inner code block with the same content. writes the test information to the test information write address of each corresponding internal code block on the memory. That is, when the data is transmitted or reproduced n times, it is written to n predetermined locations on the memory.

Then, for blocks in which no errors are detected or errors thereafter are corrected, check information is written to a predetermined location on the memory. As a result, for blocks in which uncorrectable errors have been detected, check information is not written to memory.
Test information can be effectively compared without referring to error flags.

Further, by making the memory address of the check information of each inner code block in the product code block having the same content common for multiple transmissions or reproductions, the required memory capacity can be further reduced. In this case, either the second or subsequent error is not detected, or when writing the corrected inner code block to memory, the check information generated by the inner code block with the same content that has been written to memory up to that point is stored in the memory. and compare it with the new test information. Then, this new test information is written to the same address, and if the old and new test information do not match, the error flag of the inner code block is changed. Since the error flag is changed only when no error is detected or the error is corrected in the second and subsequent inner code blocks, it is necessary to check whether any errors are detected in the inner code blocks that were previously decoded and stored in memory. Alternatively, if the new and old check information does not match even though the check information has been corrected, the error flag is inverted to determine that there is an uncorrectable error. In addition, if there is an uncorrectable error in the intra-code block, it is natural that the new and old check information will not match, but similarly, the error flag is inverted and the new code is newly written to the memory from the second time onwards. Indicates that the block has no detected errors or has been corrected.

Alternatively, the old and new checks can be performed only if the error flag attached to the intra-code block indicates that the error has not been detected or has been corrected (this condition is often expressed as "no error flag"). If the information does not match, it may be replaced with an error flag that indicates the existence of an uncorrectable error, and in other cases, the error flag of the new inner code block in which the second or subsequent error has not been detected or has been corrected may be used. .

[Effect]

With the above configuration and operation, the memory provided for one product code block contains data after inner code decoding that has been repeatedly transmitted or recorded and reproduced multiple times, with no errors detected or no errors corrected. The previous one will be overwritten. Therefore, even if an inner code block has an uncorrectable error detected in the first transmission or reproduction, if the error is not detected or corrected in the second or subsequent transmission or reproduction, it is rewritten to the correct inner code block. Therefore, if the outer code block is read from this memory after the input of the inner code block by repeated transmission or reproduction of this product code block is completed, the inner code block will be stored in a separate memory for each transmission or reproduction. It is possible to obtain the same effect as storing data and selecting data with as few errors as possible from among them at the time of outer code decoding, and the error correction ability can be improved. Furthermore, by comparing, for example, checksum data between inner code blocks where errors are not detected in the inner code, it is possible to detect error corrections or omissions in error detection during inner code decoding, improving data reliability. . here,
In the conventional example disclosed in Japanese Patent Application Laid-Open No. 63-317990, each piece of outer code data is compared individually and rechecked for errors, but due to the nature of the error correction code, errors may occur in the inner code. When erroneous correction occurs, it is often the case that a large number of code blocks are included in the data due to a burst error, and the method of the present invention can achieve almost the same effect.

In addition, in the present invention, even in the case where only -fold encoding is performed instead of the product code configuration (for example, when only the inner code described here is added),
It is clear that a similar effect can be obtained when the same code block is repeatedly transmitted or recorded and reproduced.

〔Example〕

The details of the present invention will be explained below using examples.

FIG. 1 is a block diagram showing a configuration in which a code error correction apparatus according to the present invention is used in an audio signal reproduction system of a so-called D22 duplex VTR, which is a digital recording type VTR.

In Figure 1, 1 is a magnetic tape, 2 is a playback head attached to a rotating drum, 3 is a demodulation circuit, 4 is an inner code decoding circuit that decodes the inner code, and 5 is a generator that generates inspection information from the decoded inner code. 6 is a memory for storing data in a product code configuration, parity, and the above-mentioned test information;
7 is a memory control circuit that controls writing and reading of the memory 6 and error flag memory 8; 8 is an error flag memory that stores the error flag added to the inner code block by the inner code decoding circuit; 9 is a comparison of check information; The test circuit for testing, 10, is an outer code decoding circuit for decoding the outer code.

The audio signal of a D2 format digital VTR is 4
Each symbol of the audio signal of the channel is encoded in the form of a product code using an 8-bit Reed-Solomon code, and is recorded twice at each end of the helical track.

By doubly recording each audio channel in this way, protection against code errors is strengthened.

An audio signal product-coded using a Reed-Solomon code recorded twice on a magnetic tape 1 is first reproduced by a magnetic head 2 in the order of inner codes of the first product code block, and is input to a demodulation circuit 3. The demodulation circuit 3 performs demodulation corresponding to the modulation performed during recording, and also detects a synchronization signal that serves as a timing reference. Next, the inner code decoding circuit 4 performs error detection and correction for each inner code block. Send demodulated signal. The inner code decoding circuit 4 performs error detection and correction using the inner code parity for each inner code block, and the decoded data is sent to the test information generation circuit 5. The data is sent to the memory 6 and the memory control circuit 7. Furthermore, if an uncorrectable error is detected by inner code decoding, a “High” level signal is sent as an error flag; otherwise, a “LO, u” level signal is sent to the memory control circuit 7 and the error flag memory 8. The test information generation circuit 5 generates test information for each input decoded inner code block and sends it to the memory 6.

Here, the check information will be explained using, for example, the so-called checksum byte, which is the lower 8 bits of the total sum of data symbols and parity symbols in each inner code block.

The D2 format reproduction signal includes an ID signal indicating the positional relationship of each inner code block on the recording track, and this corresponds to the position of each inner code block within the product code block. The memory control circuit generates an address in the memory 6 for each inner code data and inspection information and an address in the error flag memory 8 for the error flag based on this ID signal, and outputs a write pulse WE for each. The data and various information of the inner code block are written into the memory 6 and the error flag memory 8. Note that when the present invention is applied to a system without an ID signal, memory addresses may be generated in accordance with the input order of reproduction signals. In this way, after the decoding of each inner code of the first product code block is completed and writing to each memory 6.8 is completed, the second product code block that has been double recorded on the magnetic tape 1 is then read by the magnetic head 2. It is played back in the same inner code order as the first time. Then, demodulation, inner code decoding, etc. are performed in the same manner, and the decoded data is sent to the test information generation circuit 5. The signal is sent to the memory 6 and the memory control circuit 7. Similarly, an error flag is sent to the memory control circuit 7 and the error flag memory 8.

Test information is similarly generated in the test information generation circuit 5 and sent to the memory 6. Here, the memory control circuit 7 is 1
Similarly to the first time, the same address as the first time is generated for each inner code data, but a predetermined address different from the first time is generated for the error flag and check information. Then, when there is no uncorrectable error and the error flag from the inner code decoding circuit 4 is "Lo, + level", the write pulse WE is output to all these addresses, and the inner code data is stored at the same location for the first time. The inner code data is overwritten, and the error flag and inspection information are written in a different location than the first time.On the other hand, when the error flag is
h” level, the write pulse WE is not output for the inner code data, and the first inner code data is stored in the memory 6.
remain within. Here, if all the contents of the preliminary error flag memory 8 are set to "High" level before the first product code reproduction, an uncorrectable error occurs in the second inner code decoding, and the error flag ( L Hlg h *″
When the level is reached, the write pulse WE can also be made not to be output for the error flag and inspection information.

After completing the second inner code block processing in this way,
The memory control circuit 7 outputs the address where the first and second check information and error flag of the code block are written and the read pulse ○E to the memory 6 and the error flag memory 8, and outputs the read pulse ○E to the memory 6 and the error flag memory 8. 8 outputs these to the inspection circuit 9. The inspection circuit 9 outputs a control command signal to the memory control circuit 7 when the first and second inspection information do not match even though both of these two error flags are at the 11LO,I+ level. , sends a "High" level error flag to the error flag memory 8. In response to this, the memory control circuit 7 outputs the error flag address and write pulse WE for the two times of decoding of the code block to the error flag memory 8, and this "High" level error flag is written to both addresses. or written. After the reproduction and decoding of all inner code blocks of the second product code block is completed as described above, the product code block data in the memory 6 is the data obtained by the two reproductions, with as few errors as possible. It is a collection of code blocks. In addition, the two error flags of each inner code block in the error flag memory 8 are used as check information when both uncorrectable errors are detected in two decodings, and even when no uncorrectable errors are detected in both decodings. When an error is detected by comparison, both become "High" level. Therefore, after that, the memory control circuit 7 reads the outer code data and parity from the memory 6, and the outer code decoding circuit 10 reads out the outer code data and parity from the memory 6.
By decoding the outer code by referring to two error flags for each data similarly read from the error flag memory 8, it is possible to improve the correction ability. Here, both error flags are “Hi”
gh” level, the outer code is decoded assuming that there is an error in the data.The comparison check of the test information is performed from the second time when all the inner code blocks are decoded until the start of outer code decoding. You can do it all at once.

Note that if the test information is written to the addresses of the first and second test information on the memory 6 at the time of the first inner code decoding, there is no need to refer to the error flag when checking whether the test information matches. disappears. In other words, if an uncorrectable error is detected in the second inner code decoding, the error flag will not be written in the check information, and if an uncorrectable error is detected in the first decoding but not in the second, the error flag will not be written in the check information. If the second test information is written to both the first and second test information addresses, it is possible that an uncorrectable error is detected in both decodings, or that an uncorrectable error is detected in both decodings, or that an uncorrectable error is not detected in both decodings, but at least one false detection or error occurs. The two pieces of inspection information become inconsistent only when a correction occurs. Therefore, in this case, the error flag memory 8 does not need different error flag addresses for the first and second times, and there is no need to read two error flags during outer code decoding, and the number of accesses can be reduced. can. Furthermore, the present invention can be applied to a system that performs multiple recording, and in that case, if an uncorrectable error is not detected at the beginning during multiple decodings, the test information is written to all of the test information addresses for each of these decodings. All you have to do is try to get into it.

Next, FIG. 2 shows a block diagram of an embodiment of the test information generation circuit 5. In FIG. 2, 11 is an adder circuit, 12
is a parallel 8-bit register.

Before the inner code block is input to the test information generation circuit 5, a reset signal is input to the register 12, and all 8 bits are cleared. Then, every time the inner code block data is input to the adder circuit 11, a clock is input to the register 12. Therefore, when data is inputted as A, B, C, etc., the output of the adder circuit 11 is (○+A), (A+
B), (A0B0C), etc., and the lower 8 bits thereof are latched into the register 12. As a result, when the input of one inner code block is completed, the lower 8 bits of the total remain in the register 12 and serve as the above-mentioned check information. Of course, other operations such as multiplication and subtraction may be used for the inspection information.

Next, one embodiment of the inspection circuit 9 is shown in a block diagram with reference to FIG. In FIG. 3, 13 and 14 are registers, 15 is a comparator, and 16 is a control circuit.

The check information and error flag of the first inner code block and the check information and error flag of the second inner code block are input to the registers 13 and 14, respectively, and are latched by the clock from the control circuit 16. Register 13.1
The output of 4 is input to the comparator 15, and the comparator 15 compares only the test information portion. And register 1
The error flag parts of outputs 3 and 14 are both LL L O
, ++ level, the control circuit 16 outputs a "High" level to the control circuit 16 only when the two pieces of inspection information do not match. and outputs a "High" level error flag to the memory control circuit 7 and error flag memory 8. Note that when the error flag is not referred to, the comparator 15 sets the control circuit 1 to the "Loty" level if the inspection information matches, and to the "High" level if they do not match.
Output to 6.

FIG. 4 shows a block diagram of another embodiment of the invention. In FIG. 4, 17 is a memory, 18 is a flag processing circuit, 19 is a test circuit, and 20 is a memory control circuit.

As in the embodiment shown in FIG.
written to. Further, the error flag is written into the error flag memory 8 through the flag processing circuit 18. Next, when decoding the inner code of the second product code block,
Only when no error is detected or corrected by the inner code decoding circuit 4 for each inner code block, the l(LO, t+ level) is input to the memory control circuit 20 as an error flag. Same address and write pulse W as the inner code data once every 17 days
E is output, and these inner code data are overwritten on the inner code data of one circuit. Subsequently, the test information of the first inner code block is read from the memory 17 and input to the test circuit 19. At the same time, the test information of the second inner code block is inputted to the test circuit 19 from the test information generation circuit 5.
If these do not match, a "High" level is output to the flag processing circuit 18. When the signal from the inspection circuit 19 is at the "High" level, the flag processing circuit 18 inverts the first inner code error flag read from the error flag memory by the memory control circuit 20 and outputs it to the error flag memory again. The memory control circuit 20 uses this as 1
Write to the same address as the second error flag. As a result, the corresponding address in the error flag memory 8 has a "High" level if there is an error the first time and no error the second time.
tLow,.

If the inspection information does not match even though there are no errors in the first and second inspections, “L” is written.
oll" level is inverted to "High" level and written. On the other hand, if an error is detected the second time, nothing is written and the state of the first time is maintained. In the above manner, 2 After the inner code decoding of the product code block is completely completed, the error flags based on the inner code in the error flag memory 8 and the memory 17 and the data of the product code block are the same as in the embodiment shown in FIG. The outer code is subsequently decoded in the same manner.

FIG. 5 shows an example of the configuration of the test circuit 19 used in the embodiment of FIG. 4. In Figure 5, 20.23 is a register, 22
is a comparator. The new test information generated from the second inner code block is input to the register 21, the old test information read from the memory 17 is input to the register 23, and these outputs are compared by the comparator 22. If these match, the comparator 22 outputs “L o, 7 lebel, if you want -1”
Outputs "High" level.

Next, an example of the configuration of the flag processing circuit 18 is shown in FIG. 6th
In the figure, 24 is a data selector, 25 is Ex-O
R gate 26 is a control circuit. During the first inner code decoding, the control circuit 26 switches the data selector 24 to the error flag side from the inner code decoding circuit 4 and outputs this to the error flag memory 8. At the second inner code decoding, Ex
-OR gate 25 side, and when the signal from test circuit 19 is at "High" level, the error flag read from flag memory 8 is inverted and output.

FIG. 7 shows another example of the configuration of the flag processing circuit 18. In FIG. 7, 27 is an error flag, that is, "Hi"
gh'' level generator, 28 is a control circuit, 29 is an inverter, and 30 is a NAND gate.

In this case, the control circuit 28 switches the data selector 24 to the error flag generator side 27 when the signal from the NAND gate 30 is at the "LoIll" level, and otherwise switches and outputs the error flag from the inner code decoding circuit 4. Therefore, when the first error flag read from the error flag memory 8 is IILo, and the test information does not match, the error flag generator 27 outputs a high level.

〔Effect of the invention〕

According to the present invention, high correction capability can be obtained using a memory with a capacity equivalent to approximately one product code block, and erroneous detection and re-detection of erroneous corrections due to inner codes can be performed, thereby improving the reliability of digital information reproduction. It has an improving effect.

[Brief explanation of the drawing]

1 and 4 are block diagrams of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration example of the test information generation circuit 5, and FIGS. 3 and 5 are test circuits 9 and 19. FIGS. 6 and 7 are block diagrams showing an example of the configuration of the flag processing circuit 18 of the embodiment shown in FIG. 4... Inner code decoding circuit, 5... Inspection information generation circuit,
6.17...Memory, 8...Error flag memory, 9.19...Inspection circuit, 7.20...Memory control circuit, 18...Flag processing circuit, 10...Outer code decoding circuit. Compiled drawings of falcon drawings

Claims (1)

[Claims] 1. Configuring an error correction code block with parity added for code error detection and correction for each predetermined amount of digital information signal, and repeatedly transmitting or recording/playing the same error correction code block multiple times. In a code error correction device that decodes a signal obtained by
); and a test information generating means (5) for generating test information for each block by arithmetic operations on each data and parity of the decoded error correction code block output from the test information generating means (5); a storage means (6) for storing at least each data of the decoded error correction code block outputted from the error correction means (4) and the check information obtained from the error correction means (4); and controlling data input/output to the storage means (6). The test information generated by the control means (7) and the test information generation means (5) corresponding to the same error correction code block read out from the storage means (6) and transmitted or recorded and reproduced multiple times. a checking means (9) for checking whether the check information matches or does not match; ), and the plural pieces of check information are stored in different locations in the storage means (6), and the same error correction code block transmitted or recorded or reproduced from the second time onward is stored in the same location in the above storage means (6). The error correction means (4) has a configuration in which the error correction means (4) controls to write only blocks whose errors have been corrected or no errors detected, into the storage means (6), and the checking means (9) detects the same error. If multiple pieces of check information generated for an error correction code block in which the code has been corrected or no error has been detected do not match, an error flag indicating the occurrence of an error is output. Characteristic code error correction device. 2. The control means (7) is configured to control, for n pieces of check information generated for the same error correction code block that has been repeatedly transmitted or recorded or reproduced n times, the control means (7) In decoding, the above error correction means (
4), the check information of the block whose error was first corrected or no error was detected is written to the n locations of the storage means (6) given to the n pieces of check information, and the above is written for subsequent blocks. 2. The code error correction system according to claim 1, wherein the code error correction means writes the check information to a predetermined one of the n locations only when the error is corrected or not detected by the error correction means (4). Device. 3. A signal obtained by constructing an error correction code block with parity added for code error detection and correction for each predetermined amount of digital information signal, and repeatedly transmitting or recording and reproducing the same error correction code block multiple times. A code error correction device for decoding a signal includes: an error correction means (4) for sequentially decoding error correction code blocks of a transmitted or reproduced signal;
); and a test information generating means (5) for generating test information for each block by arithmetic operations on each data and parity of the decoded error correction code block output from the test information generating means (5); a first memory which stores at least each data of the decoded error correction code block outputted from the error correction means (4) and the check information of the error correction code block;
a storage means (17); and a second storage means (8) for storing an error flag indicating whether or not an uncorrectable error is detected in each error correction code block by decoding by the error correction means (4). , the second storage means (8) and the first storage means (17).
); and a control means (20) for controlling data input/output to the same error correction code block that is repeatedly transmitted or recorded/reproduced multiple times.
Among the respective pieces of test information generated by a checking means (19) for checking whether the check information written and read out from the storage means (17) matches; The blocks are stored in the same location in the first storage means (17), and at least the inspection information of the first block is stored in the first storage means (17) together with the data of the block. An error flag indicating whether or not an uncorrectable error is detected in the block by decoding by the error correction means (4) is stored in the second storage means (8), and then the error flag is stored in the second storage means (8).
Regarding the same error correction code block transmitted or recorded or reproduced from the first time onwards, only the blocks whose errors were corrected or no errors were detected by the error correction means (4) are stored in the first storage means (17). The checking means (19) has a configuration for controlling the checking information to be written in the block, and the checking means (19) writes the checking information generated by the checking information generating means (5) of the block that is transmitted or reproduced from the second time onwards and in which no uncorrectable error is detected. The test information and the control means (20) are used to store the test information in the first storage means (17).
), if the inspection information of the previously transmitted or reproduced block does not match, the error flag stored in the corresponding location of the second storage means (8) is inverted and re-stored. A code error correction device comprising: 4. The checking means (19) reads out from the first storage means (17) the checking information of the blocks that have been transmitted or reproduced from the second time onwards and in which no uncorrectable error has been detected, and the control means (20). The test information of the same block previously transmitted or reproduced does not match, and the error flag of the block stored in the relevant location of the second storage means (8) indicates that there is no uncorrectable error. 4. The code error correction apparatus according to claim 3, wherein the code error correction apparatus is configured to rewrite the error flag to a value indicating that an uncorrectable error exists only when the error flag is detected.