JPH0632170B2 - Code processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Use of the Invention] The present invention is intended to prevent an error correction operation from being erroneous when a time axis correction operation is erroneous in a digital recording / reproducing apparatus involving a time axis variation such as a digital VTR. The present invention relates to the code structure of.

[Background of the Invention]

Conventionally, as a method of correcting an error in a digital VTR, there is a method called, for example, an erasure correction as shown in FIG. 1, in which two kinds of error detection codes or error correction codes are combined and the position of the error code is searched for and corrected. However, in this case, one kind of each code word is fixedly used. In Fig. 1, blocks 9, 18, 27,
The shaded part up to 63 is the parity of the error detection code A, and the shaded parts up to blocks 55, 56, 57, ..., 62 is the parity of the error correction code B. Here, the detection parity 9 detects the presence or absence of an error regarding the blocks 1 to 8. Similarly, Parity 18 is block 10-17.
Up to now, 27 performs error detection in the lateral direction with 19 to 26, respectively. On the other hand, error detection parity 55 is block 1,
An error correction operation is performed for 10, 19, 28, 37, and 46. Similarly, the correction parities perform the error correction operation in the vertical direction such as 56 for blocks 2, 11, ..., 47.

Therefore, the blocks 2, 11, 20, 29, 38, 4
Errors up to 1 block of 7 can always be detected by parity 56.

Here, it is assumed that the block 20 makes a mistake. In that case,
The error in the column of the parity 56 can be determined by the correction code B, but at the same time, the error by the parity 27 in the row of the parity 27 can also be determined by the detection code A. In this way, the block 20 can be identified as erroneous, and the position of the error can be known. If the position is known, that is, the error in the position can be corrected by the error correction code. This is called erasure correction. Erasure correction is often used because it can correct up to twice the correction capability of error correction code and is efficient, but if only one row or column error is not detected, it cannot be corrected and must be corrected. The area that does not exist expands. That is, when the recording / reproducing system has a time-axis fluctuation, it is necessary to process the time-axis fluctuation by a memory or the like to remove the time-axis fluctuation, but if a malfunction occurs at this time, the damage is great. For the sake of simplicity, it is assumed that the correction range of the time axis corrector is 18 blocks and the highest address of the memory corresponds to even and odd of each row. That is, the first row 1-
The 9th block is written in the portion where the memory highest address is 0, and the 10th to 18th blocks in the second row are written in the portion where the memory highest address is 1.

Here, if the block number is missed in block 19, all the data of blocks 19 to 27 are written in the part where the highest address is 1, and the highest address is 0.
The data of one cycle before, that is, the data of blocks 1 to 9 will be left in the portion. At this time, since the parities 9 corresponding to 1 to 8 are correct, no error is detected by the error detection code A, and it is determined that there is no error. On the other hand, since the error detection parities 55 to 62 are errors within one block, it is determined that all columns have errors. However, since the lines cannot be limited, block 1
There is no choice but to perform the retouching operation (interpolating with a very similar signal) for all up to 53.

Even if the block number is mistakenly jumped to an irrelevant address, the correct data will be replaced with the data of another address, and the same is true. This can be largely prevented by providing a protection circuit so that the block number sequence is not disturbed. However, when the data is reproduced discontinuously, for example, a VTR of a method called a segment type VTR
In the case of, the head rotates multiple times to reproduce one screen. That is, since the data is cut off only for the head switching time, effective protection cannot be performed at the data restart point.

[Object of the Invention]

An object of the present invention is to eliminate the above-mentioned drawbacks and to realize a code processing circuit for always detecting the position even if the time axis correction is erroneous.

[Outline of Invention]

In the present invention, even if the parity in the row direction is exchanged with the data as a pair, it is possible to detect that the parity has been exchanged and determine that it is an error.

More specifically, in the present invention, the recording system is provided with means for generating the parity of the error detection code or the error correction code for each row and each column of the data block matrix and adding the parity to the codeword string to be recorded. In the reproducing system, a time axis corrector for temporarily storing the read code word string in the storage means to correct the time axis fluctuation of recording / reproducing, and reading the read code word string, and the data and parity of the time code corrected read code word string. In a digital recording / reproducing apparatus provided with a parity checker for determining an error position from the time axis corrector, a means for sequentially generating a plurality of types of code patterns with a repetition cycle longer than the processing unit of the time axis corrector, and at least the time axis corrector. Installed before
A first arithmetic unit for adding the code pattern to a codeword string to be recorded or reproduced, and a code before addition by adding the code pattern again to the codeword string output from the time base corrector. A second arithmetic unit for restoring a word string, wherein the parity checker determines an error position from the data and the parity of the output of the second arithmetic unit. .

According to this configuration, the content of each code word input to the time axis corrector is converted by the first arithmetic unit, but the same code pattern is added again by the second arithmetic unit. Unless there is an error in the corrector, the original codeword before conversion is restored. The addition referred to here is modulo-2 addition. On the other hand, if the time axis corrector fails to write the code word string in a row of the data block matrix, the content of the storage means of the time axis corrector remains the code word string of the previous writing cycle. Become. This codeword string is already added with the code pattern of the first arithmetic unit, but a code pattern different from this is added in the second arithmetic unit, so the original codeword string is not restored. Therefore, the parity checker detects that this line is a narrative. That is, even if there is an error in the time axis corrector, the error position can be specified.

Example of Invention

 The present invention will be described in detail below with reference to examples.

As described above, according to the present invention, the first arithmetic unit for converting the code word string by adding the cyclic code patterns is provided at least before the time axis corrector of the recording / reproducing system, and the output side of the time axis corrector is provided. A second arithmetic unit for restoring the original code word string is provided. The first arithmetic unit may be provided in the encoder that generates the recording codeword string, that is, on the recording side or the reproducing side. In the embodiment described below with reference to FIGS. 2 and 3, the first arithmetic unit is provided on the recording side. FIG. 2 shows the main part of the encoder of the recording system of the embodiment. Input data 64
Is data for which the parity calculation of the correction code B has already been completed. That is, the parities in the row direction of the blocks 55 to 62 in FIG. 1 have already been generated and added to the code word string. The sign of the data 64 is inverted by the calculator 65-1 (first calculator) in accordance with a certain rule, and is guided to the calculator 69. The arithmetic unit 69 and the one-block delay memory 68 are for generating the parity (error detection code A) of each row of the data block matrix such as the blocks 9, 18, and 27 in FIG.

In the arithmetic operation of the arithmetic unit 69, the sign of the operation is, for example, CRC.
(Cyclic redundancy check code) or the like may be used. In this case, the arithmetic unit 69, when given the code word of the first block (for example, block 1 in FIG. 1) of each row from the arithmetic unit 65-1, divides it by a specific 8-bit code, The quotient is stored in the 1-block delay memory 68. Next, given the code word of the second block, add the previous quotient to it,
The sum is again divided by the 8-bit code. By repeating this operation cycle eight times, the parity (error detection code A) of the row is generated.

Next, the calculation contents of the calculator 65-1 will be described in detail. For this calculation, for example, if all 8 bit parities are to be inverted, a calculation of adding a pattern of 11111111 will be performed. If the first half is to be inverted, it is 11110000, if the second half is to be inverted, 00001111, if not inverted at all, 00
It suffices to perform an operation for adding the patterns represented by 000000. At least, the polynomial that generates the parity should not be able to divide these sign inversion patterns. On the other hand, the address counter 71 that counts down the word clock 70 is reset once in one field.
In response to 2, the address 73 for one field is output, the address of the programmable ROM 74 is created, and the operation switching control signal 75 and the parity / data switching switch control signal 76 are output.

The operation switching control signal 75 is sequentially switched each time the block row changes to select four kinds of operation methods. Therefore, the parities 9, 18, 27, ..., 63 for each row are the parities calculated by the sequences whose sign-inverted sequences are different. Next, the data 78 from the buffer memory 77 for compensating the time required for the above processing and each parity 79 are selected by the switch 80 and spliced. This switching is controlled by the switch control signal 76 described above. The code word thus constructed is shown in FIG.
5 is the same as the generation method, but different from the others. Similarly, 18
And 54 and 27 and 63 are the same. In this way, the code word string whose contents are converted by adding the code patterns and which is added with the parity is recorded on the magnetic recording medium by the magnetic head.

FIG. 3 shows the main part of the reproducing-side compounder of the magnetic recording / reproducing apparatus of the embodiment. The reproduction data 81 read from the magnetic recording medium is written in the time axis corrector 84 according to the address 83 generated by the address generator 82 from the synchronization pattern and block number in the data. Reading is performed sequentially according to the read address starting at reset 72.
On the other hand, the address generator 82 simultaneously outputs the operation control signal 75 that changes for each row. The arithmetic unit 65-2 (second arithmetic unit) is controlled by the arithmetic control signal 75, and the arithmetic unit 65-1 of FIG. 2 respectively operates on the code word string of each row of the data block matrix (FIG. 1). The signs of the same pattern as the added ones are added again. That is, the operation corresponding to each row, that is, the sign inversion which is different for the input data is performed for each row. The sign-inverted data 85 after the calculation is subjected to a parity calculation by a parity checker 86, and if an error is detected as a result, it is output as an error flag 87.
Further, the data 88 in which the delay amount of the arithmetic unit 69 and the parity checker 86 is corrected by the buffer memory 89 is also sent to the next error detection processing circuit.

Next, the operation when the time axis correction is incorrect will be described. For example, it is assumed that the lines of blocks 19, 20, 21, ..., 27 are erroneously written in the lines of blocks 10, 11, 12 ,. At this time, the data inversion of the parity 27 is 8
It is made up of the code sequence of only the last 4 bits among the bits. On the other hand, the parity 18 is assumed to have the data inversion made from the code sequence of only the first 4 bits of the 8 bits. Incorrect block 10, 11, 12, ………, 1
Since it was written in 8, block 19, 20, .........,
The data of 26 is subjected to a parity check from the first half 4-bit inverted data, and as a result, it can be determined as a code error. Further, since the row of the block is erroneous, the writing is not performed and it is regarded as the parity 27 and is read out is actually the parity 9 which is the signal one cycle before the time axis corrector, and the blocks 1, 2, 3 , ..., 8 are all data whose polarities are inverted, and the parity 9 is calculated.
However, in this case, the parity detection is performed on the data whose polarity is inverted in the last 4 bits, so that
It can be detected as a code error. Therefore, the correction code B is determined to be erroneous in all columns, but the positions are 10, 11, ..., 18, rows and 19, 20 ,.
Since it can be limited to 27 lines, it is not necessary to modify all the data, and only two lines are needed.
If the line is not written at all, but the line is not written by mistake, the error line is only the line of Parity 27, so the error can be identified and all can be corrected.

In the above description, an error detection code is used for each row of the data block matrix, and an error correction code is used for each column. However, both may be error correction codes or both may be error detection codes. Alternatively, the same idea can be applied to a chain structure in which the matrix is further n-fold.

The same applies when correction using a combination of a correction code and a pointer is used. Furthermore, plural types of random data for scrambling processing may be prepared and switched as a polarity inversion pattern. Alternatively, only the start timing of scrambled data may be changed between rows.

Further, it goes without saying that it is also possible to perform the parity calculation with the input data as it is, and to invert the polarity for each row only for the parity portion. In addition, it is not always necessary to perform the first code polarity reversal process with a different pattern for each row on the encoder that generates the code word string to be recorded on the magnetic recording medium, that is, at the time of reproduction. It is sufficient to perform the processing at least before the time axis corrector and detect the error by the same method after the time axis correction. That is, in the illustrated embodiment, the first calculator 65-1 provided in the encoder shown in FIG. 2 may be provided immediately before the time axis corrector 84 shown in FIG. However, there is a risk that this process may be mistakenly performed. Also, ROM for parity calculation
In the case of performing the above, etc., it can be realized by preparing a plurality of types of tables corresponding to the polynomials of the parity calculation and similarly switching the addresses and the like.

〔The invention's effect〕

As described above, according to the present invention, even if an error in time axis correction occurs during reproduction, the error portion cannot be detected without fail and the addition of hardware required for that is very small (control P
There are 1 to 2 ROMs and 2 to 4 EXCL USIVE OR gates. ).

[Brief description of drawings]

FIG. 1 is a diagram for explaining an erasure correction method, and FIGS. 2 and 3 are configuration diagrams of an embodiment of an encoder and a signal device of a code processing circuit according to the present invention, respectively. 65, 66, 69 ... Arithmetic unit, 71 ... Address counter, 74 ... ROM, 77, 89 ... Buffer memory.

Claims (1)

[Claims] 1. A recording system is provided with means for generating a parity of an error detection code or an error correction code for each row and each column of a data block matrix and adding the parity to a code word sequence to be recorded, and the reproducing system is A time axis corrector for temporarily storing the read code word string in the storage means and then reading the read code word string in order to correct the time axis fluctuation of the recording / playback, and determining the error position from the data and the parity of the read code word string subjected to the time axis correction. In the digital recording / reproducing apparatus including the parity checker, the means for sequentially generating a plurality of types of code patterns with a repetition period longer than the processing unit of the time axis corrector, and at least before the time axis corrector are provided. , A first arithmetic unit for adding the code pattern to a code word sequence to be recorded or reproduced, and the code pattern to the code word sequence output from the time base corrector. And a second operator to restore the code string before the addition by adding the down again, the second
A code processing circuit characterized by determining an error position from the data and the parity of the output of the arithmetic unit.