JPS60101766A - Address detection system - Google Patents

Abstract

PURPOSE:To perform securely highly reliable address detection for correcting an address error by sending out a load pulse and a clock for address changing to an address counter according to the error detection result of address information. CONSTITUTION:An error detecting circuit 1 detects whether an input address (a) has an error or not, and an error flag (d) is set to a high or low level according to whether the error is present or not. Then, a clock generator 3 applies the load pulse (e) to the address counter 4 with a synchronizing signal passed through a delay circuit 2 synchronously with the address (a) unless the error is present. When the error is detected, on the other hand, the last correct address is increased by one by the address counter 4 with a clock (f) outputted by the generating circuit 3 and the error is corrected securely to output the address from the counter 4. Consequently, the high-reliability address detection for correcting securely the error of the address is performed.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to an address detection method for a recording/reproducing device that uses a format with continuous addresses, such as an optical disk, magnetic disk, or magnetic tape, and particularly relates to an address error detection/correction function. Regarding.

Prior Art If there is an error in the address part of an optical disk, magnetic disk, magnetic tape, etc., there is a risk that erroneous data may be input or output. Particularly in optical discs, random errors often occur. Therefore, the cyclic redundancy check code CRC (
Cyclic Redundancy Check C
Methods such as adding an error detection code such as ode) and adding an error correction code have been considered. However, even if errors can be detected using the cyclic redundancy check code CRC, the original correct address cannot be inferred. Further, even if an error correction code is added, if many errors occur in the address part, they cannot be corrected, and even if they are correctable, the correction procedure becomes complicated. In addition, even if addresses are interleaved in data in order to be robust against burst errors (a group of error bits in which the number of correct bits between two adjacent error bits is less than a specified number), unrecorded sectors The disadvantage is that it is not useful when searching for an address.

Purpose An object of the present invention is to eliminate the drawbacks of the prior art as described above, and to provide a highly reliable address detection method that detects and corrects address errors and outputs them.

composition Hereinafter, one configuration example of the present invention will be described based on the drawings.

FIG. 1 shows an optical disk, a magnetic disk, and a magnetic disk used in the present invention.
FIG. 2 is a diagram showing an example of the configuration of sectors of a magnetic tape or the like. A preamble (consisting of 40 consecutive zeros) is written at the beginning of each block and is used to create a synchronization clock for the next data. There are various synchronization methods, but the synchronization signal usually has sufficiently high reliability against address errors. Also, the address has a CRC
Error detection codes and error correction codes are added to improve the reliability of addresses.

FIG. 2 is a block diagram showing an example of the configuration of the present invention.

The error detection circuit 1 sets the error flag d to H when there is an error in the input address signal a. As is clear from the sector format in FIG. 1, address signal a is normally output later than the synchronization detection signal, so
The synchronization detection signal A is input to the delay circuit 2 for the purpose of timing with the address signal A. Clock generation circuit 3
is, the error flag d indicates L for the address signal a synchronized with the input delayed synchronization signal C, and the address is tKξ.
If there is no error, a load pulse e is generated to load the correct address into the address counter 4.

When the error flag d becomes H, indicating that an error has occurred in the address, a clock for counting up is sent to the address counter 4. Next, explanation will be given using the timing chart shown in FIG.

Address signal a increases one by one from n-1, and it is assumed that an error has now occurred at address n+1. As shown in the delayed synchronization signal C, the synchronization detection signal A is time-adjusted by the delay circuit 2 to a position synchronized with the address signal a. , in the figure, n + of address signal a
Since there is an error in the part corresponding to 1, the error plug d becomes [■] in that part. On the clock generation date wt3, the clock f is output in synchronization with the rise (H) of the error flag d, and when the error flag d is L, a load pulse e is output for loading the address signal a as is. The address counter 4 outputs the address signal a sent in response to the load pulse e as it is as an address output signal g. On the other hand, when the clock f for raising the address signal a from 1 to 1 is sent, in this case, an error has occurred at n+1, so this clock f causes the address counter 4 to change from n to n+1.
It is counted up and becomes the address output signal g.

At this time, the address counter 4 receives the correct address signal a (in this example,
Needless to say, n) is counted.

FIG. 4 is a block diagram showing another configuration example of the present invention.

This configuration example is a configuration example that can deal with a case where it is impossible to detect a synchronization signal. That is, the internal synchronization generating circuit 5 is provided before the delay circuit 2 shown in the second I solo. Even if an error occurs in the input synchronization detection signal, the internal synchronization generation circuit 5 counts the bit synchronization signal and generates a pulse at the original pulse position of the synchronization signal, and outputs it as a normal synchronization output signal i. Output to delay circuit 2. In this way, by always keeping the synchronization signal normal, it is possible to detect addresses without errors.

The configuration other than the internal synchronization generating circuit 5 is exactly the same as that of the embodiment shown in FIG. 2, and the timing chart is also exactly the same as that of FIG. 3 except that the synchronization output signal i plays the role of the synchronization detection signal. be.

Effects As explained above, according to the address detection method of the present invention, the clock or load pulse can be synchronized with the address information using means for detecting an error in address information and whether or not there is an error in the address information. and an address counter that loads the address information as it is by inputting the load pulse and changes the address value by inputting the clock, thereby detecting and correcting address errors and outputting them. It is possible to realize a highly fre- sive detection method.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a sector format applied to the present invention. FIG. 2 is a block diagram showing one embodiment of the present invention, FIG. 3 is a timing chart of FIG. 2, and FIG. 4 is a block diagram showing another embodiment of the present invention. ■=Error detection circuit, 2: Delay circuit, 3: Clock generation circuit, 4 Near address counter, 5: Internal synchronization generation circuit. Patent Applicant: Ricoh Co., Ltd. - Representative Patent Attorney Masatoshi Isomura No. 3 Figure 4 Amendment to Figure Proceedings (Voluntary) December 16, 1980 4゛6 Director-General of the Agency Mr. Kazuo Wakasugi 1 Indication of the Case Showa 1958 Patent Application No. 209448 2, Ji Ming's name Address detection method 3, Person making the amendment P1 Relationship Patent applicant address 1-3-6 Nakamagome, Ota-ku, Tokyo @
(f', 4) ``'' Ricoh Co., Ltd. - Representative Hama 1) Hiro 4, agent name < δ,! Number of inventions increased by amendment None 6, -?
! In the "Detailed Description of the Invention" of the specification to be amended, "Preamble (consisting of 40 consecutive zeros) j" on page 5, lines 10-11 of the specification is corrected to "Preamble". ■ Correct "Click for synchronization of the next busy data" on lines 11-12 of page 3 to "Clock for bit synchronization".

Claims (1)

[Claims] (1) A means for detecting an error in address information in an optical disk, magnetic disk, magnetic tape, etc., and emitting a clock or a load pulse in synchronization with the address information, depending on whether or not there is an error in the address information. and an address counter for loading the address information as is by inputting the load pulse and changing the address value by inputting the clock.