JPS62256270A - Error correction device - Google Patents

Abstract

PURPOSE:To improve the error detection/correction capability by deciding an error data group of a block address of a recovered data as a missing block, feeding the result to a decoder of the next stage as missing location information for the calculation of missing. CONSTITUTION:Error codes C1, C2 are added to the 1st and 2nd series of a data word group, a block address BA is added along with the 1st series and the result is recorded on a recording medium. The reproduced data from the medium is fed to a RAM 11 and a BA detection circuit 12, the circuit 12 detects a BA from the reproduced data and outputs it to the RAM 11 and a missing block decision circuit 13. The circuit 13 decides whether or not the BA is reproduced correctly and gives the result to a C2 decoder 14. The 1st, 2nd series data of the RAM 11 are subject to error correction by a C1 decoder 16 and the C2 decoder 14 and the corrected information is sent to an interpolation deciding circuit 17. The circuit 17 decides whether or not data is to be interpolated from the corrected information F1, F2 and gives the result of discrimination to an interpolation circuit 15. The circuit 15 uses a signal from the circuit 17 to interpolate the data from the RAM 11 and outputs the result.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an error correction device used for recording and reproducing digital data in digital audio tape recorders, digital video tape recorders, and the like.

[Prior art and its problems] In this type of error correction device, when double error correction codes are attached to data, each of the first and second error correction codes constitutes an individual error correction block. Therefore, even if error correction is not possible with one of the error correction codes, the error can be corrected using the other error correction code, and therefore the error correction ability can be further improved.

It is possible to correct up to 2 word errors within one block by casting.
When the error location is known and an error correction code with a distance of 5 that can correct up to 4 word errors is used, up to 2 word errors are corrected during first stage decoding, and errors of 3 words or more are detected. In this way, by using this error state information and performing an erasure operation during the next stage of decoding, it is possible to significantly reduce the risk of error detection and correction being overlooked and erroneous correction.

In addition, in a digital audio φ tape recorder, a digital video tape recorder, etc., digital data is once written in a RAM, and a first error correction is performed on a first series of a plurality of data word groups written in this RAM. At the same time, a second error correction code is added to the second series, and recording is performed on the magnetic tape along the first series. At this time, a block address is added and recorded for each first error correction block. When reproducing the magnetic tape, a block address is detected from the reproduced data, data is again written into the RAM based on this block address, and errors are corrected using the first and second error correction codes. Therefore, if this block address is incorrect,
Since it is impossible to even detect it on the first stage decoder side,
Depending on the correction ability of the next-stage decoder, it was not possible to correct block address errors when the correction ability range was exceeded.

By the way, if the information when the block address is incorrect is reflected in the erasure information on the next-stage decoder side, it becomes possible to use this as location information, and the correction ability can be improved.

[Object of the invention] This invention was made in view of the above-mentioned circumstances.
It is an object of the present invention to provide an error correction device that has high error correction ability and can reduce errors in error detection and correction or errors in correction.

[Summary of the Invention] The present invention comprises a erased block determination circuit made of a simple circuit, and sends the output of the erased block determination circuit to the next stage decoder as erasure location information on the next stage decoder side. This is used to perform the disappearance calculation.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

Here, an error correction code of C1 is added to the first series of the data word group, an error correction code of C2 is added to the second series, and block addresses of O to 127 are added along this first series. is recorded on a recording medium such as a magnetic tape. Note that the error correction codes C1 and C2 are Reed-Solomon codes with a distance of 5.

FIG. 1 shows the circuit configuration of this error correction device. Reproduction data from the recording medium is sent to the RAM 11 and also to the block address detection circuit 12.

The block address detection circuit 12 detects a block address from the transmitted reproduction data, and transfers the detected block address to the RAM 11 and the erased block determination circuit 1.
Output to 3. In the RAM 11, reproduced data is written in the format shown in FIG. 2 for each error correction block from 0 to 127 according to the block address from the block address detection circuit 12. The erased block determination circuit 13 uses a configuration described later to determine whether or not the block addresses sequentially input from the block address detection circuit 12 are correctly reproduced.The erased block flag indicating the determination result is transmitted to the C2 decoder. Send to 14th. The data written in the RAM 11 is error-corrected by the C1 decoder 16 and the C2 decoder 14, and then read out to the interpolation circuit 15. The C1 decoder 16 has a RAM 11
Error correction is performed on the data read from the first series, that is, for each block, and the corrected data is sent back to the RAM 11, and information indicating the correction state is held as a flag F1 for each block. It is sent to the C2 decoder 14 and the interpolation determination circuit 17. The C2 decoder 14 uses C! In substantially the same manner as the decoder 16, data is corrected according to the second series, and information indicating the correction state -0- is held as a flag F2 for each block and sent to the interpolation determination circuit 17. Interpolation judgment circuit 1
7 is the flag F1 from the C1 decoder 16 and the C2 decoder 1
It is determined whether or not to perform data interpolation based on the 7 lags F2 from 4 to 7, and the determination result is output to the interpolation circuit 15. Then, the interpolation circuit 15 performs pre-interpolation or average value interpolation on the data sent from the RAM 11 based on the signal from the interpolation determination circuit 17, and the interpolated data is sent to the next stage for D/A conversion (not shown). output to the device.

Next, a detailed configuration of the lost block determination circuit 13 for detecting a lost block address from block addresses sent from the RAM 11 will be explained with reference to FIG. As shown in the figure, the erased block determination circuit 13 includes a set circuit 131, a set circuit 132, a first latch circuit 133, a second latch circuit 134, and a judge circuit 135.

The block address from the block address detection circuit 12 is first sent to set circuits 131 and 132.

According to the input block address, the set circuit 131 sets the first 128 bits according to the number of block addresses.
A flag "1" is set in the corresponding bit position of the latch circuit 133. The set contents of the first latch circuit 133 are sent as they are to the set circuit 132 and the judge circuit 135. Like the first latch circuit 133, the set circuit 132 calculates the block address number according to the block address input from the block address detection circuit 12 and the setting state of the flag at the corresponding bit position of the first latch circuit 133. A flag 1 is set at the corresponding bit position of the 128-bit second latch circuit 134 according to the flag. The contents of this second latch circuit 1340 are sent to the judge circuit 135. Judge circuit 135
is composed of, for example, an exclusive NOR circuit, and includes a first latch circuit 133 and a second latch circuit 1.
A lost block flag indicating whether there is a block to be deleted is output to the next stage C2 decoder 14 according to the flag at the same bit position in 34.

Next, the operation of the above embodiment will be explained.

The raw data is stored in RAM 11 and block address detection circuit 1.
2, the block address detection circuit 12 detects the block address from the transmitted reproduced data and outputs the detected block address to the RAM 11 and the erased block determination circuit 13.

The RAM 11 writes reproduced data in accordance with the block address from the block address detection circuit 12 for each error correction block from 0 to 127 in a format as shown in FIG. The data word written to this RAM 11 is then read out to the C1 decoder 16. C! The decoder 16 performs a predetermined syndrome calculation on the data words read from the RAM 11 for each block, that is, from the vertical direction in FIG. It detects the number of errors, calculates the amount and position of the error, and corrects up to 2-word errors. Then, the corrected data is stored in RAM1.
1 and rewrites it, and sets the flag F1 indicating the correction status to o'' in the case of no error, single error, or double error, and 1'' in the case of triple or more errors (uncorrectable). This flag F1 is held for each block and is output to the C2 decoder 14 and the interpolation determination circuit 17.

On the other hand, in the lost block determination circuit 13, RAM
11, the set contents of the first latch circuit 133 and the second latch circuit 134 are reset. The set circuit 131 to which the block address from the block address detection circuit 12 is input is configured to select the first latch circuit 13 according to the input block address.
Set 7lag 1' in the corresponding bit position of 3. The set contents of this first latch circuit 133 are set circuit 1
32 and the judge circuit 135. When a block address is input from the block address detection circuit 12, the set circuit 132 determines whether a flag "1" has already been set in the corresponding bit position of the first latch circuit 133 having the same value as this block address. If it is determined that 7 lag '1'' has already been set in the corresponding bit position of the first latch circuit 133, that is, if the same block address is detected from the block address detection circuit 12 at least twice. When the same block address is sent, a flag "1" is set in the corresponding bit position of the second latch circuit 134 to indicate that the same block address has been sent. The set contents of this second latch circuit 134 are sent to a judge circuit 135. The judge circuit 135 determines whether or not there is a block to be erased depending on the state of the flag of the bit at the same position in the first latch circuit 133 and the second latch circuit 134. This means that the set circuit 131 and the set circuit 132 have correctly consecutive block addresses of 12 from 0 to 127.
When 8 blocks have been read, the flag ``1'' is set in all the registers of the first latch circuit 133, and the flag ``1'' is not set in each bit of the second latch circuit 134, and all are 0. '', the erased block flag output by the judge circuit 135, which is an exclusive NOR circuit, for each bit output of the first and second latch circuits 133 and 134 is 0''. Furthermore, if the block addresses read out to the set circuit 131 and the set circuit 132 are not consecutive and an intermediate block address is handled, the first latch circuit 1
The flag 1" is not set in the corresponding bit of 33 and becomes "0", and similarly the flag "1" is not set in the corresponding bit of the second latch circuit 134 and becomes "0°". Become.

Therefore, in this case as well, the lost block flag output by the judge circuit 135 is 1''. Furthermore, if the block addresses read out to the set circuit 131 and the set circuit 132 overlap twice or more, the set circuit 132 determines this and sets a flag in the corresponding bit of the second latch circuit 134. 1" is set. At this time, the corresponding bit of the first latch circuit 133 is set to "1", so in this case, the output signal of the judge circuit 135 becomes 111 I+.

Now, in the C2 decoder 14, in the same manner as the C1 decoder 16, the position and amount of errors in the second series, that is, the data words along the horizontal direction in FIG. 2 are detected and corrected. At this time, for correction, first determine whether error correction is possible without using acalculation, that is, whether or not there are up to two erroneous data words, and if it is determined that it is possible. Correct up to 2 word errors as is. If it is determined that this is not possible, then the C1 decoder 16 uses the 7-lag F1 from the C1 decoder 16 to determine whether or not there are three or less error locations that cannot be corrected. If there are three or less locations, the location is deleted and a disappearance calculation is performed. If the data word error correction by this erasure calculation fails, the erased block flag from the erased block determination circuit 13 uses the duplicated or skipped block address as erasure information, and C! On the decoder 16 side, it is determined whether the sum of the location of the uncorrectable error and the overlapped or skipped block address is 4 or less. If there are 4 or less,
The erasure calculation is performed again using that part as the error location. If the error correction fails here as well, it is determined that the error cannot be corrected, and the flag F2 is set to 1" and sent to the interpolation determination circuit 17. In the interpolation determination circuit 17, R
7 lag F1 from C1 decoder 16 and flag F from C2 decoder 14 for successive data words from AM11.
2, it is determined whether or not to perform interpolation, and the determination result is sent to the interpolation circuit 15. As a result, the interpolation circuit 15 performs pre-interpolation or average value interpolation as appropriate on the data sent from the RAM 11, and this completes the processing of this error correction device, and the data after the interpolation process is transferred to the next stage. output to the D/A* converter.

[Effects of the Invention] As described in detail above, according to the present invention, the lost block determination circuit is configured with a simple circuit, and the output of this lost block determination circuit is used as lost location information on the next stage rear device side. Since the data is sent to the next-stage decoder and used to perform erasure calculation, the error correction ability is high and it is possible to further reduce error detection and correction oversights and erroneous corrections. A correction device can be provided.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention; FIG. 1 is a block diagram showing the overall circuit configuration, FIG. 2 is a diagram showing the format of data written to the RAM, and FIG.
FIG. 2 is a block diagram showing a detailed circuit configuration of a lost block determination circuit in the figure. DESCRIPTION OF SYMBOLS 11... RAM, 12... Block address detection circuit, 13... Lost block determination circuit, 131, 13
2... Set circuit, 133... First latch circuit,
134... Second latch circuit, 135... Judge circuit, 14... C2 decoder, 15... Interpolation circuit, 1
6...C1 decoder, 17...Interpolation determination circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] Digital data is divided into a plurality of data word groups, a first error correction code is added to a first series of the data word groups, and each first series of the data word groups is A block address is added to a block address, an error correction code, and first and second error correction codes are recorded on a recording medium along a first sequence, and when this recording medium is played back, the first and second error correction codes are
In an error correction device that performs error correction on a data word using an error correction code of a first decoder that performs error correction on a first series of data words; and a first decoder that performs error correction on a first series of data words. A second decoder performs error correction using the error state detected by the first decoder and the erasure block information determined by the erasure block determination circuit.
An error correction device comprising: a decoder.