JPS61283078A - Decoding device for error correcting code - Google Patents

Abstract

PURPOSE:To shorten a correcting time at correcting processing by writing the data of '0' by all bits to the first memory, in which the data are stored, before the data are fetched. CONSTITUTION:When the error of the data coded through an error correcting circuit 15 is corrected, by the prescribed means, before the data are fetched to the first memories 10 and 11 in which the data are stored, all bits write the data of '0'. Reproducing data only, which is judged to be correct by the error detection of a CRC code, etc., are written to the first memories 10 and 11, and the pointer corresponding to the written reproducing data is cleared. When the error is corrected in such a condition, in order to correct one error symbol identified by the pointer, the obtained syndrome itself comes to be the correct symbol after correction, the number of steps of the error correction routine can be decreased and the correcting processing time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding device for error correction codes used in digital recording/reproducing devices, digital disks, and the like.

[Summary of the invention]

The present invention is an error correction code decoding device that uses a pointer formed by an error detection code such as a CRC code, and performs error correction by a pointer laser method, in which data is taken into a first memory in which the data is stored. By writing data in which all bits are "O" into this first memory, the correction time during correction processing is shortened and the hardware for correction is simplified.

[Conventional technology]

In a digital recording/reproducing device that records/reproduces a digital audio signal, two simple parity sequences (referred to as a P sequence and a Q sequence, respectively) are formed in diagonally different directions of a two-dimensional array of audio data. , C as an error detection code in the vertical direction of this two-dimensional array
A cross-interleave code for encoding an RC code is known. Decoding of this error correction code is first performed using C
Error detection is performed using an RC code to form a pointer indicating the presence or absence of an error, and this pointer information is used to perform pointer radar decoding that alternately performs decoding for P sequences and decoding for Q sequences. .

That is, correction is performed only when one symbol in each of the P and Q sequences is an error, and the pointer for the corrected symbol is cleared. In this way, the accuracy of the pointer is important in the pointer registration method, so
Conventionally, a method has been adopted in which all pointer areas in a memory are set to an error state before reproducing data is taken in, and the pointers are cleared only for symbols that are determined to be correct as a result of CRC code decoding.

For example, when one P sequence is formed by eight symbols WO to W7 and a parity symbol P, the parity symbol P of the simple parity code is generated so as to satisfy the following equation.

WO■W1■W2■W3■W4■W5■W6■P-0 (However, ■ means the addition of IIIod, 2, and is specifically realized by an exclusive OR gate.) Reproduction data If, for example, W3 of this series in the series becomes an error, that is, W=W3+E (where E: error pattern), only the pointer related to W3 is set, the pointers of the remaining symbols in the series are cleared, and the syndrome is determined by the following formula. S is calculated.

5-WO■W1■W2■W3■W4■W5ΦW6■W7
(2) PE Therefore, error correction is performed by the calculation (W3 (5) = W3). In this manner, in the conventional simple parity code correction routine, the syndrome S is obtained for each series of received data, and the syndrome S and the error symbol are added (sod, 2).

[Problem that the invention seeks to solve]

In the case of one-error correction in which a simple parity code can correct an error, a conventional decoding device calculates an error pattern E by calculating a syndrome, and calculates the error pattern E by calculating a syndrome.
is added to the error word pointed to by the pointer (sod
, 2) I tried to do it.

The object of the present invention is to perform the step of calculating the syndrome and adding the syndrome to the error symbol (sod).

2) To provide an error correction code decoding device that can combine two steps into one step, thereby shortening correction time or reducing the scale of hardware. be.

According to this invention, since the correction time can be shortened, the number of times of decoding within a predetermined time can be increased in the case of a cross-interleaved code that alternately performs decoding for P sequences and decoding for Q sequences. , error correction ability can be improved.

[Means for solving problems]

The present invention includes a first memory 10.11 that stores data encoded by a simple parity code, and a second memory 12.11 that stores a pointer indicating whether or not there is an error in the data.
13, an error correction circuit 15 that corrects errors by a pointer laser method using the data stored in the first memory 10.11 and the pointer stored in the second memory 12.13; Before loading data into memory 10.11, first
This is an error correction code decoding device characterized by comprising means 22, 23 and 31 for controlling data such that all bits are written in the memory 10 and 11 of 0 degrees.

[Effect]

According to this invention, the first memory 10 for storing data
．． When reproducing data is taken into the first memory 10 and 11, data in which all bits are 0' is written into the first memory 10 and 11 during a free time before that.

Then, only the playback data determined to be correct by error detection such as CRC code is stored in the first memo IJI0,1.
1 to clear the pointer corresponding to the written playback data. If you perform error correction in this state,
When correcting one error symbol identified by a pointer, the obtained syndrome itself becomes the correct symbol after correction, and the number of steps in the error correction routine can be reduced. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The description of this embodiment is given in the following order.

a. Overall configuration and explanation of error correction code C1 Operation of decoding process d. Description of error correction circuit 15 In this embodiment, a time-axis compressed digital audio signal is recorded on a magnetic tape using a rotating head. It is. Time axis compression is a process for dividing and recording one field of a color video signal and one field of a digital audio signal on one track of a magnetic tape.

a. Overall configuration In FIG. 1, reference numeral 1 indicates a magnetic head having a rotary head configuration, and the reproduction signal of the magnetic head l is transmitted to a CRC check circuit 3 via a rotary transformer (not shown) and a reproduction amplifier 2. supplied to The CRC check circuit 3 performs error detection using a CRC code. Reproduction data output from the CRC check circuit 3 is supplied to terminals a of switch circuits 6 and 7, respectively. This reproduction data transmission path is called a data bus 4.

A 1-bit pointer is formed by error detection for each CRC block in the CRC check circuit 3. A pointer output from the CRC check circuit 3 in synchronization with each word of reproduced data is supplied to each terminal a of the switch circuits 8 and 9. This pointer transmission path is called a pointer bus 5.

Data RAMs 10 and 11 are connected to the switch circuits 6 and 7, respectively. Pointer RAMs 12 and 13 are connected to the switch circuits 8 and 9, respectively. Reproduction data supplied to terminals a of switch circuits 6 and 7, respectively, is written to data RAMs 10 and 11. The pointers supplied to terminals a of switch circuits 8 and 9 are written to pointer RAMs 12 and 13, respectively. Data R
Reproduction data read from AM10 and AM11 is taken out to terminals of switch circuits 6 and 7, respectively. Pointers read from data RAMs 12 and 13 are taken out to terminals of switch circuits 8 and 9, respectively.

Data RAM 10.11 and Pointer RAM 12.1
3, a memory control circuit 14 is provided. The memory control circuit 14 generates addresses for these RAMs, controls read/write timings for these RAMs, and the like. Under the control of the memory control circuit 14, time axis fluctuations are removed and time axis expansion is performed in the data RAMIQ, 11 and pointer RAMs 12, 13.

An error correction circuit 15 is connected to each of the data bus 4 and pointer bus 5. This error correction circuit 15 is
As described later, data RAM l0゜11 and pointer R
Initialize AM12.13 and determine whether error correction is possible for each code series.

Performs processing such as correcting error words and clearing pointers.

Data that has been subjected to error correction processing is stored in data RAM10.
or 11 and supplied to the digital processing circuit 16 via the terminal of the switch circuit 6 or 7. The pointer read from the pointer RAM 12 or 13 is supplied to the digital processing circuit 16 via the terminal of the switch circuit 8 or 9. The digital processing circuit 16 performs processing regarding words that cannot be error corrected. For example, when the words located before and after the error word are correct, the error word is interpolated using the average value of these two words,
Also, when only the previous word is correct, the error word is interpolated with the previous word, and further,
Muting is performed when there is no correct word either before or after the word. Output data from the digital processing circuit 16 is supplied to a D/A converter 17, and a reproduced audio signal is taken out at an output terminal 18.

b. Description of error correction code The error correction code of this embodiment will be explained with reference to FIG. Each column in the vertical direction in FIG. 2 constitutes a CRC block consisting of a total of 10 words, including 8 words of digital audio data and 2 words of parity word, and CRC encoding is performed for each CRC block.
A C code is added. One code block is configured by arranging m CRC blocks. One code block contains, for example, one minute of l-feel digital audio signal.

Two simple parity code sequences P subjected to cross-interleaving that completes within l code blocks.

Q is formed. One P sequence is composed of 8 words of audio data and a parity word P included in different CRC blocks every predetermined number of blocks, as shown by the solid line in FIG.

The other Q sequence includes 8 CRC blocks included in different CRC blocks every predetermined number of blocks, as shown by the broken line in FIG.
It is composed of word audio data and parity words P and Q. Each word of audio data included in one code block belongs to both the P sequence and the Q sequence,
The P sequence and Q sequence are made to be different from each other for each word. When recorded on magnetic tape,
A block synchronization signal and a block address are added to each CRC block.

To decode the error correction code described above, a pointer is formed by detecting an error for each CRC block, and this pointer information is used to decode each P sequence, and then to decode each Q sequence. , and further performs decoding of each P sequence and decoding of each Q sequence alternately.

Increasing the number of times this decoding is performed increases the number of error words that can be corrected.

Operation of C0 decoding processing FIG. 4 shows a decoding operation performed using one field of a color video signal as a temporal division.

In each section a, b, c, and d in FIG. 4, the following operations are performed.

Section a: All clear of data RAM 10 or 11 and all set of pointer RAM 12 or 13 Section b: Loading of playback data into data RAM 10 or 11 and CRC check and pointer clear based on CRC check Section C: Cross interleaving Section of code correction d: Data transfer from RAM 10, 11, 12 or 13 to digital processing circuit 16 In FIG. 4, the shaded section indicates a time margin in consideration of time axis fluctuations.

The operation of this embodiment will be described in detail with reference to FIG. FIG. 4A shows data RAM l0 and pointer RA
FIG. 4B shows the decoding operation performed by the data RAM II and pointer RAM 13. In the field indicated by Fl in FIG. 4, as shown in FIG. 1, switch circuits 6 and 8 select the terminal a side, and switch circuits 7 and 9 select the terminal A side. In the first interval a in FIG. 14 and the error correction circuit 15, pointers are set at all addresses of one code block in the pointer RAM 12 (all pointers are set to .degree.l").

In section b of FIG. 4A, data is reproduced from the magnetic tape by the magnetic head l, and error detection is performed by the CRC check circuit 3. Through the data bus 4 and the switch circuit 6, only error-free data is sent to the data R.
Written to AMl0. At the same time, the pointer corresponding to the error-free data is cleared (set to "0"). In the section b, the digital audio signal of one code block and the pointer are written into the data RAM 10 and the pointer RAM 12.

In the next section C after data capture is completed, the data RAM 10 and pointer RAM 12 are accessed, and the error correction circuit 15 performs error correction. The error-corrected digital audio signal and pointer are output to the digital processing circuit 16 in the section d of the next field F2. In field F1, as shown in FIG. 4B, data RA'MII and pointer RAM1 are stored.
The error-corrected digital audio signal and pointer read from the digital audio signal 3 are output to the digital processing circuit 16.

d. Description of error correction circuit 15 FIG. 3 shows the configuration of an example of the error correction circuit 15. In FIG. 3, an exclusive OR gate (hereinafter referred to as E
(referred to as an X-OR gate) 21, a latch 22, and a bus controller 23 are provided to generate a syndrome. The bus controller 23 controls the data bus 4
and the latch 22. The output of the latch 22 and the word via the data bus 4 are supplied to the EX-OR gate 21, and the output of the EX-OR gate 21 is supplied to the latch 22.

The pointer bus 5 includes a bus controller 24° error counter 26. An error address latch 28 is connected. The bus controller 24 includes an RS flip-flop 2
5 and the pointer bus 5. This bus controller 24 controls whether the output of the RS flip-flop 25 is output to the pointer bus 25 or not. The error counter 26 checks the number of errors in one P sequence or one Q sequence by counting a pointer of "1" for each sequence.

The output of the error counter 26 is supplied to a correction determination circuit 27. It is determined that error correction is possible only when the number of error words in one sequence is one.

The error address latch 28 is supplied with the output of the multiplexer 30. The multiplexer 30 is supplied with the error address latched in the error address latch 28 and an address from the address generation circuit 29 (which is part of the memory control circuit 14). The output of the multiplexer 30 is the data R on the side performing the error correction operation.
AM and pointer RAM.

Furthermore, a timing control circuit 31 is provided which supplies a clear signal to the latch 22 and the error counter 26 and controls setting and resetting of the RS flip-flop dub 25. This timing control circuit 31 generates a clear signal and a set/reset signal in each section a, b, and c in FIG. 4.

In section a in FIG. 4, the latch 22 is cleared and the RS flip-flop 25 is set. All bits of the latch 22 are set to “0” by the bus controller 23.
'' data is output to the data bus 4. The bus controller 24 outputs the 1
The pointer ' is output to the pointer bus 5. The multiplexer 30 selects the address from the address generation circuit 29, and data of all bits 0° is written in the data RAM 10 or 11, and a pointer 1' is set in the pointer RAM 12 or 13.

In section b, the pointer is °'0 in the playback data.
' only data is written to the data RAM 10.11. At the same time, the bus controller 24 is operated by the pointer from the CRC check circuit 3, and when the pointer is at 0°, the 0' pointer from the RS flip-flop 25 is transferred to the pointer RAM 12.13 via the bus controller 24. supplied to

In section C, the bus controllers 23 and 24 are turned off, and the playback data read from the data RAM is
- The pointer is supplied to the OR gate 21 and the pointer read from the pointer RAM is supplied to the error counter 26 and error address launch 28. In this case, the P series and Q
The latch 22 and error counter 26 are cleared for each series. A syndrome is generated by EX-OR gate 2.1 and latch 22. The error counter 26 is counted up for every pointer of °1'.
The count values of the l series are supplied to the correction determination circuit 27. The error address latch 28 latches one error address corresponding to the 1° pointer.

If the correction determination circuit 27 determines that correction is possible, a write command is generated from the correction determination circuit 27, and the bus controllers 23 and 24 are turned on.
Multiplexer 30 selects the latched error address. Therefore, the correct data from latch 22 replaces the error word and the corresponding pointer is set to 0°.

If correction is not possible, the correction determination circuit 27 does not issue a write command.

FIG. 5 shows, for example, the order of a correction routine for one P sequence. As shown in FIG. 5, for example, the words WO to W7 and P forming one P sequence are read out sequentially from the data RAM 10, and the pointers of these words are sequentially read out from the pointer RAM 12. The read data and pointer are supplied to the error correction circuit 15 via the data bus 4 and pointer bus 5, respectively.

The error correction circuit 15 generates syndromes and counts the number of errors as described above. For example, if word W3 is an error word, immediately after reading parity word P, the correct word W3 is written to data RAM 10 and the corresponding pointer is cleared.

Note that the data RAM and pointer RAM do not need to be separate hardware, and can be configured by dividing the memory area of one RAM.

The present invention can also be applied to product codes that form parity code sequences in the vertical and horizontal directions of a two-dimensional array of data.

〔Effect of the invention〕

According to this invention, unlike conventional decoding devices that correct errors by calculating syndromes and then adding error data and syndromes, correct data is generated immediately after syndrome calculations are completed. can. Therefore, according to the present invention, the time required for error correction operation can be shortened. In addition, an EX-OR gate for adding the syndrome and error data is no longer required.
Hardware can be simplified.

The present invention is suitable for application to error correction codes such as cross-interleave codes and product codes that can be decoded many times to increase the number of cases in which error correction can be performed. It is preferable that the interval C in is as short as possible in order to reduce the delay from when the digital audio signal is reproduced until it is taken out to the output terminal 18.

However, since the interval C is an interval in which error correction is performed, it becomes longer if the number of times of decoding of the P sequence and the number of times of decoding of the Q sequence is increased. According to this invention, P series or Q
Since the time required for one decoding of a sequence is short, it is possible to satisfy both a reduction in delay and an increase in the rate of error correction.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of this invention, Fig. 2 is a route diagram used to explain an error correction code to which this invention can be applied, and Fig. 3 is a block diagram of an error correction circuit in an embodiment of this invention. , FIG. 4, and FIG. 5 are route maps used to explain the operation of an embodiment of the present invention. Explanation of main symbols in the drawings 1: Magnetic head, 3: cRc check circuit. 10.11: Data RAM, 12.13: Pointer RAM, 15: Error correction circuit. Agent Patent Attorney Tadashi Sugiura Knowledge of the entire organization Figure 1 Gross interleader Figure 2 RAM operation Figure 4 Figure 5 Correction rule t-

Claims (1)

[Claims] A first memory that stores data encoded using a simple parity code; a second memory that stores a pointer indicating whether or not there is an error in the data; an error correction circuit that corrects errors by a pointer ledger method using the data stored in the data and the pointer stored in the second memory; 1. A decoding device for an error correction code, comprising: means for controlling so that data in which all bits are '0' is written;