JPS63160066A - Address data processor - Google Patents

Abstract

PURPOSE:To improve the capability of error detection by regarding correct address information to be correct when an expected address and a reproduced address are coincident and regarding the estimated address to be correct even in the dissidence when the number of dissident parts is within the correction capability of an error correction code. CONSTITUTION:Address information sets a1-P6 to be extracted (21) are stored in a register 31 and compared (32) with the estimated information in a register 30. The circuit 33 gives number O of dissidence between the address information part (a) and the estimated part to a system controller 10 in case of coincidence, and the address information (a) is given to the system controller 10 and an estimated address generating circuit 28 via a selector 34. In case of dissidence, when the total of the number of dissidence of the address (a) and the parity P is discriminated (33) to be a correctable value or below, an OK signal is given. When it is discriminated to be in excess of correctable number, the information (a) is regarded as an error and a signal NG is fed to the system controller 10 and the information of the sector represented in the address is not decoded and thrown away. Through the constitution above, even with an error in the reproduced address information, the correctable error is detected to be correct and to error detection capability is improved.

Description

[Detailed description of the invention] The invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Embodiment G1. Description of truck and sector formant (Second
(Fig. 3) Explanation of the main parts of the G2 data reproducing device (Fig. 1) G2-1 Address signal processing in the initial state (Fig. 1, Fig. 4) G2-2 Address signal processing in the steady state (Fig. 1) figure,
FIG. 5) H Effect of the Invention A Field of Industrial Application This invention relates to a processing device for address data added to each data block, such as data reproduced from a magneto-optical disk.

B. Summary of the Invention The present invention detects errors in address information without using an error detection and correction decoder when an error detection and correction code is generated for address data. The address information predicted from the above is compared with the next input address information, and if the two match, the address information is considered correct, and even if they do not match, the number of mismatches is determined by the correction ability of the error correction code. If it is within the range, the predicted address information is considered to be correct, and this is an attempt to improve the ability to detect errors in address information.

C. Conventional technology When digital data is transmitted via a transmission medium, for example, when it is recorded on a disk recording medium such as a magnetic tape, optical disk, magneto-optical disk, or magnetic disk, and then reproduced, it is divided into blocks of unit information amount. It is common to perform signal processing. During signal processing on the reproduction (receiving) side, address information is usually added to each block in order to distinguish it from other blocks.

For example, in the case of optical disks and magneto-optical disks, data is recorded as concentric or spiral trunks, but each trunk is divided into multiple sectors;
One block of data is recorded in one sector. Then, the sector has other sectors (
Address data is recorded to distinguish the block from the block. Address data generally consists of track address information, sector address information, and accompanying error detection or correction codes, and if the error detection or correction codes are decoded and the address information is determined to be reliable, It processes the data within that sector.

D. Problems to be Solved by the Invention However, error correction decoders generally have a more complicated structure than error correction encoders, and the higher the error correction ability of the error correction code, the more complicated the structure becomes. , which led to an increase in circuit scale.

By the way, track addresses and sector addresses recorded on optical discs and the like are generally assigned consecutive numbers such as 0, 1, 2.3, etc. in the radial and circumferential directions. When such consecutive addresses are assigned to data, the address value currently being read can be predicted by incrementing the previous address value by "1" if the previous address value is known.

Therefore, by comparing the current address information extracted from the reproduced data and the predicted address information and detecting a mismatch between the two, it is possible to detect an error. In this way, correct address information can be detected without using an error correction decoder. In this case, parity information for error detection or correction is added to the reproduced address information, so the predicted address information is also encoded, parity information for error detection or correction is added, and the parity information is included in the comparison. be done.

However, when comparing parity information in this way, even if the address information correctly matches the predicted value, if there is an error in the parity information section, the whole will not match, and the data in the sector of the correct address information will Even if the reproduced address data and predicted address data do not match, if the error that occurs in the reproduced address data can be corrected with an error correction code, it is possible to use a decoder. Although the data can be detected as correct, it is detected as an error and the data cannot be used.

In view of the above points, the present invention provides for detecting errors in address information without using an error correction decoder.
The purpose of this study is to improve its error detection ability.

E. Means for Solving Problems In this invention, address data is transmitted sequentially in blocks, and address data consisting of address information and error correction parity information generated by encoding this address information is added to each block. extraction means (22) for extracting the address data from the extracted digital data; prediction means (28) (29) for predicting the next address data from the previous address data; and address data from the extraction means (22). a comparing means (32) for comparing the predicted address data; a means (33) for determining that the address information is correct when at least the address information matches in the comparing means (32); If the two do not match, and the number of mismatched points is less than (d-1)/2, where d is the minimum distance between error correction codes for address information, the predicted address information is determined to be the correct address. means (33).

F Effect When the reproduced address information and the predicted address information match, it is detected as correct address information regardless of whether the parity information matches or does not match.

Furthermore, even if the two address information do not match, if the number of points of mismatch is less than or equal to (d-1)/2, it is within the range where the error can be corrected using parity information. The probability of an error occurring is higher than non-wealth. Therefore, the predicted address information can be determined to be correct address information.

G. Embodiment An example of the apparatus of the present invention will be described using a data reproducing apparatus for a magneto-optical disk as an example.

First, track and sector formats proposed for magneto-optical disks will be explained.

G1) Explanation of rank and sector formant As shown in Figure 2, this magneto-optical disk (1) records data as one trunk per rotation, with trunks (2) formed in a circular or spiral shape. and will be played from now on.

One track (2) of this magneto-optical disk (1) consists of a plurality of sectors equally divided in the circumferential direction, and each sector contains a predetermined number of data, error correction codes, error detection codes, etc. What is generated and added is recorded.

In the example of Figure 2, one track is as shown in Figure A.
For example, there are 32 sectors.

The format of the data block recorded in one sector is, for example, as shown in FIG. That is,
One sector is divided into 43 segments, and each segment is equivalent to 18 bytes.

The first O-th segment of each sector is an address part IDR in which address data is recorded, and the first
- The 43rd segment is a data section DTR in which actual data is recorded.

Each segment of the address part IDR and data part DTR has a structure as shown in C and D in the same figure, and the first 2 bytes are used as a servo area, and the 3rd to 18th bytes contain address information. and for actual data.゛And as address data,
As shown in Figure C, an address mark SMI whose first byte is a sync pattern is recorded, followed by the upper 8 bits TA (M) of the track address TA, the lower 8 bits TA (L), and the sector address SA. is recorded, followed by 3 bytes of parity information P for error correction for the track address TA and sector address. In this example, address mark SM2, address information TA, SA, and their error correction parity P information are subsequently recorded in double writing. Note that the last two bytes are a gap part between the data part DTR and the data part DTR.

As shown in the figure, the data portion DTP has 16 bytes per segment, and 512 bytes of data in one sector and 16×42=672 bytes are recorded for parity information for error correction of this data.

In this example, the recorded information on the disc is channel coded, for example, "1 byte of data is
Muffing is performed on 5 channel bits so that there are 4 "1"s among the 15 channel bits. However, “1
” and “1”, there are always two or more “0”s, and one byte is divided into the upper 4 bits and the lower 4 pins, and one of the 15 channel bits of “1” Set the positions so that one is an odd number and the other is an even number. ” 4-15 modulation is performed.

Since the error correction codes for the address information TA and SA are processed in units of 4 bits in the above-mentioned 4-15 modulation, 4 bits are treated as one symbol as shown in FIG. 3, for example (12, 6). It is composed of Reed-Solomon codes. In FIG. 3, a1 to a6 are address information symbols, and P1 to P6 are parity symbols. This error correction code has a minimum distance d=7 (symbols),
It is possible to correct errors of (d-1)/2=3 symbols or less.

Then, track address TA and sector address S
A is assigned sequentially, for example, the track address TA is 0, 1.2, etc. from the recording start side of the disc.
Furthermore, a sector address SA is sequentially assigned to data in each sector from address 0 to address 31 within one trunk.

That is, the i-th track address T A (1) is TA (11=TA (i -1) + 1, and the first sector address 5A (J) is 5AU) = SA (j
−1) +1.

Description of Main Parts of G2 Data Reproducing Apparatus Next, an example of the main parts of a magneto-optical disk data reproducing apparatus to which the present invention is applied is shown in FIG.

In the figure, (11) is a magneto-optical disk, and (12) is a motor for driving its rotation.

The playback data from the disk (11) is supplied to the playback process circuit (13), and the actual data and address data that had been modulated by 4-15 are demodulated into data in units of 1 byte (8 bits), and then sent to the PCM decoder. (14) and is temporarily written into the buffer register. Then, errors in the address data are detected as shown below, and the data in the sector where the correct address was detected is stored in a system controller (equipped with a microcomputer) (1
0) is read out from the buffer register and decoded.

In this example, in a steady state where consecutive addresses are sequentially obtained, error detection is performed by comparing the address data read from the disk with the predicted address data. However, when the initial state is reached for address information, such as when there is no initial value for continuous addresses or when continuous addresses are interrupted, such as when starting disk playback or when a data reading head jumps to a track, the next Since there is no appropriate address information for predicting the address value, if the reproduced address data and the predicted address data are compared at this time, an error will be detected for incorrect address data.

Therefore, in this example, the error detection method for address data is changed between the initial state and the steady state.

In other words, the system controller (10) has a key human power device (15).
is connected to start the disc, control the head for reading data from the disc (for example, track jump), etc. In this example, switch circuits (22) and (27) are provided that can be switched between an initial state and a steady state, and are switched to the terminal S side in the initial state and to the N terminal in the steady state according to a switching signal from the system controller (10). Switched to the side.

G2-1 Address Signal Processing in the Initial State First, address data error detection in the initial state will be explained.

The demodulated data from the reproduction process circuit (13) is
The address data is supplied to the address data extraction circuit (21), and the address data of the O-th segment of each sector is extracted.

The address data (address information symbols 31 to a6 and parity symbols P1 to P6 in FIG. 3) from this address data extraction circuit (21) is extracted from the switch circuit (21).
2) is supplied to the reproduction address register (23) and stored therein, and at the same time symbols a1 to a6 of the address data are supplied to the ECC encoder (24).
) from which parity symbols P1° to P
- is generated.

Then, the parity symbols P1 to P6 from the reproduction address register (23) and the generated parity symbol P
i' to P♂ are compared in a match/mismatch judgment circuit (25). Here, if no error occurs in the information symbols a1-a6 and the parity symbols P1-Ps, P-P6 and P18-P- match. therefore,
In this judgment circuit (25), errors in address information can be detected depending on whether the two parity symbols match or do not match. When the judgment circuit (25) judges that both parity symbols match, an OK signal indicating that the address information is correct is supplied to the system controller (10), and the signal is opened to the gate circuit (26). A signal is supplied, and the address information from the playback address register (23) is supplied. IJat to a6 are supplied to the system controller (1o) via the terminal S of the switch circuit (27). In response to the signal from the system controller (10), the decoder (14) reads the data of the sector indicated by the address information a1 to aG from the puffer register and decoders it.

The address data error detection operation in this initial state can also be realized by software using a microcomputer. FIG. 4 is a flowchart for error detection.

G2-2 Address signal processing in steady state In this initial state, when the system controller (10) determines that correct address information has been obtained by the signal OK, or when correct address information has been stably obtained (signal OK continues) (obtained multiple times), the system controller (obtained multiple times)
The switch circuits (22) and (27) are switched to the terminal N side by the switching signal from 10) to enter a steady state. Note that the transition from the initial state to the steady state can also be performed using the detection result of the servo lock state.

By the way, before switching to this steady state, the address information through the terminal S side of the switch circuit (27) is supplied to the predicted address data forming circuit (2B). In this forming circuit (28), "I" is added to the track address and sector address values from the switch circuit (27) to generate a predicted address information symbol a, which is the next predicted address value.
IJl~a- are formed, and these predicted address symbols aIH~a6'' are supplied to the encoder (29) to generate predicted parity symbols Pt' for error correction.
"" P♂ is generated.

Then, from this encoder (29), predicted address symbols a1"~a- and predicted parity symbols P1"~P
- is obtained and stored in the predicted address register (30). Therefore, when the switch circuits (22) and (27) are switched to the terminal N side, predicted address data is already prepared in the predicted address register (30).

Address data a1 to P6 from the address data extraction circuit (21) are stored in the reproduction address register (31) through the terminal N side of the switch circuit (22). This reproduced address data is the predicted address data a1'' to P6N from the predicted address register (30).
and is compared by a match/mismatch judgment circuit (32). In this example, the judgment circuit (32) separately compares the address symbol part and the parity symbol part, and the judgment circuit (32) separately compares the address symbol part and the parity symbol part.
The signal is supplied to the error determination circuit (33). In the error determination circuit (33), first, as a result of comparing the address information part, that is, the symbols a1 to a6, and the predicted symbols a1H to a, H, if it is determined that the number of mismatched symbols is zero, that is, the two match, then from this A signal OK indicating that correct address information has been obtained is supplied to the system controller (10), and a select signal is supplied to the selector (34), so that the address information a1 to a6 from the reproduction address register (31) is The system controller (10) is connected to the system controller (10) through the selector (34) and through the terminal N side of the switch circuit (27).
and is supplied to the predicted address forming circuit (28).

If the number of mismatched symbols in the comparison result of the address information part in the judgment circuit (32) is not zero, that is, when there is a mismatch, the error judgment circuit (33) compares the number of mismatched symbols in the address information part and the parity symbol. It is determined whether or not the total number of unmatched symbols can be corrected using parity symbols, and when the number of errors that can be corrected is withdrawn, an OK signal is sent from the error discrimination circuit (33) to the system controller (10). At the same time, the selector (34) is supplied with a select signal that outputs predicted address information a, H to a- from the predicted address register (30).

On the other hand, when the error is above the number that can be corrected, a signal NG indicating that the address information is in error is supplied from the error determination circuit (33) to the system controller (10). At this time, the address information from the selector (34) is the system controller (
10), it is not used, and the data in the sector indicated by that address is discarded without being decoded. Therefore, either the reproduced address or the predicted address may be obtained as an output from the selector (34).

By the way, in this example, a (12,6) Reed-Solomon code is used, and it is possible to correct errors for up to three symbols. Therefore, if the total number of mismatched symbols is 3 or less, the predicted address may be set as the correct address, but in this example, it is set to 2 or less in consideration of safety.

The error detection of the address data during normal operation as described above can also be carried out by software processing by a microcomputer. FIG. 5 is a flowchart of the execution program.

In this case, address information a1 to a6 of the reproduced address data is read and predicted address information 3. ”%36
As a result of the comparison with Since the sector data can be decoded, the parity information P1 to P6 is not read and compared with prediction information. and,
If the result of comparing only the address information symbol part is a mismatch, the parity symbol is read and the entire address data is compared.

Note that in the above example, the recorded data is divided into the upper 4 bits and the lower 4 pins and is modulated 4-15 and recorded as described above, so 4 pins are 1 symbol. An error correction code is formed as follows. On the other hand, if we consider the occurrence of two consecutive errors,
In the case of FIG. 6, the probability that each byte is incorrect, as shown by C1, is higher than the probability that successive symbols with different bytes are incorrect, as shown by C2 in the same figure. Here, the x mark in the figure represents a symbol causing an error.

Based on the above, weighting is applied to the occurrence of consecutive errors. For example, when a two-symbol consecutive error occurs in a byte, as shown in C) in the same figure, another symbol is incorrect. also outputs the address signal OK and uses the predicted address as the correct one. In the case of the same figure, when a two-symbol consecutive error spans two bytes as shown by C4, the address signal is output if there is even one other error symbol. A signal NG indicating a data error may be output.

Note that this invention is applicable not only to address processing for playback data from an optical disc (but also to all address processing on the receiving side when an error correction code is configured as address data and digital data is transmitted in blocks). It is possible.

Effects of the Invention According to this invention, errors can be detected for address data to which an error correction code is generated and added without using an error correction decoder.Especially for codes with a large minimum distance, the decoder is much more effective than the encoder. Since the configuration is complicated, the present invention can simplify the overall configuration and reduce the circuit scale.

In this invention, instead of detecting errors only when input address data and predicted address data do not match, it is assumed that the address information is correct when only the address information excluding error correction parity matches, and that the address information is correct when only the address information excluding the error correction parity matches. If there is a mismatch that can be corrected using the error correction parity, it is assumed that this is an error that has occurred in the transmission system, and the predicted address is regarded as correct address information, thereby improving the error detection ability of detecting correct address information as correct. That is, even if there is an error in the reproduced address data, if the error is corrected by the error correction decoder and the address information becomes correct, it can be detected as correct, and the data in the sector at that address can be decoded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of the device of this invention, FIG. 2 is a diagram showing an example of a trunk and sector format of a magneto-optical disk, and FIG. 3 is a structural diagram of an example of address data.
FIG. 4 is a flowchart of address data processing at an initial stage, FIG. 5 is a flowchart of address data processing at a steady state, and FIG. 6 is a diagram showing types of error occurrences. (22) is an address data extraction circuit, (28) is a predicted address information forming circuit, (30) is a predicted address register, (31) is a reproduction address register, (32) is a match/mismatch judgment circuit, (33) is This is an error determination circuit.

Claims (1)

[Scope of Claims] a) The above-mentioned data is transmitted sequentially in blocks, and is added with address data consisting of address information and error correction parity information generated by encoding this address information for each block. extraction means for extracting address data; b) prediction means for predicting next address data from previous address data; c) comparison means for comparing address data from the extraction means with the predicted address data; d) means for determining that the address information is correct when at least the address information matches in the comparison means; and e) means for correcting errors in the address information by determining the number of mismatches when the two do not match in the comparison means. An address data processing device comprising means for determining the predicted address information as a correct address if it is less than or equal to (d-1)/2, where d is the minimum distance between codes.