JPS63160066A - Address data processor - Google Patents

Address data processor

Info

Publication number
JPS63160066A
JPS63160066A JP30747386A JP30747386A JPS63160066A JP S63160066 A JPS63160066 A JP S63160066A JP 30747386 A JP30747386 A JP 30747386A JP 30747386 A JP30747386 A JP 30747386A JP S63160066 A JPS63160066 A JP S63160066A
Authority
JP
Japan
Prior art keywords
address
information
error
dissidence
estimated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30747386A
Other languages
Japanese (ja)
Other versions
JP2508471B2 (en
Inventor
Takayoshi Chiba
Tamotsu Yamagami
Yoichiro Sako
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP61307473A priority Critical patent/JP2508471B2/en
Publication of JPS63160066A publication Critical patent/JPS63160066A/en
Application granted granted Critical
Publication of JP2508471B2 publication Critical patent/JP2508471B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To improve the capability of error detection by regarding correct address information to be correct when an expected address and a reproduced address are coincident and regarding the estimated address to be correct even in the dissidence when the number of dissident parts is within the correction capability of an error correction code.
CONSTITUTION: Address information sets a1WP6 to be extracted (21) are stored in a register 31 and compared (32) with the estimated information in a register 30. The circuit 33 gives number O of dissidence between the address information part (a) and the estimated part to a system controller 10 in case of coincidence, and the address information (a) is given to the system controller 10 and an estimated address generating circuit 28 via a selector 34. In case of dissidence, when the total of the number of dissidence of the address (a) and the parity P is discriminated (33) to be a correctable value or below, an OK signal is given. When it is discriminated to be in excess of correctable number, the information (a) is regarded as an error and a signal NG is fed to the system controller 10 and the information of the sector represented in the address is not decoded and thrown away. Through the constitution above, even with an error in the reproduced address information, the correctable error is detected to be correct and to error detection capability is improved.
COPYRIGHT: (C)1988,JPO&Japio
JP61307473A 1986-12-23 1986-12-23 Address data processing device Expired - Fee Related JP2508471B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61307473A JP2508471B2 (en) 1986-12-23 1986-12-23 Address data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61307473A JP2508471B2 (en) 1986-12-23 1986-12-23 Address data processing device

Publications (2)

Publication Number Publication Date
JPS63160066A true JPS63160066A (en) 1988-07-02
JP2508471B2 JP2508471B2 (en) 1996-06-19

Family

ID=17969500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61307473A Expired - Fee Related JP2508471B2 (en) 1986-12-23 1986-12-23 Address data processing device

Country Status (1)

Country Link
JP (1) JP2508471B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04229465A (en) * 1990-12-27 1992-08-18 Matsushita Electric Ind Co Ltd Optical information recording and reproducing device
US6175943B1 (en) 1997-12-17 2001-01-16 Samsung Electronics Co., Ltd. Apparatus for controlling addresses of symbol data for error correction
JP2009510923A (en) * 2005-09-29 2009-03-12 ドルビー・ラボラトリーズ・ライセンシング・コーポレーション Error correction in packet communication networks using data integrity check
JP2009510924A (en) * 2005-09-29 2009-03-12 ドルビー・ラボラトリーズ・ライセンシング・コーポレーション Error correction in packet communication networks using verification sets
JPWO2010109830A1 (en) * 2009-03-24 2012-09-27 日本電気株式会社 PLTn bit correction circuit, GFP layer 2 synchronization circuit using the same, and GFP frame transfer apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139982A (en) * 1984-07-31 1986-02-26 Toshiba Corp Address data processing system of disk reproducing device
JPS61170964A (en) * 1985-01-22 1986-08-01 Matsushita Electric Ind Co Ltd Error correction controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139982A (en) * 1984-07-31 1986-02-26 Toshiba Corp Address data processing system of disk reproducing device
JPS61170964A (en) * 1985-01-22 1986-08-01 Matsushita Electric Ind Co Ltd Error correction controller

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04229465A (en) * 1990-12-27 1992-08-18 Matsushita Electric Ind Co Ltd Optical information recording and reproducing device
US6175943B1 (en) 1997-12-17 2001-01-16 Samsung Electronics Co., Ltd. Apparatus for controlling addresses of symbol data for error correction
JP2009510923A (en) * 2005-09-29 2009-03-12 ドルビー・ラボラトリーズ・ライセンシング・コーポレーション Error correction in packet communication networks using data integrity check
JP2009510924A (en) * 2005-09-29 2009-03-12 ドルビー・ラボラトリーズ・ライセンシング・コーポレーション Error correction in packet communication networks using verification sets
JPWO2010109830A1 (en) * 2009-03-24 2012-09-27 日本電気株式会社 PLTn bit correction circuit, GFP layer 2 synchronization circuit using the same, and GFP frame transfer apparatus

Also Published As

Publication number Publication date
JP2508471B2 (en) 1996-06-19

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees