JP2574740B2 - PCM signal reproduction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to error correction of digital audio signals, and is particularly suitable for digital audio tape recorders.
The present invention relates to a PCM signal reproducing device.

[Background of the Invention]

2. Description of the Related Art In recent years, digitization of transmission signals in audio has rapidly progressed, and digital audio discs (CDs) and PCM broadcasting of sound by broadcasting satellites have been or will be implemented. Under such circumstances, digitalization is being considered for tape recorders.

Although several methods have been considered as digital tape recorders, rotary head type tape recorders (hereinafter referred to as R-DATs) are excellent in that they can increase the recording density and are easy to access.

FIG. 1 shows a block configuration of the R-DAT. This will be described below with reference to the drawings.

Although FIG. 1 uses an example including a portion related to a still image and a portion related to a two-channel audio signal, a method not including a still image may be used.

For example, left channel and right channel analog signals are input to the analog audio signal input terminals 1-1 and 1-2.

Input signals from the input terminals 1-1 and 1-2 are input to the analog-to-digital conversion circuit 2 and converted into digital signals. The digital signal converted here is once recorded in the memory 3. The signal recorded in the memory 3 is
The data is read out at predetermined intervals, and the encoding processing is performed by the encoding processing circuit 5. Here, the addresses at the time of recording and reading of the memory 3 are controlled by the memory control circuit 4, and an interleaving process is performed.

Next, the signal subjected to the encoding process and the interleaving process is converted from a parallel signal into a serial signal by the parallel / serial conversion circuit 6 to obtain a serial signal.

A synchronization signal and a signal from the control signal generation circuit 7 are time-division multiplexed on this serial signal.

This signal is input to the modulation circuit 8 and subjected to predetermined digital modulation, and then to the recording amplifier 9. The signal is input to the heads 34 and 35 via the head switching circuit 10 and is recorded on the magnetic tape 33.

For reproduction, a head reproduction signal 31 based on a signal recorded on a magnetic tape is input to a waveform equalization circuit 12 via a head switching circuit 10 and a pre-reproduction value amplifier 11. Waveform equalization circuit
In 12, after performing a predetermined waveform equalization, the waveform equalization output signal is input to the code identification circuit 37 to perform code identification and data clock reproduction.

The code-identified signal is input to the demodulation circuit 13 and also to the synchronization signal detection / protection circuit 14, where a synchronization signal is generated. This synchronization signal is input to the control circuit 15 to generate a control signal. Although not shown in the drawing, the control signal is input to each circuit block.

The signals demodulated by the demodulation circuit are sequentially recorded in the memory 16. The signal recorded in the memory 16 is controlled by a memory control circuit 17, and is read out by performing a predetermined deinterleave process or the like, and is input to an error correction circuit 18 to perform error data detection / correction processing.

These error data are detected and corrected, and the data is then input to an error correction circuit 21 to perform predetermined correction on the error data.

The error correction processing data is input to the digital-to-analog conversion circuit 20, and the two-channel analog signals 19-1, 19-1,
Converted to 19-2. Here, 38 and 22 are data buses.

The still image signal 7-23 is converted into a digital component signal by the image conversion circuit 7-24 and recorded. The recorded signal is transferred to the memory 26, for example, in line units. The contents of the memory 26 are controlled by the memory control circuit 25, and are sequentially input to the encoding circuit 5 and encoded. The encoded signal is input to the parallel / serial conversion circuit 6 and converted into a serial signal.

The serial signal is time-division multiplexed with the signal from the synchronizing signal / control signal generating circuit 7 and input to the recording amplifier 9 at a different timing from the previous audio signal, and is recorded on the magnetic tape 33 in the same manner.

Similarly, reproduction is performed by amplifying and equalizing a reproduction output signal 31 from the head, detecting and protecting a code identification / synchronization signal, demodulating the signal, demodulating the signal, and sequentially recording it in the memory 27. The recorded signal is read out under the control of the memory control circuit 28 and subjected to a decoding process in the same manner, and then input to the image conversion circuit 29 to be converted into a video output signal 30.

Here, the cylinder 32 and the tape running system are controlled by a cylinder / capstan servo circuit 36 which receives a predetermined signal, and at a predetermined rotation speed and a predetermined tape speed,
In addition, predetermined tracking is performed.

 The above is the outline of the configuration and operation of the R-DAT.

Next, the tape format of the R-DAT will be described with reference to FIG.

FIG. 2A shows the winding of the two-head cylinder 32 and the tape, and the winding angle (wrap angle).
Is, for example, 180 ° or less and 120 ° in this embodiment. Also ν
t indicates the tape speed, and N indicates the cylinder rotation speed.

FIG. 6B shows a track pattern on the tape 33, which is a track pattern having a track angle θ テ ー プ and a track length 1 in a region of an effective track width W on a tape having a tape width A.

FIG. 3C is an enlarged view of the track pattern. Lap angle
This is an example in the case of 120 °, in which the still image area p is 32 ° and the audio area s is 69 °.

FIG. 3 shows a specific embodiment of the block configuration. First, as for the block length, the number of data per block and the corresponding block length were determined in consideration of the code configuration, the magnitude of the burst error of the transmission system or the medium, and the random error rate.

 This will be described below with reference to FIG.

One block consists of an 8-bit synchronization signal and 8-bit control signal.
It comprises a display signal, 12 data words in 8-bit units, 4 parity words in 8-bit units, and 2 different parity words in 8-bit units. Where the first data word is 16
The bit digital sampled signal is divided into two by the upper 8 bits. These are indicated by U for the upper 8 bits and L for the lower 8 bits.

There are four parity words, P ₀ , P ₁ , P _2, and P ₃ , and two other parity words, Q ₀ and Q ₁ , each of which is a different data word. It is generated by the tuple. Each data and parity word are arranged in order from the upper bit.

FIG. 4 shows an interleave format. This interleave format is a format on any one track, and therefore Lou and Lol and Rou and R
ol indicates the upper 8 bits and lower 8 bits data words of the first sampled data in the track, respectively. That is
Lou and Lol are upper 8 bits and lower 8 bits of the first L channel data, respectively.

First, the sampled data is divided into odd-numbered data words and even-numbered data words. This is because, for example, even when the first half or the second half of the track becomes a continuous error, a value close to the original value can be generated by average value interpolation or the like unless other data words are erroneous. Further, in order to avoid consecutive errors in the divided data, adjacent data, for example, Lou and L ₂ u are transmitted or recorded with a certain block away.

In the figure, SYNC is a synchronization signal and is a predetermined 8-bit pattern. The other C & D is a control display signal word having 8 bits. Thus, one block is composed of 160 bits.

In the case of FIG. 4, one frame is composed of 256 blocks. For example, the data of the 17th block is L ₉₆ u, L ₉₆ l, L ₂ u, L ₂ l, L ₆₇₆ u, L ₆₇₆ l, B ₅₇₆ u, R
₅₇₆ l, R ₄₈₂ u, R ₄₈₂ l, R ₃₉₀ u, R ₃₉₀ l, R _0,48 u, P _0,48
1, P _2,32 u, P _2,32 l, P _2,32 l, Q _0,16 and Q _1,16
And one C & D, and a synchronization signal is added.

FIG. 5 is a timing chart showing the operation of the recording system, which will be described below with reference to the drawing.

A two-channel audio signal sampled at a fixed sampling frequency, for example, 44.1 KHz and quantized with a fixed quantization bit number, for example, 16 bits, has a fixed sample number, for example, 768, for each channel as shown in FIG. Divide for each sample. A frame is constituted by the data thus divided. That is, they are recorded on the same track.

First, for each divided data,
The data is recorded in RAM1 and RAM2 at the timings shown in FIGS.
Here, when processing is performed at the timing described later, it is possible to use the RAMs 1 and 2 alternately as memories for this purpose.

Next, the data recorded in the memories of the RAMs 1 and 2 are encoded at the timing shown in FIG.

The encoded data is time-axis-compressed and output at the timing shown in FIG. E, and is added with the still image information and other control signals to obtain a recording signal shown in FIG. The hatched portion during the timing of F is an audio signal area.

FIG. 6 is a timing chart showing the operation of the reproducing system, which will be described with reference to the drawings.

The timing of the reproduced signals from the two heads of channels 1 and 2 is shown in FIG. The audio signal portion, that is, the hatched portion in the reproduced signal is shown in FIG. The signals in FIG. B are sequentially processed and recorded in the memory. The data recorded in the memory is decoded at the timing shown in FIG. The processed signal is expanded on the time axis, and is output at a certain period at the timing shown in FIG.

One of the problems of the R-DAT is a track shift.
In R-DAT, as a tracking method, for example,
Although the tracking control is performed by the ATF or the like like -3507, there is a case where the reproduction is performed over a plurality of tracks as shown by 40 in FIG. 7 due to the lack of the ATF signal or the like.

In such a state, data of a plurality of tracks is included in the reproduction data of one track shown in FIG. Therefore, there is a case where data of a different code sequence is included in the code sequence to be error-corrected. Could be done. This erroneous correction causes an abnormal sound, which is a problem in digital audio devices.

[Object of the invention]

An object of the present invention is to enable efficient error correction even when an interleave shift occurs due to a track shift or the like.
An object of the present invention is to provide a PCM signal reproducing device.

[Summary of the Invention]

According to the present invention, a track address and a block address to which data is added at the time of recording are checked at the time of reproduction, and when a track shift or a block shift is detected, an error correction method is changed to perform error correction with high error detection capability. Thus, the occurrence of abnormal sound caused by the interleave shift is prevented.

(Example of the invention)

 Hereinafter, an embodiment of the present invention will be described.

First, the R-DAT error correction code and error correction method will be described with reference to FIG.

For encoding, double encoding is performed using a Reed-Solomon code (hereinafter abbreviated as RSC (16, 12)) having a code length of 16 words and 12 data words and RSC (18, 16). That is, four parity words are added to 12 data words by RSC (16, 12). This is referred to as C ₂ code. Next, the interleaved for each data word and parity word, two words by RSC (18, 16) for each different C ₂ 12-word data word contained in the code and 4 words of the parity words 16 words Is added. This is referred to as C ₁ code.

First described C ₂ code. For example, the data word L ₀
u, L ₂ u, L ₄ u, R ₀ u, R ₂ u, R ₄ u, L ₁ u, L ₃ u, L ₅ u, R ₁ u, R ₃ u, R ₅ u 12
Than _{words, P 0 u, P 2 u} , P 1 u, and generates a 4-word parity word of P ₃ u. Similarly, data words L ₀ l, L ₂ l, L ₄ l, R ₀ l, R ₂ l, R ₄ l, L ₁ l,
_{L 3 l, L 5 l,} R 1 l, R 3 l, R 5 l of 12 words from _{P 0 l, P 2 l,} P 1 l, to produce a 4-word parity words P ₃ l. Here, in order to make the explanation easy to understand, the data words are sequentially referred to as W ₀ , W ₂ , W ₃ , W ₄ , W ₅ , W ₆ , W ₇ , W ₈ , W ₉ ,
Let W ₁₀ and W ₁₁ be the parity words P ₀ , P ₁ , P ₂ and P ₃ .

RSC (16, 12) is defined on the Galois field GF (2 ^8). Here, assuming that a primitive element of a Galois field GF (2 ⁸ ) having a primitive polynomial of F (x) = x ⁸ + x ⁴ + x ³ + x ² +1 on G (2) is α, g ₂ (x) = (x + 1) (x + α) (x + α ² ) (x + α
³ ) The code of 16 words of code length, 12 words of data, and 4 words of parity which is a generator polynomial is RSC (16,12). That, C ₂ code polynomial representation _{C 2 (x) = W 0} x 15 + W 1 x 14 + ... + W 10 x 5 + W 11 x 4 + P 0 x 3 + P 1 x 2 + P 2 x + P 3 is g ₂ (x) Parity words P ₀ , P ₁ , P ₂ , P ₃
Determine the value of

Next, the C ₁ code by the 4-word parity word generated by the data word and C ₂ code of interleaved 12-word 2
Generate word parity words. For example, in the case of the interleave shown in FIG. 4, for example, in the 17th block, data words L ₉₆ u, L ₉₆ l, L ₂ u, L ₂ l, L ₆₇₆ u, L ₆₇₆ l, R ₅₇₆ u, R
₅₇₆ l, R ₄₈₂ u, R ₄₈₂ l, R ₃₉₀ u, R ₃₉₀ l and parity word P
Q _0,16, and Q from 16 words of _0,48 u, P _0,48 l, P _2,32 u, P _2,32 l
Generate two parity words of _1,16 .

Here, in order to make the explanation easy to understand, the data words are sequentially referred to as W ₀ , W
₁ , W ₂ , W ₃ , W ₄ , W ₅ , W ₆ , W ₇ , W ₈ , W ₉ , W ₁₀ , W _11, and P ₀ , P ₁ , P ₂ , P ₃ and Q ₀ as parity words , Q ₁

RSC (18, 16) is a code having a code length of 18, a data word of 16, and a parity word of 2 using g ₁ (x) = (x + 1) (x + α) as a generating polynomial. That, C ₁ code polynomial representation _{C 1 (x) = W 0} x 17 + ... + W 11 x 6 + P 0 x 5 + P 1 x 4 + P 2 x 3 + P 3 x 2 + Q 0 x + Q 1 is g ₁ (x) The values of the parity words Q ₀ and Q ₁ are determined so as to be divisible by.

During decoding, performs a de-interleaving after the error detection and error correction by C ₁ code, and performs error detection and error correction with C ₂ code. C ₁ code by the code length 18, parity number 2, the minimum distance 3, C ₂ code is used code length 16, parity number 4, the Reed-Solomon code of the minimum distance 5. Thus, the C ₁ decoder is capable of error correction of one symbol.
In the C ₂ decoding, S errors of unknown error positions and E error positions of known error (in the following description, the former is an error and the latter is an erasure) are in the range of 2S + E ≦ 4. Can correct the error. (Japanese Patent Application No. 58-1109
31) Therefore, perform error detection and one symbol correction at C ₁ decoding, a flag indicating the state of the decoding is added to each word simultaneously, the C ₂ decoding according to the condition of the flag which is added by the C ₁ decoding, the following By performing optimal decoding among the three types of decoding shown in (1), it is possible to perform error correction with excellent capability.

(1) S = 2, E = 0: Correct 2 errors.

(2) S = 1, E = 2: One error and two erasures are corrected.

(3) S = 0, E = 4: 4 erasures are corrected.

FIG. 8 is a flowchart of C ₁ decoding. N (E)
C ₁ is a number of errors detected by the decoding, performs a one symbol correction when an error is determined to one. Further, use of F ₀ flag and F ₁ flag as a flag indicating the state of decoding of a C ₁ decoding. The F ₀ flag is set to “1” when an error is detected, and F ₁
The flag is set to "1" when two or more errors make the correction impossible.

Next, a flowchart of a C ₂ decoding in FIG. 9. In the _{figure, L (F 0), L} (F 1) is the number of matching positions that are added in the error locations and F ₀ flag or F ₁ flag detected by C ₂ decoding. N (F ₀ ) and N (F ₁ ) are the numbers of the F ₀ flag and the F ₁ flag, respectively. F is an uncorrectable flag added to a symbol determined to be uncorrectable, and F =
In the case of 1 is flagged all symbols of C ₂ block, in the case of F = F ₀ adds a flag only symbols that are added to F ₀ flags.

Hereinafter, the procedure of the C ₂ decoding by Figure 9.

(1) First, decoding is performed with S = 2, E = 0. As a result, it is possible to detect an error position up to two symbols at an arbitrary position. When it is determined that the number of errors is two or less, correction is performed when the possibility of erroneous correction is small based on the presence or absence of a flag added to the error position and the number of flags in the block. If there is a possibility of erroneous correction, it shall be uncorrectable.

(2) If it is determined in (1) that there are three or more errors, F ₀
If the number of flags 3, 3 being the addition of F ₀ flags
The decoding of S = 1 and E = 2 is performed with two of the symbols being erased. If it is determined that there is an error only in the symbol to which the flag is added, correction is performed using the result of the decoding.

(3) If it is determined in (1) that there are three or more errors, F ₀
If the number of flags 4, 4 which is added the F ₀ flag
Assuming that the symbol is lost, decoding of S = 0 and E = 4 is performed, and symbol correction is performed.

(4) (1) is determined that an error is three or more, if the number of F ₀ flag is 5 or more, if the number of F ₁ flag 3, F ₁
S = 1 and E = 2 are decoded with two of the three symbols to which the flag is added being erased. When it is determined that there is an error only in symbols that are added in the F ₁ flag, using the result of the decoding, performs a correction.

(5) In (1), it is determined that there are three or more errors, and (2) to
If the correction conditions of (4) do not apply, correction is impossible.

As described above, by performing the decoding twice by different decoding methods, it is possible to correct even if the single decoding cannot be corrected or is erroneously corrected.

In yet C ₁ decoding, it is possible to erasure correction of up to two by using a flag or both flags indicating that correcting the flag That error flag or error from the demodulation circuit. In addition, erroneous correction can be reduced. That is, 2S + E
≦ error correction in the second range that can be performed, by taking a method similar to C ₂ decoding, can increase the error detection and correction capability of a C ₁ decoding.

The C ₁ has been encoded by the RSC (18, 16) as an example of the code, the control display signal word in Fig. 12 (C & D)
By using the RSC (19, 16) including the above, an error can be detected and corrected even for the control display signal word.

As an example of C ₁ code also encodes Language of the same block in Figure 4, the generated parity word Q ₀ and Q ₁
The was placed in the block, by C ₁ encoded by interchanging the words in different blocks as described in the prior art,
Since the continuous errors in the reproduced signal is separated in the C ₁ decoder, C ₁
The ability to correct the code can be used effectively.

As described above, by performing the error correction and the erasure correction and the combined correction of the erasure and the error, it is possible to perform the correction having both excellent correction ability and detection ability. However, since erasure correction has no detection capability, erroneous correction is performed, for example, in the case of FIG. Will contain data of different tracks in the case such as FIG. 7 but, C ₁ parity C ₁ flag is not added to which is added correctly. In other words, it becomes a detection leakage data of a C ₁ correction. In error correction, this detection omission can be determined when detecting an error position. However, in erasure correction, all data to which a flag is not added are corrected as being correct, so that erroneous correction is performed. This is the same even when data in one track is shifted. Therefore, it is necessary not to perform erasure correction when a track shift or a block shift occurs. In such a case, the possibility of erroneous correction increases with other correction methods.

In order to detect a track shift and a block shift during reproduction, a block address signal and a track address signal are recorded in the control / display signal portion of FIG.
The control / display signals are shown in FIG. FIG. 7A shows control / display signals for odd-numbered blocks, and FIG. 7B shows control / display signals for even-numbered blocks. For odd blocks, add “0” to the first bit,
The upper 7 bits of the block address (0 to 255) are recorded in the second to eighth bits. In the even-numbered block, “1” is added to the first bit, and the lower three bits (0 to 7) of the track address are recorded in the second to fourth bits. The fifth to eighth bits record an inter-music code, a sampling frequency, and the like.

To prevent erroneous correction will check the track address and the block address during reproduction, if the tracking error or block misalignment is detected, may do it by changing the algorithm of the C ₂ decoding. Algorithms in such a case include the following.

(1) No correction is made.

(2) Only error correction is performed.

(3) Error correction or error + erasure correction is performed.

Next, a PCM signal reproducing apparatus according to the present invention will be described with reference to an eleventh embodiment.

In FIG. 11, 42 is a track address check circuit, 45 is a block address check circuit, and 44 is an OR circuit. The check of the track address and the block address is performed when the reproduction signal shown in FIG. 6 is recorded in the memory. That is, when the reproduction signal is recorded in the memory 16 by the demodulation circuit 13, the track address check circuit 42
And input to the block address check circuit 43 to check whether or not the address is abnormal. If an abnormality is found, the output signal is set to "1". And
Check the output signal when performing the C ₂ decoding by the error correction circuit 18, when the "0" performs normal decoding, changes the Fukugo algorithm in the case of "1".

C ₂ Fukugo algorithm, in the case of normal above (1) to
The decoding of (5) is performed. If a track shift or a block shift occurs, for example, if error correction and error + erasure correction are to be performed, an algorithm other than (3) may be used. That is, the conditions (1), (2), and (4) may be changed to “when the number of _F0 flags is four or more” and (5) may be performed.

FIG. 12 shows a track address check circuit. In the figure, 45 is a latch circuit, 46 is a match detection circuit, 47
Is an SR latch circuit. First, a reset signal is input to the reset signal input terminal 49 to reset the RR latch circuit 47. Then, the track address in the reproduction signal is sequentially latched by the latch circuit 45. In the match detection circuit 46,
Two adjacent track addresses are compared. And
If the track addresses are different, the RS latch circuit 47 is set, and the output 50 is set to "1". This coincidence detection circuit 46 is constituted by an EOR circuit. The input terminal 48 is a clock for latching a track address in the latch circuit 45, that is, a clock for latching data only when a control and display signal in which the track address is recorded from the demodulation circuit 13 is output. Enter

FIG. 13 shows a block address check circuit. In this circuit, the block address in the reproduced signal is compared with the block address generated by the memory control circuit 17, as in the circuit of FIG. If they do not match, the output 52 is set to "1". The block address generated by the memory control circuit 17 is changed from “0” to “255” by the counter.
Are generated sequentially, and if they are normal, they match the block addresses in the reproduced signal. However, if the reproduced signal is shifted for some reason, they do not match.

FIG. 14 shows an error correction device. In FIG.
59 is a bus line, 60 is a syndrome generation circuit, 61 and 62 are R
OM, 65, 67, 69 are RAM, 64 is an arithmetic circuit, 66 is a counter, 68
Is a comparison circuit, 70 is a condition judgment circuit, 71 is a program ROM, 7
2 is an address counter. This circuit includes three bus lines, a circuit connected to the bus lines, and a control circuit that controls the operation of each circuit by a program. A bus line 57 is a data bus for exchanging data such as a received signal and an error pattern. A bus line 58 is a location bus for exchanging data such as a data position.
Is a flag bus for exchanging flag data added to data. Further, a data input / output terminal 78, a location input / output terminal 79, and a flag input / output terminal 80 are connected to each bus.

The syndrome generation circuit 60 generates a syndrome based on the reception signal input from the data input / output terminal 78.

The operation circuit 64 performs an operation for obtaining an error position and an error pattern based on the syndrome generated by the syndrome generation circuit. In the arithmetic circuit, GF
Perform multiplication, division and addition on (2 ^m ).

The RAM 65 is for storing the syndromes and the calculation results of the calculation circuit 65. Reference numeral 63 denotes an eight-input OR circuit for determining whether data on the data bus 57 is "0".

The ROMs 61 and 62 are ROMs for performing data conversion between the data bus 57 and the location bus 58. That is, on the data bus, data is handled in a vector expression, and on the location bus, data is handled in an exponential expression. Therefore, when exchanging data between the data bus 57 and the location bus 58, the data must be converted by the ROM 61 or the ROM 62.

The counter 66 counts the number of flags in one block. C in ₂ decoding, and counts the number of F _0, F ₁ in the counter 66 is compared with a predetermined number by comparing circuit 68 in number, does not perform correction something make a correction of the word, or whether to correct It is determined whether or not the correction is impossible.

The RAM 67 is used to store the number of flags, error positions, and the like counted by the counter 66. The comparison circuit 68 is used for comparing the number of flags described above with a predetermined number, and comparing data and a constant during decoding.

RAM 69 stores C ₁ added to data in C ₂ decoding.
The flags F ₀ and F ₁ indicating the result of decoding are stored. The status of the flag stored in the RAM 69 is used to check the presence or absence of the flag at the error position obtained by decoding.

The condition determination circuit 70 determines whether or not to branch the program based on the result determined by the OR circuit 63 and the comparison circuit 68 and the status of the flag stored in the RAM 69.

The program ROM 71 stores a program for controlling each circuit described above to perform decoding. Reference numeral 73 denotes a signal for determining the address of the RAM and determining constants to be input to each bus line and the comparison circuit. Reference numeral 74 denotes a signal for determining a condition for branching a program.
It decides whether or not to branch by comparing the situation of 9 mag. 7
Reference numeral 5 denotes a signal for determining a branch destination when branching. Also, 7
Reference numeral 6 denotes a signal for controlling a buffer and a register connected to each bus.

The counter 72 controls a program address. This counter advances the address of the program ROM 71 by the clock input from the master clock input 81 and executes the program. When branching a program, a branch destination address 75 is loaded into a counter by a branch instruction 77, and the program is branched. The input terminal 82 is for inputting a signal for resetting the counter 72 at the start of the program.

The procedure for performing error correction, first inputs the received signal, performs generation of the syndrome, and performs the storage of the number of flags counted, the flag status to RAM69 is C ₂ decoding. Next, decoding is performed by a program, an error position and an error pattern are obtained, and error data is corrected. Also, C ₁ decoding and C ₂
If decoding becomes uncorrectable, a flag
The flag to be added to the data is output from 80.

The outputs of the track address check circuit 42 and the block address check circuit 43 are input from the input terminal 56 to the condition determination circuit 30. Then, when decoding by a program, this signal is checked, and the algorithm to be executed may be changed depending on whether it is “1” or “0”.

As described above, by changing the error correction algorithm when a track or block shift occurs, error correction with excellent correction and detection capabilities for both normal and data shifts. Can be done. Also, since the algorithm is changed on the program, other algorithms can be easily handled by changing the program.

In the R-DAT, the code is constituted by a so-called complete code which is encoded for each data in the track. Therefore, the selection of the algorithm by the address check is performed for each data in the track. That is, by performing a track address check in the track, the algorithm is selected depending on whether a mismatch occurs or not.

As another embodiment, there is a method in which an algorithm is selected only when the number of mismatches is equal to or greater than a predetermined number, and a method in which an algorithm is changed only for the data having mismatches.

〔The invention's effect〕

According to the present invention, even when a data interleave shift occurs due to a track shift or a block shift, it is possible to perform error correction with excellent correction ability and detection ability without performing error correction.

[Brief description of the drawings]

FIG. 1 is a block diagram of an R-DAT device, and FIG. 2 is an R-DAT device.
FIG. 3 is a block diagram of data, FIG. 4 is an interleave format, FIG. 5 is a timing chart at the time of recording, FIG. 6 is a timing chart at the time of reproduction, FIG. Figure 8 shows
Flowchart of C ₁ decoding, the flowchart of FIG. 9 is C ₂ decoding, Fig. 10 control, configuration of the display signal, FIG. 11 is a block structure of the playback apparatus of the present invention, FIG. 12 track address check circuit, FIG. 13 shows a block address check circuit, and FIG. 14 shows an error correction circuit. Next, reference numerals will be described. 16 Memory 17 Memory control circuit 18 Error correction circuit 20 Digital-to-analog converter 21 Error correction circuit 27 Memory 28 Memory control circuit 42 Track address check circuit 43 Block Address check circuit 44 OR circuit 45 Latch circuit 46 Match detection circuit 47 SR latch circuit 60 Syndrome generation circuit 61 ROM 62 ROM 63 OR circuit 64 Operation Circuit 65 RAN 66 Counter 67 RAM 68 Comparison circuit 69 RAM 70 Condition judgment circuit 71 Program ROM 72 Address counter

Continued on the front page (72) Inventor Hiroyuki Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi Inside the Home Appliances Research Laboratory, Hitachi, Ltd. ) Inventor Takao Arai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (56) References JP-A-57-46585 (JP, A)

Claims (2)

(57) [Claims] 1. A PCM signal and at least a first of the PCM signal.
A diagonal track in which a large number of signal blocks each including a second two types of error detection / correction parity, a control signal including at least one of a block identification signal and a track identification signal, and a synchronization signal is recorded. The sequentially formed magnetic tape is reproduced, and the magnetic tape is reproduced according to the error detection / correction algorithm based on the error detection / correction parity.
In a PCM signal reproducing apparatus configured to detect and correct an error of a PCM signal, a first error detection and correction by the first error detection and correction parity (that is, error detection and correction) is performed on the reproduced PCM signal. A first error correction circuit that performs a predetermined number of error corrections and generates a flag indicating the state of the first error detection and correction, and inspects the reproduced block identification signal and track identification signal. An error is detected in the reproduced PCM signal by a check circuit and the second error detection / correction parity, and according to a flag indicating a state of the first error detection and correction among the detected errors. First for performing error correction with erasure correction
And the second error detection / correction parity described above, an error is detected in the reproduced PCM signal, and error correction in the first algorithm excluding the error correction of only the erasure is performed. And a second algorithm for performing the error detection and correction on the reproduced PCM signal in accordance with the first or second algorithm. When no abnormality is detected in the signal or track identification signal, error detection and correction of the reproduced PCM signal by the second error detection and correction parity are performed in accordance with the first algorithm, and the block identification signal is checked by the checking means. When an abnormality is detected in the track identification signal or the track identification signal, the second
And a second error detection and correction circuit configured to perform error detection and correction of the PCM signal reproduced by the second error detection and correction parity according to the algorithm of (1). 2. The second error detection and correction circuit according to the second algorithm when the detection means detects that the block identification signal or the track identification signal has become discontinuous. 2. The method according to claim 1, wherein error detection and correction of the reproduced PCM signal are performed by the second error detection and correction parity.
PCM signal playback device.