JPH038613B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application) The present invention relates to a PCM playback device, and in particular to an SHF-player that prevents noise from occurring due to errors.
This product relates to a PCM playback device that can be used for PCM broadcasting, 8mm video PCM audio, helicopter scan tape decks, etc.

(Background) Transmitting and receiving information, or
When information is once recorded and then played back, noise input into the transmission medium or recording medium causes
The reproduced information may not match the original information.

Information converted into a digital signal is transmitted or recorded with a correction code corresponding to the information added to the information, thereby correcting erroneous data during reproduction to achieve faithful reproduction.

FIG. 1 shows an example of a signal format for audio PCM transmission. One frame is composed of 1 to 5 signals. 1 is a frame pattern indicating the beginning of the frame, 2 is a control code indicating the content of information, 3 is a range bit indicating the scale of information, and 4 is an information signal. The information signal 4 has 1 channel to 5 channels (4-1, 4-2, 4-3, 4-
4, 4-5). 5 is a correction code for error correction.

FIG. 2 shows a bit interleave matrix. When the one frame is transmitted, it is transmitted vertically in bit units. From the horizontal axis, 7 bits of the correction code are added to the 56 bits of the 1-bit range information signal. This bit interleaving disperses burst noise and improves the efficiency of correcting error data.

Furthermore, signals other than frame patterns are scrambled to facilitate bit clock reproduction in the receiver.

The above format is used for the audio information part of commercial broadcasting, and is of high quality as PCM audio, but considering the public nature of broadcasting, C/N deterioration in weak electric fields is a problem. Even in this state, it is necessary to output the playback sound.

As described above, the frame pattern is at the beginning of one frame and serves as a reference for reproduction and decoding.
If this frame pattern is not detected, the first
All information in the frame cannot be played back correctly.

Therefore, the conventional PCM reproducing apparatus has the disadvantage that noise (shock sound) may be generated in the output signal when a frame pattern is not detected.

(Purpose) The purpose of the present invention is to reduce noise by outputting correctly reproduced previous frame information when a frame pattern (synchronization signal) is missing or a large number of errors occur due to long burst noise.
Our goal is to provide PCM playback equipment.

(Summary) The present invention prevents the data of the previous frame from being saved when descrambling is not performed correctly due to undetected frame patterns (synchronization signals) and a large number of errors occur, or when it is detected that data cannot be corrected. It is unique in that it stops switching between RAMs in the system and expands and releases the previous frame's data.

Another feature of the present invention is that when a large number of errors or a large number of uncorrectable errors are detected by the means for detecting errors in input data, the previous frame reproduced data is used instead of the intra-frame reproduced data. The point is that it is made to elongate and release.

(Example) The present invention will be explained below with reference to Examples.

FIG. 3 shows an embodiment of the PCM reproducing device of the present invention. The data converted to digital signals is
The signal is input to a synchronization signal detection circuit 6 and a descrambling circuit 7. The output of the synchronization signal detection circuit 6, which detects the frame pattern as a synchronization signal, activates the descrambling circuit 7. The descrambled data is used to remove bit interleaving.
It is input to the RAM write circuit 8.

The RAM is the first RAM (A) 11 and the second RAM (B) 1
There are two types (2), and the write operation and read operation are switched by the switch 10. Each RAM has a capacity for one frame, and in order to solve the bit interleaving shown in FIG. 2, writing is performed in the vertical direction and reading is performed in the horizontal direction.

Reference numeral 9 denotes a correction circuit, which reads data and detects and corrects erroneous data. 13a is an output data expansion control circuit, 13b is each channel
This is an output circuit that separates 1ch to 5ch.

Now, when no frame pattern is detected by the synchronization detection circuit 6, a pseudo synchronization signal (supplementary synchronization signal) is generated as a reference for system operation. However, since the start timing of descrambling has been lost, the next RAM switching is stopped. This causes incorrect data to be written.
RAM is not connected to correction circuit 9. Therefore, in the next frame, data is written to the same RAM as the previous frame, and data is output from the RAM containing the data of the previous frame.

FIG. 4 is a time chart of the circuit operation of FIG. 3. Frame F3 and frame F4
When the synchronization signal between is missing and not detected,
The output data expansion control circuit 13a is activated, and the switching between writing and reading of the first RAM (A) 11 and the second RAM (B) 12 is stopped by the next synchronization signal. As a result, the data read from the first RAM (A) 11 is expanded into two frames by the output data expansion control circuit 13a and output to the output circuit 13b. Note that in the next frame, normal RAM switching is restored.

In this way, when one frame of data is expanded over two frames, the beginning of frame number 5 to be interpolated becomes continuous, as shown in Figure 5.
The data will be close to the correct data. As a result, it is possible to avoid the shock noise caused by erroneous detection of data. Note that FIG. 5 shows a waveform obtained by converting the output of FIG. 3 into an analog signal by a D/A converter.

FIG. 6 shows the second embodiment of the present invention when deinterleave correction and data output are configured with three RAMs.
This is an example. The circuit configuration is almost the same as that in FIG. 14 is the added third RAM (C) 14. First RAM (A) 11, second RAM (B) 12,
The third RAM (C) 14 is controlled by a switching circuit 15. The RAM is responsible for three tasks: writing for deinterleaving, detecting and correcting error data, and outputting data. The difference from the above is that the data is not output together with the correction, but the corrected data is rewritten to the original RAM, and the output is output only.
The reason lies in the provision of RAM.

The switching circuit 15 switches the RAM 11,
12 and 14 while shifting each frame. The connection state of the RAM will be explained with reference to FIG.

In frame F1, the first RAM (A) 11
is the second RAM (B) 1 in the RAM write circuit 8.
2 is connected to the correction circuit 9, and the third RAM (C) 14 is connected to the data output circuit 13. next frame F2
Then each RAM is shifted and the third RAM
(C) 14 is the RAM write circuit 8, the first RAM
(A) 11 is the correction circuit 9, the second RAM (B) 12 is
Connected to data output circuit 13.

Now, if the synchronization signal between frames F2 and F3 is lost, the output data expansion control circuit 13a is activated with a delay of one frame period. Also, the second
The contents of RAM (B) become uncertain. Therefore, the correction in frame F4 is insufficient, and in the next frame F5, the second RAM (B) 12 returns to writing, the first RAM (A) 11 goes to the correction circuit, and the third RAM(C) 14 remains as is. The data read from the RAM(C) 14 is expanded into two frames by the output data expansion control circuit 13a and output to the output circuit 13b. As a result, as in the first embodiment, it is possible to avoid the shock noise caused by erroneous detection of data.

Note that this RAM switching control can be controlled, for example, by
This can be easily done by programming it in ROM or the like.

Further, the first and second embodiments are each
Although the case where two or three RAMs are used has been described, the present invention is not limited to this, and more RAM may be added. In this way, the number of decompressed frames can be made longer than two frames, and even if the synchronization signal is missing over several frames, this can be dealt with.

The above is an explanation of the case where the synchronization signal is missing and the reference point for descrambling becomes unknown and the data cannot be obtained correctly. However, when the synchronization signal is missing and the synchronization signal is replenished at the correct position, the data can be read correctly. be able to. Therefore, detection of synchronization signal,
A third embodiment of the present invention will be described below, in which it is determined whether data has been read correctly regardless of whether it is not detected, and RAM switching is controlled.

Figure 8 is an example. Although it is basically the same as in FIG. 6, the correction circuit 9 controls the switching circuit 15 and starts the output data expansion control circuit 13a. In other words, as a result of detecting data errors by the correction circuit 9, if there are many data errors within the frame, for example, when it is determined that more than half of the data are errors, an abnormality within the frame is detected and the output data is Make the switch.

The timing will be explained with reference to FIG. If there are many errors in the data written to the second RAM (B) 12 in frame F3, the correction circuit 9 detects the number of errors in the next frame F4, and when the detection is finished, that is, frame F4. Between frame F5, the RAM switching circuit 15 is controlled, the third RAM (C) 14 remains connected to the data decompression control circuit 13a, and the first RAM (A) 11 and the second
Switch between RAM(B)12 and RAM(B)12. This allows the second
This prevents the output of error data in the RAM (B) 12.

Next, another embodiment of the present invention will be described. 11 and 12 respectively show the relationship between the head and tape of a helical scan type PCM tape deck and the general structure of the PCM tape deck. 16 is a magnetic tape, and 17 is a trajectory of a recording (or reproducing) head on the tape. One trajectory corresponds to one frame unit. The tape 16 is pulled out from the cassette half 18 and placed in the cylinder 19.
can be wrapped around. The surface to be wrapped is approximately 90° of the cylinder 19. Also, cylinder head 2
Two 0s are provided in the cylinder 19, each with
They are placed at 180° intervals.

FIG. 13 shows the format of the signal recorded on the tape. One frame is divided into three regions: X, Y, and Z. The Y area is located at the center of the tape and is an area where main data is recorded. The X and Z areas are located at the edge of the tape and are allocated to control data and additional data areas.

The main data area Y is composed of 256 blocks from 0 to 255, and one block is shown at 20. Data words in 8-bit units start with a synchronization signal (SYNC), control data (C&D),
Data1, Data2...Data12, Parity1, Parity2,
Consists of Parity3, Parity4, and 16-bit CRCC.

This CRCC is a cyclic code used to detect errors within one block. In addition, the data words within the frame are interleaved (dispersed) in order to increase data correction efficiency.
Parity1 to Parity4 are similarly interleaved. Therefore, in order to correct error data using Parity 1 to Parity 4 during playback, it is necessary to deinterleave the data words and Parity within the frame and rearrange the data.

Since interleaving is completed in one frame, error propagation due to malfunction of deinterleaving can be completed within one frame.

Now, FIG. 9 shows a circuit according to a fourth embodiment of the present invention. 21 is a CRC check circuit for detecting errors within a block of input data. 22 is a synchronization signal detection circuit, and 23 is a RAM select circuit. 24 is a RAM write circuit, 25 and 26 are
RAM, 27 is a data error correction circuit, 28, 2
9 is a RAM changeover switch. 30 is a data output circuit, the output of which is transmitted to the D/A circuit.

Figure 10 shows the RAM select circuit 23 and
3 is a circuit diagram showing a specific example of RAM changeover switches 28 and 29. FIG. That is, this circuit can be composed of a T flip-flop 31 and an inverter 32, as surrounded by a broken line. The T flip-flop outputs a high/low signal in a toggle manner depending on the output of the synchronization signal detection circuit 22 unless the CRC circuit 21 detects an abnormally large number of data errors. (The output of the CRC circuit 21 is normal, and when the H level is abnormal, it becomes the L level.) RAM2
5 and 26 become writable when, for example, a high level signal is input to the write enable terminal WE, and become readable when a low level signal is input.

Next, the basic operation of this embodiment will be explained.

As mentioned above, deinterleaving is necessary depending on the data array format, and writing and reading are performed alternately using the two frame RAMs 25 and 26, and deinterleaving is performed by controlling the read address.

The input data is subjected to data error detection by the CRC check circuit 21, and simultaneously written to the first RAM (A) 25 or the second RAM (B) 26 via the RAM write circuit 24. When the CRC check circuit 21 detects an error in the block, an error flag is added to the written data. The correction circuit 27 converts the error data into correct data using the Parity word and the error flag, and outputs the correct data from the data output circuit 30b.

Next, the operation of this embodiment will be explained in detail with reference to the time chart shown in FIG. Since the tape winding angle is 90 degrees and there are two cylinder heads, the signal from the tape is input for two frames, the sum of heads A and B, for each rotation of the cylinder.
This intermittent data is stored in the first RAM (A) 25 and the second RAM (A) 25.
The data is written alternately to the RAM(B) 26.

Now, in writing to the second RAM (B) 26 at time 31 of the time chart shown in FIG. 14, there are an abnormally large number of error flags (for example, 256 (100 or more errors out of 1), it can be determined that the entire frame has been corrupted by some kind of noise. It is clear that even if the data in the second RAM (B) 26 is sent to the correction circuit as it is, the correction will not be sufficient due to the correction capability. Therefore, RAM select circuit 23
The RAM changeover switches 28 and 29 are controlled via the RAM changeover switches 28 and 29 to stop switching (A) and (B). Then, as shown in the time chart in Figure 14, the output data is the content of the first RAM (A) 25 of the previous frame, and the content of the second RAM (B) 26, which has many errors, is not output. It can be done.

FIG. 15 shows a case where this embodiment is implemented using another correction method. As mentioned above, in this helical scan method, data is input intermittently.

This embodiment utilizes this, and as shown in FIG. 15, the correction circuit is operated during the time from when data input and writing to the RAM are completed until the next writing, and the data to be corrected is ,at the time
A method is used to rewrite the data in RAM. Also, while writing and correcting data in this RAM, data is output from the other RAM (in other words, data from the previous frame is held) at regular intervals (RAM read state). I have to.

On the other hand, time 32 on the time chart (Figure 15)
When the data in the second RAM (B) 26 is corrected, if there is more error data than the correction ability and a large amount of uncorrectable data occurs, RAM switching is stopped in the next frame. Then, the same content as the previous frame is output as the output data, and noise due to incorrectly corrected data or error data can be prevented from being output.

It is clear that the circuit of this embodiment can also be applied to PCM audio of 8 mm video using a rotary head.

(Effects) As described above, according to the present invention, when the frame pattern that is the synchronization signal is not detected and the synchronization signal is not supplemented at the correct position, or when the number of data errors in the frame is extremely large, When the time is up, the RAM corresponding to reading the output data is used in the previous frame.
Since the RAM is maintained and data is output from the RAM, noise (shock sound) in the output signal can be prevented.

Further, by expanding one frame data over two or more frames and outputting the data, it is possible to output data that is close to correct data.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of the data format in a frame, FIG. 2 is a diagram showing a bit interleaving matrix, FIG. 3 is a block diagram of a first embodiment of the present invention, and FIG. 4 is a diagram of the first embodiment. Figure 5 is a time chart showing another example of the operation of the RAM in this example. Figure 5 is a waveform diagram obtained by analog conversion of the output data of this embodiment.
FIG. 7 is a block diagram of the second embodiment of the present invention, FIG. 7 is a time chart explaining an example of the operation of the RAM of the second embodiment, and FIG. 8 is a block diagram of the third embodiment of the present invention. Figure 9 is a block diagram of the fourth embodiment of the present invention, Figure 10 is a circuit diagram showing a specific example of the RAM set circuit and RAM changeover switch in Figure 9, and Figure 11 is a head of a helical scan type PCM tape deck. Figure 12 is a schematic structural diagram of the PCM tape deck.
FIG. 3 is an explanatory diagram of the format of the signal recorded on the tape, FIG. 14 is a time chart showing an example of the circuit operation of the fourth embodiment, and FIG. 15 is an illustration of the operation of the RAM of the fourth embodiment. This is a time chart showing an example. 6... Synchronous signal detection circuit, 7... Descrambling circuit, 8... RAM writing circuit, 9... Correction circuit, 10... Switch, 11, 12, 14...
RAM, 15...Switching circuit, 21...CRC check circuit, 23...RAM select circuit, 25,
26...RAM, 27...correction circuit, 13,30
...Data output circuit.

Claims (1)

[Scope of Claims] 1. A signal obtained by pulse modulating an information signal such as voice is divided into frames on the time axis, and a signal sequence in which an error detection code or correction code is added to the information signal completed within the frame is transmitted. , a PCM reproducing device that reproduces the original information signal from the signal sequence on the receiving side, or a PCM reproducing device that records the signal sequence on a recording medium and reproduces the original information signal from the signal sequence on the reproducing side, 1 means for detecting a synchronization signal at the beginning of a frame; at least two frame data storage means; when data is written in one of the frame data storage means, data is read from one of the other frame data storage means; switching means for detecting and correcting errors in frame data, and switching means for detecting and correcting errors in frame data; and switching means for detecting and correcting errors in frame data; When N (N is a positive integer) playback data 1 in the frame
It is characterized by comprising a time axis expansion means for outputting each of the data a plurality of times, and when the synchronization signal detection means does not detect a synchronization signal, time axis expansion of one frame of reproduced data is provided. PCM playback device. 2 A signal obtained by pulse modulating an information signal such as voice is divided into frames on the time axis, and a signal sequence in which an error detection code or a correction code is added to the information signal completed within the frame is transmitted, and the signal is processed on the receiving side. In a PCM playback device that reproduces the original information signal from a sequence, or a PCM playback device that records the signal sequence on a recording medium and reproduces the original information signal from the signal sequence on the playback side, synchronization at the beginning of one frame is used. means for detecting a signal; at least three frame data storage means; means for error detection and correction of data within the frame; and when data is written in one of the frame data storage means, other frame data storage means; One of the means performs data correction, the other one switches the storage means so that data is read, and the means for detecting and correcting errors in the data corrects errors in the frame data by a predetermined amount. When a large amount of data is detected, or when uncorrectable data is detected, the data is read from the storage means that stores the frame data before the uncorrectable data, and the uncorrectable data is switched so that it is not read out. means, and outputting each of the N reproduced data in the frame multiple times when a larger number of data errors than the expected amount are detected as described above, or when uncorrectable data is detected. The feature is that the device is equipped with a time axis expansion means, and expands the time axis of one frame of reproduced data when a larger number of data errors than a predetermined amount are detected in the frame, or when it is detected that the data cannot be corrected. PCM playback device.