JPS6150538B2 - - Google Patents

Description

Detailed Description of the Invention The present invention provides a PCM signal transmission method in which an error correction code is added when transmitting or recording a PCM signal, and the arrangement order of the PCM signal and error correction code is changed (interleaved). Regarding.

The present invention particularly relates to improvements when adding error detection codes.

FIG. 1 shows an encoder for the PCM signal transmission method as described above. Input terminals indicated by 1L and 1R are supplied with PCM signal sequences SL and SR related to left and right channels formed by PCM modulating a stereo audio signal.
This PCM signal series is processed by the distribution circuit 2, and each channel is converted into a 3-channel PCM signal series.
It is divided into SL ₀ , SL ₁ , SL ₂ and SR ₀ , SR ₁ , SR ₂ . One sample each of the left and right channel audio signals is converted into one word Li and Ri, L ₀ ,
When the PCM signal series SL and SR are continuous as L ₁ , L ₂ ...... and R ₀ , R ₁ , R ₂ ......, each PCM signal series from the distribution circuit 2 is as shown below. .

SL ₀ = (L ₀ , L ₃ , L ₆ , ......) SL ₁ = (L ₁ , L ₄ , L ₇ , ......) SL ₂ = (L ₂ , L ₅ , L ₈ , ...... ) SR ₀ = (R ₀ , R ₃ , R ⁶ , ………) SR ₁ = (R ₁ , R ₄ , R ₇ , ………) SR ₂ = (R ₂ , R ₅ , R ₈ , … …) 6 of the same timing of these PCM signal sequences
By supplying the word to the (mod.2) adder 3, a parity signal Pi as an error correction code is formed. For example, the parity signal P ₀ is formed by (L ₀ R ₀ L ₁ R ₁ L ₂ R ₂ =P ₀ ), and the parity signal sequence SP ₀ is generated from the adder 3 by performing such operations sequentially. As the adder 3, an exclusive OR gate can be used. Further, the parity signal may be formed by serial processing using an exclusive OR gate and a shift register.

PCM signal series SR ₀ , SL ₁ , SR ₁ , SL ₂ , SR ₂ and parity signal series SP ₀ are connected to delay circuits 4a to 4f, respectively.
is supplied to The delay amounts of the delay circuits 4a to 4f are selected to be d, 2d, 3d, 4d, 5d, and 6d, where the unit delay amount is d (word time). Then, the PCM signal sequence SL ₀ and the PCM signal sequence SR ₁₀ appearing at the output of each delay circuit 4a to 4f,
SL ₁₁ , SR ₁₁ , SL ₁₂ , SR ₁₂ and parity signal series
A total of 7 words with the same timing each with SP ₁₀
It is supplied to the CRC encoder 5 for error detection.
A CRC code is formed. CRC (Cyclic
Redundancy Check) is a type of error detection using a cyclic code, in which the code to be transmitted (in this case, a 7-word code) is expressed as a polynomial whose coefficients are each bit, and this polynomial is mod.2), and the remainder generated at that time is added to the code to be transmitted and transmitted. On the receiving side, the code to which this remainder is added is divided by the generator polynomial, and it is divisible and no remainder is generated. When the value is not divisible, it is determined that there is no error, and when it is not divisible and some kind of remainder occurs, it is determined that there is an error.

A check signal series SQ consisting of a CRC code, other PCM signal series SL ₀ , SL ₁₁ , SL ₁₂ , SR ₁₂ and a parity signal series SP ₁₀ are supplied to a mixing circuit 6,
The signal is formed into a channel signal sequence and appears at the output terminal 7. Although not shown, a time-base compression circuit and a synchronization mixing circuit are provided for the output terminal 7 to form a data-missing period similar to the vertical blanking period of a television signal and corresponding to horizontal and vertical synchronization signals. A synchronization signal is added. In this way, the signal format similar to that of television signals is
Originally, the purpose was to enable a video tape recorder for recording and reproducing television signals, such as a helical scan rotary two-head VTR, to record and reproduce PCM signals.

For example, at the timing when L ₀ appears in the PCM signal series SL ₀ , the distribution circuit 2 outputs R ₀ , L ₁ , R ₁ , L ₂ ,
R ₂ appears and a parity signal P ₀ appears from adder 3. Therefore, the CRC encoder 5 has L ₀ , R _0-3d , L _1-
7 words of _6d , R _1-9d , L _2-12d , R _2-15d , P _0-18d are supplied, and the CRC code for these 7 words is
Q ₀ is formed. Therefore, these 7 words
CRC code Q ₀ and synchronization signal as shown in Figure 3
It is inserted and transmitted within one horizontal interval defined by HD.

A decoder for the encoder shown in FIG. 1 is shown in FIG. Data reproduced from a VTR and passed through a synchronization separation circuit and a time base expansion circuit is supplied from an input terminal 8 to a CRC decoder 9. The CRC decoder 9 detects errors in each horizontal section of data, and the detection result is added to each word as a 1-bit discrimination bit as shown by the broken line, and is supplied to the distribution circuit 10. From this distribution circuit 10, six PCM signal sequences SL ₀ , SR ₁₀ ,
SL ₁₁ , SR ₁₁ , SL ₁₂ , SR ₁₂ and parity signal series
SP ₁₀ will appear. Delay circuits 11a and 11f are provided for canceling the amount of delay in the encoder for deinterleaving processing that aligns the timing of each PCM signal series using this parity signal series SP ₁₀ as a reference and restores the original arrangement order. In other words,
The amount of delay of each of the delay circuits 11a to 11f is 6.
d, 5d, 4d, 3d, 2d, d (word time)
It is said that The six words of the PCM signal series restored to the original arrangement order in this way and the parity signal are supplied to the error correction circuit 12. For example, the parity signal P ₀ and the 6 words L ₀ , R ₀ , L ₁ of the PCM signal,
R ₁ , L ₂ , and R ₂ are supplied to the error correction circuit 12, and syndrome S ₀ is formed by calculating L ₀ R ₀ L ₁ R ₁ L ₂ R ₂ P ₀ =S ₀ . If all words have no errors, all bits of syndrome _S0 will be "0". Also, if one word in the PCM signal is erroneous, the error pattern matches syndrome S ₀ , so adding syndrome S ₀ to the word detected as erroneous will correct this. Ru. and error correction circuit 1
The PCM signal corrected in step 2 is supplied to the mixing circuit 13, and the PCM signal series of the left and right channels appear at the output terminals 14L and 14R of the mixing circuit 13.

In the above-mentioned PCM signal transmission method, the PCM signal is temporally interleaved and transmitted, and then deinterleaved on the receiving (playback) side.
Burst errors such as dropouts that occur during transmission can be dispersed into bit error groups.
This can prevent a situation in which a word or more is incorrectly corrected and cannot be corrected.

By the way, a common error detection code is assigned to all data inserted into the horizontal section, so if even one word of the data is erroneous, other correct data will also be detected as being erroneous. It can be done. This means that when random errors that fall within one horizontal interval occur, error correction is likely to be impossible.

In consideration of the above points, the present invention temporally interleaves a PCM signal and an error correction code, and then adds an error detection code.

FIG. 4 shows the configuration of the encoder of the present invention. 15
PCM signals of n channels are supplied to n input terminals denoted by , and the PCM signal sequences of (n-1) channels among them are d ₁ , 2d ₁ , ...... (n-
1) Interleaving is performed by supplying the signals to delay circuits each having a delay length of _d1 . At the same time, the words extracted from each of the PCM signal sequences supplied to the input terminal 15 are sent to the correction encoder 16.
An error correction code sequence is formed by being supplied to the nd ₁ delay circuit. In this way, n PCM signal sequences and one correction code sequence are interleaved by being delayed by different times as d ₁ , 2d ₁ , (n-1) d ₁ , nd _1. What is extracted from each is supplied to the detection encoder 17. And (n-1) PCMs
The signal sequence is supplied to a delay circuit with a delay amount of d ₂ , 2d ₂ , ......(n-1)d ₂ , and the error correction code sequence is
The error detection code sequence from the detection encoder ₁₇ is further supplied to the delay circuit with a delay amount of (n+1)d ₂
is supplied to the delay circuit. PCM not delayed
A signal sequence, a PCM signal sequence, an error correction code sequence, and an error detection code sequence from each delay circuit are taken out to an output terminal 18.

A decoder for the encoder described above is shown in FIG. The PCM signal sequence and error correction signal sequence from the input terminal 19 are (n+1)d ₂ , nd ₂ , ......, 2
Deinterleaving is performed by being supplied to delay circuits having delay amounts of d ₂ and d ₂ respectively, and the error detection code sequence is returned to the original arrangement relationship based on the reference, and the error detection decoder 20 removes the error. is detected.
This detection result is added to each word of each data as shown by the broken line, and the PCM signal sequence is nd ₁ , (n-
1) Deinterleaving is performed by supplying the delay amount of d ₁ , d ₁ to a delay circuit. The signal is returned to the original arrangement relationship based on the error correction code sequence and is supplied to the correction decoder 21, where the error is corrected, and taken out to the output terminal 22.

By using the encoder and decoder with the above configuration, interleaving and deinterleaving are performed for error detection, so errors can be detected for each word in one unit interval during transmission, making it possible to If errors of short length occur randomly, the errors can be effectively corrected.

An embodiment of the present invention will be described below. FIG. 6 shows the configuration of the encoder, and FIG. 7 shows the configuration of the decoder. This example, similar to Figures 1 and 2 above, uses a stereo audio signal.
This is a case where PCM signal sequences SL and SR of left and right channels obtained by PCM modulation are recorded and reproduced by a VTR. In other words, each channel is distributed into three PCM signal sequences by the distribution circuit 2, and one word extracted from each PCM signal sequence is supplied to the (mod.2) adder 3, thereby generating a parity signal. A series SP ₀ is formed. The PCM signal series SR ₀ , SL ₁ , SR ₁ , SL ₂ , SR ₂ and the parity signal series SP ₀ are supplied to the delay circuits 23a to 23e, and the parity signal series SP ₀ is supplied to the delay circuit 2.
3f. The delay amounts of the delay circuits 23a to 23f are determined by assuming that the unit delay amount _d1 is 14 word times, and therefore 14, 28, 42, 56, 70, 84
(word time) is selected for the delay amount.

The PCM signal sequences SL ₀ , SR ₁₀ , temporally interleaved by the delay circuits 23a to 23f are
SL ₁₁ , SR ₁₁ , SL ₁₂ , SR ₁₂ and parity signal series
The 7 words extracted from each SP ₁₀ are CRC
A check signal sequence is supplied to the encoder 5.
SQ ₀ is formed. Next, delay circuits 24a to 24
Interleaving is performed again by g. The unit delay amount d ₂ is selected to be 2 word times, so the delay amounts of the delay circuits 24a to 24g are 2, 4, 6, 8, 10, 12, and 14 (word times), respectively.
It is said that The PCM signal series interleaved in this way SL ₀ , SR ₁₁₀ , SL ₁₁₁ , SR ₁₁₁ ,
SL ₁₁₂ , SR ₁₁₂ , parity signal series SP ₁₁₀ , and check signal series SQ ₁₀ are supplied to mixing circuit 6, and appear at output terminal 7 as a one-channel signal series.

Although not shown, the output signal sequence of the encoder is recorded and reproduced by a VTR in a signal format similar to that of a television signal. One horizontal section with a recording signal at this time is as shown in FIG. In other words,
At the timing when L ₀ in the PCM signal series SL ₀ appears, R _-48 , L _-95 , R _-143 ,
Each word of L _-190 and R _-238 is connected to the delay circuits 24a to 24
A parity signal sequence P _-288 appears at the output of the delay circuit 24f, and a CRC code Q _-42 appears at the output of the delay circuit 24g, and these are mixed and inserted into one horizontal section.

The data reproduced from the VTR and time-axis expanded is supplied to the input terminal 8 of the decoder shown in FIG.
It is supplied to the distribution circuit 10. The PCM signal series from the distribution circuit 10 is supplied to delay circuits 25a to 25f, and the parity signal series is supplied to a delay circuit 25g. Delay circuits 25a to 25g
The distribution circuit 1 has a delay amount that cancels the delay amount of the delay circuits 24a to 24g and performs deinterleaving.
Check signal series from 0 and delay circuits 25a, 2
Each output of 5g is supplied to a CRC decoder 9 to detect errors. The detection result is added to each word as shown by the broken line.

Also, the PCM signal series is transmitted to the delay circuits 26a to 26
f. The delay circuits 26a to 26f have a delay amount that cancels the delay amount of the delay circuits 23a to 23f of the encoder (FIG. 6) and performs deinterleaving, and after deinterleaving, error correction is performed using a parity signal. Errors are corrected in circuit 12. Then, it is returned to the PCM signal series of the left and right channels by the mixing circuit 13 and taken out to the output terminals 14L and 14R.

In the embodiment of the present invention described above, the horizontal section in which L ₀ of the PCM signal sequence SL ₀ is included is defined as H ₀ , and L _0+3o
When the horizontal intermediate point where appears is Hn, the PCM signals included in each of the horizontal sections H ₀ , H ₂ , ......
The PCM signal and CRC code are as shown in FIG. Since the data transmitted in this way is delayed-leaved by the delay circuits 25a to 25g, the data as shown by the broken lines in FIG.
L ₀ , R _-42 , L _-83 , R _-125 , L _-166 , R _-208 , P _-252 ,
_Q6 is fed to the CRC decoder 9. After this error detection, they are deinterleaved by the delay circuits 26a to 26f, so that H ₀ , H ₁₆ , H ₃₂ , H ₄₈ ,
The PCM signals L ₀ , R ₀ , L ₁ , R ₁ , L ₂ , R ₂ included in the horizontal sections of H ₆₄ , H ₈₀ , and H ₉₆ and the parity signal P ₀ are supplied to the error correction circuit 12, Error correction is performed.

As understood from the description of one embodiment above,
In the present invention, error detection is performed in units of seven words of data and CRC code that are diagonally combined in FIG. 9. Therefore, when short burst errors are randomly present, the correction efficiency can be improved more than when error detection is performed for each horizontal section. For example, if the three words L ₀ , R _-42 , and R _-125 are incorrect, according to the present invention, even though the other words L _-83 , L _-166 , R _-208 , and P _-252 are correct, It is judged as a mistake. On the other hand, according to the encoder and decoder configured as shown in FIGS. 1 and ₂ , in order to add an _error detection code to the entire data of one horizontal section, the _horizontal A total of 18 words of data included in the interval are judged to be incorrect even though they are correct. In this way, if the number of correct words that are detected as incorrect can be reduced, it will be possible to prevent uncorrectable words when performing correction decoding, and the correction efficiency can be improved.

Note that a full addition code obtained by fully adding two words may be used as the error correction code, and a parity code or a full addition code may be used as the error detection code. Furthermore, two or more words of error correction code may be added to a plurality of words of the PCM signal. For example, d ₁ in Figure 4,
The delay amount of 2d ₁ , ......, (n-1) d ₁ , nd ₁ is divided and interleaving is performed again, and this new interleaving
An error correction code may be formed from the PCM signal. Furthermore, a shift register circuit or RAM (random access memory) may be used to generate a predetermined amount of delay.

As described above, according to the present invention, the PCM to be transmitted
First, an error correction code is formed on the signal, and then a first delay process is performed so that the PCM signal and the error correction code are interleaved with each other, and the PCM signal sequence that has been subjected to this first delay process is and the error correction code, and performs second delay processing so that the PCM signal and error correction code that have been subjected to the first delay processing are interleaved with the error detection code; Since the PCM signal, error correction code, and error detection code are transmitted after being subjected to delay processing of Since this burst error can be replaced with a random error based on the interleaving performed, the error detection ability can be improved, and the PCM signal in which the error was detected was formed by the first delay processing. Since the signal is further spread based on interleaving, the error correction ability of the error correction code can be fully utilized, and therefore the overall error correction ability can be significantly improved synergistically. Also, 2
Should be transmitted to heavily interleave
Even if one of the codes added to the PCM signal is an error detection code that only detects errors, the error correction ability can be fully demonstrated. In comparison, the processing is performed at high speed, and the overall error correction processing time is shortened.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of an encoder and decoder as an example of the PCM signal transmission method, Figure 3 is a diagram showing the signal form during transmission, and Figures 4 and 5 are used in the present invention. 6 and 7 are block diagrams of the encoder and decoder used in an embodiment of the present invention, and FIG. 8 shows the signal form during transmission. 9 are schematic diagrams used to explain the present invention. 1L and 1R are input terminals to which the PCM signals of the left and right channels of the stereo signal are supplied, 3 is a (mod.2) adder, 5 is a CRC encoder, and 9 is a CRC
Decoder, 12 is an error correction circuit, 4a to 4f, 11
a~11f, 23a~23f, 24a~24g,
25a to 25g and 26a to 26f are delay circuits.

Claims (1)

[Claims] 1 A predetermined number of PCMs from the PCM signal series to be transmitted
Sequentially select signals and select a predetermined number of PCMs selected.
forming an error correction code based on the signal, performing first delay processing on the predetermined number of PCM signals so that the error correction codes interleave each other; and PCM signals subjected to the first delay processing; An error detection code is formed based on the error correction code, and a second delay processing is further performed so that the PCM signal and the error correction code subjected to the first delay processing and the error detection code are interleaved with each other. , transmitting the PCM signal subjected to the second delay processing, an error correction code, and an error detection code.
PCM signal transmission method.