JPH0690859B2 - Digital information signal processing method - Google Patents

Description

The present invention relates to a digital information signal processing method applied when recording and reproducing a digital audio signal together with a video signal, for example.

As one of the rotary head type VTRs, magnetic tape is wound around the table guide drum at 180 ° or more, and scanning is performed by the rotary heads arranged at 180 ° angular intervals, and one field is added to the track in the section of 180 ° at the winding angle. Has been proposed, in which a video signal of 1 field and a digital audio signal for one field are recorded in another section in which two rotary heads are overlapped and scanned.

When the audio signal accompanying this video signal is digitalized, in order to simplify the timing relationship such as clock generation, a frequency (2h) twice the horizontal scanning frequency h is often used as the sampling frequency s. In case of NTSC system (s = 31.5KHz)
Therefore, in the case of two channels such as a stereo signal, the digital audio signal for one field is (525 × 2 = 1050) samples.

By the way, in order to cope with an error due to a dropout during recording / reproduction, the above digital audio signal has a code configuration capable of error correction. There are various kinds of codes of this kind, but one that adds a redundancy code such as parity to a plurality of words in a vertical, horizontal or diagonal direction of a digital audio signal of (m × n) matrix configuration is available. Used. Convolutional error correction codes are not used because they are not suitable for editing. The values of m and n mentioned above are determined so that the error correction capability is as high as possible.

However, the digital audio signal for one field may not always have a matrix configuration of (m × n). So, this invention is one field audio
Like the PCM signal, when the total number of symbols of the digital information signal to be divided into units of error correction coding processing is not divisible by (n or m), digital data having control information of a predetermined number of symbols is added, The total number of symbols is divisible by (n or m).

An embodiment in which the present invention is applied to the rotary head type VTR as described above will be described below.

FIG. 1 shows the data structure of one unit in one embodiment of the present invention. One word is 8 bits, (m = 8 words) (n = 132 blocks) (m × n = 1056 words). Has been done. NT when the sampling frequency is 2h
The SC-type digital audio signal for one field is 1050 words, so 6 words (ID ₀ , ID ₁ ... ID ₅ )
Control data will be added. That is, (L ₀ , R ₀ , L ₁ , R ₁ , L ₂ , R ₂ , ...... L ₅₂₂ , R ₅₂₂ , L ₅₂₃ , R ₅₂₃ )
The above-mentioned 6-word control data is added to the beginning of the digital audio signal for one field continuous with.

In this control data, ID ₀ is a marker word, ID _{1 to} ID ₄ are time codes, ID ₁ (hour), ID
Indicates ₂ (minutes), ID ₃ (seconds), and ID ₄ (field). ID ₅ is
Each of the 8 bits (a _{0 to} a ₇ ) has the following information. a ₀ indicates whether or not this control data is valid, a ₁ and a ₂ indicate the type of digital audio signal (discrimination between monaural, stereo, bilingual, etc.), a
₃ distinguishes between audio information and information for display on one channel, a ₄ a similar distinction on the other channel, and a ₅ and a ₆ at the beginning of recording and Bit ₇ is set to a high level at the end of recording, and a ₇ is a bit for preventing dubbing.

In addition, 1056 words including control data ID _{0 to} ID ₅ are arranged every 2 words at intervals of 44 blocks in the horizontal direction. In hardware, it is written to addresses separated by 44 blocks by the address control of RAM.
Apart from control data or parity data,
Two words (Li, Ri) will be lined up in the horizontal direction. Thus, the reason why the digital audio signal is interleaved by dividing the horizontal direction into three is to increase the burst error length that can be corrected, for example, the average value. Sometimes, (L
By arranging i, Ri) in the horizontal direction, the correction length can be made longer than that in the vertical direction.

Two parities, for example, even parities, are added to the digital audio signal and control data for one field. Assuming that the audio data series of each row of the above matrix structure is W ₀ , W ₁ , ... W ₇ , as shown in FIG. 2, there are 14 blocks or 15 blocks in each data series with a lateral distance. A first parity sequence P is formed from the 8 words to which it belongs. In FIG. 2, the words included in this parity series P are represented by black circles.

Also, a second parity sequence Q is formed from 9 words extracted from each of the audio data sequences W _{0 to} W ₇ and the parity sequence P at a distance of 12 blocks from each of the nine sequences. In FIG. 2, the words included in this parity series are represented by white circles. The first parity series P is arranged at the center of one block, and the second parity series Q is arranged at the end of one block. In other words, the data at the central position in one block has a high probability of being incapable of error correction. Therefore, the parity series P, which is less important than the audio data, is arranged and the parity series P is generated. The parity series Q is arranged at the end of one block in order to maximize the distance between words.

Each block of 132 blocks contains 8 words of digital audio signal and 2 words of parity data,
For error detection for each block data,
A 16-bit CRC code is added, and a block synchronization signal and block address signal are added and recorded on the magnetic tape. For example, when the data of the first block is taken out, it becomes as shown in FIG. This is followed by the second block, the third block ... 132 block.

FIG. 4 shows the configuration of an embodiment of the present invention, in which a recording audio signal is supplied to the input terminal 1 and is digitized by the A / D converter 2. The solid arrow in FIG. 4 indicates the direction of the signal during recording, and the broken arrow indicates
The direction of the signal at the time of reproduction is shown.

The digital audio signal from the A / D converter 2 is RAM
3 or written to RAM4. Each of RAM3 and RAM4 is 1
It can store digital audio signals for a field, and while the input data is being written in one RAM, the previous field data is read from the other RAM and supplied to the P, Q encoder / decoder 6. Then, two parities are formed and this parity is written to the other RAM. As shown in FIGS. 1 and 2, an address generation circuit 5 is provided in each of the memory areas of the RAM 3 and the RAM 4 in order to write predetermined data and read out by interleaving. The address generating circuit 5 is for generating a predetermined block address by an address counter, a ROM and an adder.

Further, the digital audio signal and the parity data read from the RAM3 or RAM4 are supplied to the adder 7, and the block address from the block address generator 8 is added. The output of the adder 7 is serialized by the parallel / serial converter 9 and supplied to the CRC encoder / decoder 10.

CRC encoder / decoder 10, for example ^{(x 16 + x 12 + x} 5
+1) is used as a generator polynomial, and a 16-bit CRC code is generated and added to each block. The operation of the CRC encoder / decoder 10 is controlled by the CRC timing generator 11. In this example, since the FM modulation method is used,
The output of the CRC encoder / decoder 10 is supplied to the FM encoder / decoder 12.

Further, the block synchronizing signal from the synchronizing signal generator 14 is added in the adder 13 and taken out to the output terminal 15. The digital signal taken out from the output terminal 15 is recorded on the magnetic tape by the rotating head.

Further, the digital signal reproduced from the magnetic tape is supplied to the input terminal 16, supplied to the FM encoder / decoder 12 via the synchronization detection circuit 17, and FM demodulated. This FM demodulated reproduction data is supplied to the CRC encoder / decoder 10, and error checking is performed by the CRC code for each block, and the result is taken out as a 1-bit error pointer. This error pointer is the pointer RAM 18 and 19
Memorized in. These pointer RAMs 18 and 19 are RAMs 3 and 4
The error pointer is written at each address of (10 × 132 = 1320 blocks). That is, the block address common to the RAMs 3 and 4 is supplied from the address generation circuit 5 to the pointer RAMs 18 and 19.

Further, the reproduced data is supplied to the RAMs 3 and 4 via the buffer 20 and the serial / parallel converter 21. This buffer 20 is C
It delays the playback data until the error pointer that is the result of the RC check is formed.

As in the case of recording, the RAM3 and RAM4 operate such that, in the field in which the reproduction data is written in one of them, the reproduction data read from the other is error-corrected. When writing the reproduction data to the RAM3 and RAM4, the error word indicated by the error pointer is prevented from being written. Therefore, the pointer RAM18
Or, the error pointer read from 19 is supplied to the timing generator 22, from which the control signal for the RAM 3 or 4 is generated.

The reproduced data read from the RAM 3 or 4 is supplied to the P, Q encoder / decoder 6, error correction is performed using parity, and the error-corrected data is again stored in the RAM 3 or 4
Written in. In this error correction, the error word only needs to have information that this is an error, and therefore, as described above, the error word itself is not written to the RAM 3 or 4. Although error correction cannot be performed if one parity generation sequence includes two or more error words, error correction using the parity P sequence and error correction using the parity Q sequence are alternately repeated. This reduces the number of words that cannot be error-corrected.

The error-corrected reproduction data read from the RAM3 and the RAM4 is supplied to the correction circuit 23, and the error-uncorrectable words are subjected to average value interpolation processing. And this correction circuit 23
The output of is analogized by the D / A converter 24, and the reproduction audio signal is taken out to the output terminal 25. An A / D converter 2 and a D / A converter 24 are provided in correspondence with the signals of 2 channels.

A CPU 26 is provided in order to add the above-mentioned control data ID _{0 to} ID ₅ to the recorded data and to extract this control data from the reproduced data. The inputs / outputs of CPU 26 are coupled to the data buses of RAM3 and RAM4.
The address generation circuit 5 is controlled by the CPU 26, and generates control data at the time of recording.
Write to a specified address in RAM3, 4. The control data is supplied to the P, Q encoder / decoder 6 together with the audio data, where it is encoded for error correction.

In addition, when playing back, along with audio data, RAM3,4
Is written to the RAM 3, 4 and then read out together with the audio data from the RAM 3, 4 and supplied to the P, Q encoder / decoder 6 for decoding the error correction code. Error corrected, RAM
The control data written in 3 and 4 are read out from the predetermined addresses of the RAMs 3 and 4 under the control of the CPU 26, and the CPU can receive this control data and use it for controlling the reproduction operation and the like.

FIG. 5 and FIG. 6 show the code configuration of another embodiment when the present invention is applied to the processing of an audio signal accompanying a CCIR video signal.

In the case of CCIR method, 2 audio signals of 1 field
Sampling with a sampling frequency of h gives 1250 samples. And in FIG. 5, ID ₀
~ Control data similar to that of the above-described embodiment shown by ID ₅ is added, and (157 × 8 = 125)
6 words) have been realized.

Then, interleaving is performed in which every two words of digital data including this control data are arranged in the horizontal direction at intervals of 52 blocks. Since it is an odd number (m = 157 blocks), one word is arranged in the remaining one block, so that the left and right data of the stereo signal are alternately included in each block.

Further, in FIG. 6, as indicated by black circles, the parity series P is formed by 8 words taken out at a distance of 17 blocks from each data series. With this,
As indicated by white circles, the parity series Q is formed by 9 words taken out from each data series at a distance of 14 blocks.

As will be understood from the above description of the embodiments, according to the present invention, for example, an audio signal accompanying a 1-field video signal is converted into a digital signal, and an error correction code is formed in a unit of (m × n) matrix structure. The sampling frequency and the value of m or n can be independently determined. Further, since the data added for this purpose has control information and is subjected to error correction coding processing, it can be effectively used.

Note that the present invention may be applied to a signal other than the audio signal accompanying the video signal, and the code for error correction is not limited to parity, and an adjacent code, a Reed Solomon code, or the like may be used.

[Brief description of drawings]

FIGS. 1, 2 and 3 are schematic diagrams used to explain the code configuration of an embodiment in which the present invention is applied to the processing of an audio signal accompanying an NTSC video signal, and FIG. Block diagrams showing the structure of an embodiment of the present invention, FIGS. 5 and 6 are explanations of the code structure of another embodiment in which the present invention is applied to the processing of an audio signal accompanying a CCIR video signal. It is a schematic diagram used for. 1 …… Audio signal input terminal, 3,4 …… RAM, 6 …… P, Q
Encoder / decoder, 10 …… CRC encoder / decoder, 15 …… recording signal output terminal, 16 …… playback signal input terminal, 18,19 …… pointer RAM, 23 …… correction circuit, 25 …… playback audio signal Output terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Nakano 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa Soni-Atsugi factory (72) Inventor Hisayoshi Moriwaki 4--14, Asahi-cho, Atsugi-shi, Kanagawa No. 1 Soni-Atsugi Plant (56) References JP-A-55-3287 (JP, A) JP-A-57-207960 (JP, A) JP-B-55-48607 (JP, B1)

Claims (1)

[Claims] 1. A digital information signal for a predetermined period is (n ×
m), the digital data having control information for an empty area in the matrix structure, which occurs when the total number of symbols of the digital information signal in the predetermined period is not divisible by (n or m). Is added, and error correction coding is performed in the unit of the matrix configuration consisting of the digital information signal and the digital data.