JPH0518298B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a data transmission device that is applied to a digital VTR that records and plays back digital video signals and a PCM tape recorder that records and plays back digital audio signals.

"Background Art and Its Problems" In a digital VTR, a recorded signal has the data structure shown in FIG. Block synchronization signal
SYNC is located at the beginning of one block, and after that,
The arrangement is such that an identification signal (ID) and address data (AD) are located, followed by data (video data and redundant data for error correction). The identification signal is for identifying the frame, field, or recording channel of the video data of the block, and the address data is for identifying one frame or one recording channel to which the data of the block belongs.
This indicates the address within the field. The address data is data that changes regularly, for example, a continuous number.

In a conventional digital VTR, each of the identification signal, address data, and data (digital video data) is independently encoded with an error detection or correction code. This is because if there is an error in the address data, it becomes unclear which address in memory the played video data should be written to. In other words, the spatial position of the played data on the screen becomes undefined. This is because it is necessary to detect at least the presence or absence of errors in the address data, and it is also necessary to detect and correct errors in the video data itself.
When an error in video data cannot be corrected, it is possible to correct the error data using surrounding correct data.

If a common error detection or error correction code is applied to both, it becomes unclear which of the address data and the video data is in error. As a result, even if the address data is correct but part of the video data is erroneous, it will not be written to the memory, and the data previously written to the memory will be used as playback data.
As a result, the quality of the reproduced image deteriorates.

However, if error correction encoding is performed separately on the identification signal and address data and the video data, redundant data will be generated in each encoding.
A problem arises in that the recorded data becomes more redundant.

OBJECT OF THE INVENTION The object of the present invention is to realize a data transmission device in which the redundancy of one block is reduced and the subsequent signal processing can be performed satisfactorily.

``Summary of the Invention'' This invention adds an error detection code to both one block of digital data and regularly changing address data indicating the order of this digital data, and performs normal playback on a digital VTR. In such a sequential transmission mode, address data is interpolated using regularity, and the correct address data after interpolation is replaced with the received address data. The system is designed to detect errors.

"Embodiment" Hereinafter, an embodiment in which the present invention is applied to a digital VTR will be described with reference to the drawings.

As shown in FIG. 2, in this embodiment, an error detection code such as an adjacent code (b-
Recording is performed by adding parity codes P and Q (adjacent code). When there are m words of identification signal and address data A ₁ to _{A n} (one word is 8 bits, for example) and n words of data D ₁ to _{D o} , the two parity codes P and Q are It is also formed by Eq.

P= _n 〓 ⁱ⁼¹ A _{i o} 〓 ⁱ⁼¹ D _j Q= _n 〓 ⁱ⁼¹ T ^m+n+1-i Ai _o 〓 ^j=1 T ^n+1-j Dj In the above equation, (mod.2), T
is the companion matrix of adjacent codes
shows.

Such an error detection code parity code P,
The Q-added recording signal is recorded on a magnetic tape by a rotating head. For example, two parallel tracks are simultaneously formed by two channel heads, and a recording signal for 1/4 field is recorded on each track. Frame ID signal among identification signals,
The field ID signal and channel ID signal do not change within one track. Further, the address data is a consecutive number indicating the order of all blocks included in one field. The reproduction signal reproduced from the magnetic tape by the rotary head is transmitted through a rotary track, a reproduction amplifier, a waveform shaping circuit, a bit clock extraction circuit, a block synchronization detection circuit, and a multiplexer (not shown) as indicated by 1 in FIG. Supplied to the input terminal.

This reproduced data is supplied to the channel decoder 2. This channel decoder 2 is provided in correspondence with a channel encoder which converts 1 word of 8 bits into 1 word of 10 bits during recording, and reproduced data converted to 1 word of 8 bits appears at its output. This reproduced data is supplied to a TBC (time base correction circuit) 3, and time base fluctuations in the reproduced signal are removed. The output of this TBC3 is ID/
The signal is supplied to the AD interpolation circuit 4.

Although not shown, this ID/AD interpolation circuit 4 interpolates the identification signal and address data using their respective regularities. During normal playback, as mentioned above, the frame ID signal of the identification signal,
Since the field ID signal and channel ID signal do not change during one track, a correct identification signal can be completely obtained by, for example, majority logic. Furthermore, since the address data is in the form of consecutive numbers, by utilizing this regularity, correct address data can be completely reproduced during normal reproduction.

The output data of the ID/AD interpolation circuit 4 is supplied to the error correction circuit 5, and error detection and error correction are performed on the data. In addition to the encoding that generates the parity codes P and Q described above, the video data is also subjected to unique error correction encoding. For example, a predetermined number of blocks are arranged in a matrix, and data contained in the same column and row is subjected to error correction encoding using simple parity or adjacent codes. The output of this error correction circuit 5 is supplied to an error detection circuit 6,
Error detection is performed on the identification signal, address data, and data for each block. During normal playback, the identification signal and address data are ID/AD.
Since the data is determined to be correct by the interpolation circuit 4, the error detection circuit 6 substantially detects errors only in the data.

FIG. 4 shows an example of the error detection circuit 6. In the figure, 8-bit parallel data is supplied to an input terminal 11, and is supplied to arithmetic circuits 13 and 14 via a latch 12. The arithmetic circuits 13 and 14 are constituted by exclusive OR gates and perform (mod.2) arithmetic operations.
The outputs of the arithmetic circuits 13 and 14 are sent to the latches 15 and 16.
is supplied to A reset pulse is supplied to the latches 15 and 16 from a terminal 17. Further, the output of the latch 15 is fed back to the arithmetic circuit 13 and is also supplied to the comparator circuit 18, and the output of the latch 16 is fed back to the arithmetic circuit 13 via the arithmetic circuit 19.
The signal is fed back to the comparator circuit 20. This arithmetic circuit 19 is a circuit that multiplies an input by a matrix T.

One block of identification signals, address data (A ₁ -A _n ), and data (D ₁ -D _o ) are supplied word by word from latch 12 to arithmetic circuits 13 and 14. At a timing before this one block of (m+n) words is supplied, latch 1 is connected from terminal 17.
Therefore, the first word _A1 of one block is output as it is from the arithmetic circuits 13 and 14 and is output to the latch 1.
5, 16. When the next word A ₂ is supplied to the arithmetic circuits 13 and 14, (A ₂ A ₁ ) and (A ₂ TA ₁ ) appear as their outputs, which are taken into the latches 15 and 16. Furthermore, when the next word A ₃ is supplied to the arithmetic circuits 13 and 14, (A ₃ A ₂ A ₁ ), (A ₃ TA ₂
T ² A ₁ ) appears and is captured in latches 15 and 16. Thereafter, similar operations are repeated. Then, one parity code P of one block is supplied to the arithmetic circuit 13, the other parity code Q is supplied to the arithmetic circuit 14, and when the output is taken into the latches 15 and 16, this latch is The outputs of 15 and 16, that is, the syndromes S ₁ and S ₂ are expressed by the following formulas.

……DnP S ₁ =A ₁ A ₂ ……AmD ₁ D ₂ …… _n 〓 ⁱ⁼¹ Ai _o 〓 ^j=1 DjP S ₂ =T ^m+n A ₁ T ^m+n-1 A ₂ ……T ⁿ⁺¹ Am T ⁿ D ₁ T ^n-1 D ₂ ...TD _o Q = _n 〓 ⁱ⁼¹ T ^m+n+1-i Ai _o 〓 ^j=1 T ^n+1-j DjQ This latch 15, Comparing circuits 18 and 20 check whether syndromes S ₁ and S ₂ appearing at the respective outputs of 16 are 0 in all 8 bits. Each of the comparison circuits 18 and 20 has a terminal 21,
Data of all 8 bits from 22 to 0 is supplied,
In addition, the comparison circuits 18 and 20
The comparison operation is performed at the timing when S ₁ and S ₂ are determined. If even one bit of the syndromes S ₁ and S ₂ is not 0, an output that becomes 1 (high level) is generated from the comparison circuits 18 and 20, and this comparison output is
It is taken into latch 24 via OR gate 23. An error flag (1 when there is an error and 0 when there is no error) is output to the output terminal 25 of this latch 24.

Although not shown, the error detection circuit 6 is provided with a delay circuit that delays the reproduced data during the period in which the above-described error detection is performed, and the reproduced data and the error flag are supplied to the frame memory 7 in synchronization. . In the frame memory 7, reproduced video data and accompanying error flags are written at addresses corresponding to the address data. in this case,
Only video data whose error flag is 0 and is determined to have no error is written to the frame memory 7, and video data whose error flag is 1 and which is determined to have an error is prohibited from being written to the frame memory 7, and the error flag is only is written. Although the video data has already been corrected by the error correction circuit 5, the error detection circuit 6 finally detects errors that cannot be corrected and erroneous corrections.

Video data and error flags are sequentially read from frame memory 7 and supplied to correction circuit 8. This correction circuit 8 uses average value interpolation or the like to make errors less noticeable. The output of the modification circuit 8 is then supplied to the D/A converter 9, and an analog reproduced video signal appears at its output terminal 10.

In the embodiment of the present invention described above, during normal playback when the running speed of the magnetic tape is the same as during recording, the rotary head regularly scans the tracks, so that the identification signal changes regularly depending on the track being played back. However, the address data is also a consecutive number, and these are the ID/AD interpolation circuit 4.
This allows complete interpolation correction. Therefore, the error detection circuit 6 substantially detects errors only in the data and parity codes P and Q.

Furthermore, during non-normal playback (also called stunt playback or shuttle playback) in which the running speed of the magnetic tape is faster or slower than during recording, the scanning locus of the rotating head may cross multiple tracks. Become. Therefore, the reproduced identification signal and address data change irregularly, and even if a certain degree of interpolation is possible, complete interpolation cannot be expected. During this non-normal reproduction, the error detection circuit 6 detects errors in both the identification signal, address data, data, and parity codes P and Q. As a result of this error detection, writing of video data determined to have an error into the frame memory 7 is prohibited.

"Application Example" Since the adjacent code is an error-correctable code, it may be configured to perform not only error detection but also error correction. During normal playback, as mentioned above, the identification signal and address data are completely interpolated.
Since the data can be corrected, error detection and error correction can be performed on the data, and effective error correction can be performed without being influenced by the identification signal and address data.

Further, as the error detection code, simple parity, CRC code, etc. can be used. Further, the present invention is applicable not only to digital VTRs but also to digital data transmission devices such as digital audio tape recorders and has similar advantages. Further, the address data is not limited to consecutive numbers, and data with regularity such as numbers that change by a predetermined difference can be used.

"Effects of the Invention" According to this invention, since a common error detection code is added to both address data and data, redundancy is reduced compared to the case where separate error detection codes are added to each. It can be reduced. In this invention, since address data that changes regularly is used, in a sequential transmission mode such as normal playback of a digital VTR, address data can be interpolated without using error detection and error correction codes. Can be completely corrected. Therefore, error detection is essentially performed only on data. Furthermore, in the non-sequential transmission mode, errors are detected for both address data and data, and an error flag can be generated for subsequent signal processing, such as writing into a frame memory.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing an example of the data structure in a digital VTR, FIG. 2 is a schematic diagram showing the data structure in an embodiment of the invention, and FIG. 3 is a diagram showing the structure of an embodiment of the invention. FIG. 4 is a block diagram of an example of an error detection circuit in an embodiment of the present invention. 4...ID/AD interpolation circuit, 6...Error detection circuit, 7...Frame memory, 8...Modification circuit.

Claims (1)

[Scope of Claims] 1. A digital information signal, regularly changing address data indicating the order of the digital information signal, and error detection encoding performed on the digital information signal and the address data in common. A data transmission device that transmits data in units of blocks consisting of generated redundant data, at least in sequential transmission mode, comprising: interpolation means for interpolating the address data using the regularity; an error detection means to which the interpolated address data, the received digital information signal and the redundant data are supplied, and perform error detection on substantially only the digital information signal; and the digital information from the error detection means. A data transmission device comprising memory means in which an information signal is written at an address corresponding to said address data.