JPS5990440A - Data transmitter - Google Patents

Abstract

PURPOSE:To make redundancy less than the case where an individual error detecting code is provided by adding the error detecting code in common to both digital data of one block and address data changing regularly and representing the order of the digital data. CONSTITUTION:The error detecting code, e.g., parity codes P, Q of adjacent codes, are added to an identification signal at each block, address data and data to perform recording. This reproducing signal is supplied to a channel decoder 2, reproducing data converted to 1 word, 8 bits appears at the output, the data is supplied to a TBC (time axis compensating circuit) 3, where the time axis fluctuation of the reproducing signal is eliminated. The output of the TBC3 is supplied to an ID/AD interpolating circuit 4. The ID/AD interpolating circuit 4 reproduces completely a correct identification signal and a correct address data at the normal reproduction, they are supplied to an error correction circuit 5, and after the error correction and detection are performed with respect to the data, the data is supplied to an error detecting circuit 6, and the error detection to the identification signal, address data and data is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device that is applied to a digital VTR that records and plays back digital video signals and a PCM tape recorder that records and plays back digital audio signals.

"Background Art and Its Problems" In a digital VTR, a recording signal has a data structure shown in FIG. Block synchronization signal 5YNC is located at the beginning of one block, and after that.

The arrangement is such that an identification signal (ID) and address data (AD) are located, followed by data (video data and redundant data for error correction). The identification signal is for identifying the frame, field, or recording channel of the video data of the block, and the address data is for identifying the frame, field, or recording channel of the video data of the block.
This indicates an address within a frame or one field. The address data is data that changes regularly, for example, a continuous number.

In conventional digital VTRs, separate error detection or error correction encoding is applied to each of the identification signal and address data, and a redundant code of the error detection or error correction code is inserted. Therefore, there is a problem that the degree of redundancy increases.

"Purpose of invention" In this invention, the redundancy of one block is reduced.

However, the purpose of this invention is to realize a data transmission device necessary for subsequent signal processing.

``Summary of the Invention'' This invention adds an error detection code to both one block of digital data and regularly changing address data indicating the order of this digital data, so that normal playback in a digital VTR is In such a sequential transmission mode, the address data is interpolated using regularity, and the correct address data after this interpolation is replaced with the received address data by an error detection code.

Error detection is performed essentially only on digital data.

"Embodiment" Hereinafter, an embodiment in which the present invention is applied to a digital VTR will be described with reference to the drawings.

As shown in FIG. 2, in this embodiment, an error detection code, for example, an adjacent code (b-+djacent
Recording is performed by adding parity codes P and Q (code). If there are m words of identification signal and address data A, "-'Am (one word is 8 bits, for example), and n words of data DI"Dn, then the two parity codes P and Q are as follows.

Each is formed by the following formula.

In the above formula, ■ represents the addition of (mod, 2),
T is.

The companion matrix of adjacent codes
x).

A recording signal to which such an error detection code is added is recorded on a magnetic tape by a one-rotation head. For example, recording signals corresponding to the yield of two parallel tracks are recorded on two channels. Freno\ID signal among identification signals,
Field ID signal.

The channel ID signal does not change within one track. Further, the address data is a consecutive number indicating the order of all blocks included in one field. The reproduction signal reproduced from the magnetic tape by the rotary head passes through a one-rotation transformer (not shown), a reproduction amplifier, a waveform shaping circuit, a pit clock extraction circuit, a pull synchronization detection circuit, and a multiplexer. This playback data is supplied to the input terminal shown in FIG. The playback data converted to 8 bits per word appears at its output. This reproduced data is supplied to a TBC (time base correction circuit) 3, and time base fluctuations in the reproduced signal are removed. The output of this TBC 3 is supplied to the /AD interpolation circuit 4.

'This ID/AD interpolation circuit 4, although not shown in the drawing, captures the identification signal and address data using their respective regularities. During normal playback, as mentioned above, the frame ID signal, field ID signal, and
Channel ID signal.

Since it does not change within one track, a correct identification signal can be obtained completely, for example, by majority logic. Also,
Address data is a sequential number, so by using this regularity.

Correct address data can be completely reproduced during normal reproduction.

From this, the output data of the /AD interpolation circuit 4 is supplied to the error correction circuit 5, and error detection and error correction are performed on the data. video data.

Error correction encoding is performed separately from the identification signal and address data. For example, if a predetermined number of blocks are
Error correction encoding using simple parity or adjacent codes is performed on data contained in the same column and the same row. The output of this error correction circuit 5 is supplied to an error detection circuit 6, and errors in the identification signal, address data, and data are detected. During normal playback, the identification signal and address data are determined to be correct by the D/AD interpolation circuit 4, so the error detection circuit 6 essentially detects errors only in the data and parity codes P and Q. Ru.

FIG. 4 shows an example of the error detection circuit 6. In the same figure, data of 8 bits (8 bits) is supplied to the input terminal indicated by 11, and is passed through the latch 12 to the arithmetic circuits 13 and 14.
supplied to The arithmetic circuits 13 and 14 are composed of exclusive OR gates, (mod, 2
). The outputs of the arithmetic circuits 13 and 14 are supplied to latches 15 and 16. This latch 15
．． On the 16th.

A reset pulse is supplied from terminal 17. Also.

The output of the latch 15 is fed back to the arithmetic circuit 13 and also supplied to the comparator circuit 18, and the output of the latch 16 is fed back to the arithmetic circuit 14 via the arithmetic circuit 19 and is supplied to the comparator circuit 20. This arithmetic circuit 19 is a circuit that multiplies an input by one matrix T.

1 block of identification signal and address data (A.

~Am) and data (D+~Dn) are supplied word by word from the latch 12 to the arithmetic circuits 13 and 14.

At a timing before this one block (m + n) word is applied, a pulse is applied from terminal 17 to reset latch 15,16, and thus.

The first word A1 of one block is processed by the arithmetic circuit 13.1.
4 is output as is and taken into latches 15 and 16. When the next word A2 is supplied to the arithmetic circuit 13゜14, (A2■Al), (Ay
■TA,) appears and is taken into the latches 15° and 16. Furthermore, when the 9th order word A8 is supplied to the arithmetic circuit 13.14, as its output, (A, ■person, ■A, 1
), (AB■TA2■T"A,) appear and are taken into the latches 15 and 16. Hereafter, the same operation is repeated. Then, one parity code P of one block is supplied to the arithmetic circuit 13. , the other parity code Q is supplied to the arithmetic circuit 14, and its output is sent to the latch 1.
5.16, this latch 15.16
The output of , ie, the syndome S1+82, is expressed by the following equation.

S, =A, ■A2■・・・・・・■Am■D1■D2
■・・・・・・・・・■Dn■P 82 =TT+1" A1 ■Tm+n-t A, ■
""Q+T"'Am■TnD1■Trl"''1.■...
...■TD ■Q The syndromes S, , S, appearing at the respective outputs of the latches 15 and 16 are the comparator circuit 18.
At step 20, it is checked whether the 8 bits are all 0.

Each of the comparison circuits 18.20 has terminals 21.22 to 8.
Data with all bits being 0 is supplied, and also.

This comparison circuit 18.20 has the syndrome s, IS2
The comparison operation is performed at the required timing. If the syndome S, , S, is not O even if it is 1 bit +, the output that becomes 1 (high level) is the comparator circuit 18.20
This comparison output is taken into the latch 24 via the OR gate 23. Output terminal 2 of this latch 24
5, an error flag (1 when there is an error; 0 when there is no error) is taken out.

Although not shown in the figure, the error detection circuit 6 is provided with a delay circuit that delays the reproduced data during the above-described error detection period, so that the reproduced data and the error flag are synchronously supplied to the frame memory 7. Ru. In the frame memory 7, reproduced video data and accompanying error flags are written at addresses corresponding to the address data. In this case, only video data for which the error flag is O and is determined to be free of errors is written to the frame memory 7.

When the error flag is set to 1, the video data determined to have an error is prohibited from being written into the frame memory 7, and only the error flag is written. Although the video data has already been corrected by the error correction circuit 5, errors that cannot be corrected and incorrect corrections are finally detected by the error detection circuit 6.

Video data and error flags are sequentially read out from frame memory 7 and supplied to correction circuit 8. In correction circuit 8, errors are made inconspicuous by means of average value interpolation or the like. The output of the modification circuit 8 is then supplied to the D/A converter 9.

An analog/4G playback video signal appears at the output terminal 10.

In the embodiment of the present invention described above, during normal playback when the running speed of the magnetic tape is the same as during recording, the nine-rotation head regularly scans the tracks, so that the identification signal changes regularly depending on the track being played back. However, the address data is also a consecutive number, and these are I
The D/AD interpolation circuit 4 can perform complete interpolation correction. Therefore, the error detection circuit 6 substantially detects errors only in the data and parity hoods P and Q.

Also, the running speed of the magnetic tape compared to when recording.

During non-normal playback (also referred to as stand playback or shuttle playback) that is made faster or slower, the scanning trajectory of the rotary head traverses one or more tracks. Therefore, the reproduced identification signal and address data change irregularly.

Even if it is possible to interpolate to a certain degree, complete interpolation cannot be expected. During this non-normal playback, the error detection circuit 6 detects errors in both the identification signal, address data, data, and parity codes P and Q. Writing to frame memo 'J7 is prohibited.

"Application Example" Since the adjacent code is an error-correctable code, it may be configured to perform not only error detection but also error correction. During normal playback, as mentioned above.

Since the identification signal and address data can be completely interpolated and corrected, error detection and error correction can be performed on the data, and effective error correction can be performed without being affected by the identification signal and address data. be able to.

In addition, error detection codes include simple parity, CR
This can be done using C code etc. Further, the present invention can be applied not only to digital VTRs but also to digital data transmission devices such as digital audio tape recorders and has similar advantages. Further, the address data is not limited to consecutive numbers, and data with regularity such as numbers that change by a predetermined difference can be used.

"Effects of the Invention" According to this invention, since a common error detection code is added to both address data and data, redundancy is reduced compared to the case where separate error detection codes are added to each. It can be reduced. In this invention, since address data that changes regularly is used, in a sequential transmission mode such as normal playback of a digital VTR, the address data can be completely processed by interpolation even without using error detection and error correction codes. Can be corrected. Therefore, error detection is substantially performed only on data. In addition, in non-sequential transmission mode, error detection is performed for both address data and data.
It is possible to generate an error flag for subsequent signal processing, for example, writing to a frame memory.

[Brief explanation of the drawing]

FIG. 1 is a route map showing an example of the data structure in a digital VTR, FIG. 2 is a route map showing the data structure in an embodiment of the present invention, and FIG. 3 is a route map showing an example of the data structure in an embodiment of the present invention. FIG. 4 is a block diagram showing an example of an error detection circuit according to an embodiment of the present invention. 4...From/ADMI circuit, 6...
Error detection circuit, 7... Frame memory, 8.
...Modification circuit. Agent Masato Sugiura

Claims (1)

[Scope of Claims] Address data that changes regularly and indicates the order of the digital data is added to the digital data that is transmitted in blocks. Data to which an error detection code is added to the address and digital data of one block is transmitted, and at least in the sequential transmission mode, the address data is interpolated using the regularity described above. The data transmission device replaces the correct address data after interpolation with the received address data, and performs error detection on substantially only digital data using the error detection code.