JPS63107056U - - Google Patents

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Publication number
JPS63107056U
JPS63107056U JP20096286U JP20096286U JPS63107056U JP S63107056 U JPS63107056 U JP S63107056U JP 20096286 U JP20096286 U JP 20096286U JP 20096286 U JP20096286 U JP 20096286U JP S63107056 U JPS63107056 U JP S63107056U
Authority
JP
Japan
Prior art keywords
data
cpu2
transmission device
cpu1
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20096286U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20096286U priority Critical patent/JPS63107056U/ja
Publication of JPS63107056U publication Critical patent/JPS63107056U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例によるデータ伝送
装置のブロツク図、第２図は送信回路の処理プロ
セスを示したフロー図、第３図は受信回路の処理
プロセスを示したフロー図、第４図はデータの説
明図、第５図は従来の伝送装置のブロツク図であ
る。 ＣＰＵ１……受信回路、ＣＰＵ２……送信回路
。 Fig. 1 is a block diagram of a data transmission device according to an embodiment of this invention, Fig. 2 is a flow diagram showing the processing process of the transmitting circuit, Fig. 3 is a flow diagram showing the processing process of the receiving circuit, and Fig. 4 is a flow diagram showing the processing process of the receiving circuit. The figure is an explanatory diagram of data, and FIG. 5 is a block diagram of a conventional transmission device. CPU1...reception circuit, CPU2...transmission circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のデータの夫々にアドレスビツトを設ける
と共に、該複数のデータをアドレス順に送信する
送信回路（ＣＰＵ２）と、該送信回路（ＣＰＵ２
）から送信されてくるデータのアドレスが予め定
められた所定の順序になつているか否かを検出す
ると共に、該送信されてくるデータのアドレス順
が所定の順序になつていないときに前記送信回路
（ＣＰＵ２）にデータの送り直しを指示する受信
回路（ＣＰＵ１）とを備えてなるデータ伝送装置
。 A transmitting circuit (CPU2) that provides address bits for each of a plurality of data and transmits the plurality of data in address order;
) detects whether or not the addresses of data transmitted from A data transmission device comprising a receiving circuit (CPU1) that instructs (CPU2) to resend data.
JP20096286U 1986-12-26 1986-12-26 Pending JPS63107056U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20096286U JPS63107056U (en) 1986-12-26 1986-12-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20096286U JPS63107056U (en) 1986-12-26 1986-12-26

Publications (1)

Publication Number Publication Date
JPS63107056U true JPS63107056U (en) 1988-07-11

Family

ID=31163971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20096286U Pending JPS63107056U (en) 1986-12-26 1986-12-26

Country Status (1)

Country Link
JP (1) JPS63107056U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5980037A (en) * 1982-10-29 1984-05-09 Nissan Motor Co Ltd Data transmitting system
JPS5983429A (en) * 1982-11-04 1984-05-14 Mitsubishi Electric Corp Information transfer device
JPS5990440A (en) * 1982-11-13 1984-05-24 Sony Corp Data transmitter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5980037A (en) * 1982-10-29 1984-05-09 Nissan Motor Co Ltd Data transmitting system
JPS5983429A (en) * 1982-11-04 1984-05-14 Mitsubishi Electric Corp Information transfer device
JPS5990440A (en) * 1982-11-13 1984-05-24 Sony Corp Data transmitter

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