JPS5980037A - Data transmitting system - Google Patents

Abstract

PURPOSE:To check the correctness of data with an exclusive OR of both received bits and to check accurately the data, by providing a check bit as well as a data bit to each slot and transmitting the logic of the check bit with inversion for each frame. CONSTITUTION:A time-division multiplex signal S1 to be transmitted is transferred to a receiving station 3 in the form of a signal S through a transmitting station 2 containing an input interface 5, a microcomputer 6, a P/S converter 7 and an optical transmitter 8. Each frame F of the signal S1 is formed with slots SL0-SL2 which are divided equally to the multiplex degree. At the same time, a start for start-stop/tuning purpose, stop bits ST and SP, and a check bit CB are provided before and after data bits D0-D6 obtained by encoding the channel signal of each of slots SL0-SL2. Then an exclusive OR is obtained between the bit CB and the bits D0-D6 of the signal S1 received at the station 3. Thus the data is checked with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an L' data transmission system that improves data error detection efficiency.

Data transmission systems that encode and transmit information include, for example, an optical multiplex transmission system as shown in FIG.

The system shown in the figure consists of a plurality of channel control signals (output v
After encoding the operation control signal of the Z station 4, it is transmitted from the optical transmitter 8 as a time division multiplexed signal S, and this time division multiplexed signal S is received by the optical receiver 9 of the receiving station 3. The control signal is converted to the original control signal and supplied to a predetermined output device 4, and has a configuration of a so-called serial transmission system.

The microcomputer 6 on the transmitting station 2 side converts the control signal input via the input interface 5 into data in a predetermined format and outputs it at a predetermined timing. is converted into a serial signal by a parallel/serial converter 7 and then supplied to an optical transmitter 8.

On the transmitting station 3 side, after the signal S received by the optical receiver 9 is amplified by the amplifier 10, the comparator 11 picks up only the data and tabular components above the reference level, and the serial/parallel converter 12 converts the signal into parallel data. It is converted into and input to the microcomputer 13.

The microcomputer 13 forms an original control signal based on the input parallel data and supplies it to the output device 4 via the output interface 14.

Then, the time division multiplexed signal S is as shown in FIG.
It consists of frames that are repeatedly output at a constant period, and each frame is divided into slots S, which are formed by dividing the frame equally to the multiplicity (3 channels in the figure).
It is composed of L◯ to SL2.

Further, each slot has data bits D encoding a control signal of the corresponding channel. - Start bit ST and stop bit S for asynchronous synchronization before and after D6
P is added, and a parity bit PB for error detection is added immediately after the data bit D6.

By the way, in data transmission, data errors are usually detected to increase the reliability of the data, and the most widely used method for detecting errors is the data bit method, as described above.

There is a parity check method that adds a parity bit PB to Do''-D6.

This parity check method uses IQIZI in the parity bit PB so that the number of "1 bits" in one slot (excluding start bit ST and stop bit SP) is always an odd number (or even number) on the transmitting side. 1", and the receiving side determines that the received data is an error if the number of II 1 II in the data bit and parity bit is an even number (or an odd number). It is.

This eliminates noise during data transmission, such as power supply noise and high-frequency noise generated from microcomputers.
In the optical transmission type, when data becomes different from the original due to the influence of disturbance light noise, etc., this erroneous data can be detected to some extent and eliminated.

In addition, the optical multiplex transmission system shown in Figure 1 has recently been installed in vehicles, and transmits on-vehicle load control signals through optical fibers, photocouplers, etc., instead of conventional electric wire harnesses. There is something like this.

As an example, as shown in FIG. 3, a horn switch 23.
Radio switch 24. There is a steering switch system equipped with an ASCD (automatic speed control device) switch 25, etc.

The operation input signal of the above switch is transmitted to the transmitting station 26.
The signal is converted into a serial data signal, transmitted from the optical transmitter 27 to the optical receiver 28, and input to the receiving station 29. Then, the receiving station 29 converts the input received signal into the original control signal and supplies it to the designated on-vehicle load.

Note that the center pad 22 shown in the figure is not connected to the steering shaft 30, and is configured so that even if the steering wheel 21 is rotated, the center pad does not rotate and maintains its original position. . This is done to improve the operability of the switches on the pad 22.

Therefore, it is possible to transmit more signals than the conventional contact type slip ring, which transmits electrical signals. can be provided.

However, in the data transmission method using the parity check method as described above, if an error occurs in an even number of bits in one slot due to noise or the like, this data error cannot be detected.

Also, for the above steering switch system.

When the parity check method is used, when the steering/h goal 21 is rotated, the steering spoke 21a passes through the optical transmission path (as shown by the imaginary line in FIG. 3), so that the transmitted light is instantaneously This results in erroneous data being input to the two receiving stations. At this time, if there is an error in an even number of bits in the data, this error cannot be detected.

For this reason, an error detection method with higher detection accuracy is required, especially for items where safety is important, such as on-vehicle loads.

The present invention has been made in view of the above circumstances, and its purpose is to provide a data transmission system that can more reliably check the correctness of data.

In order to achieve such an object, the present invention provides a data transmission method in which frames consisting of a plurality of data throwers are cyclically transmitted in series; A check bit is provided, and the logical value of the check bit is sequentially inverted and transmitted for each frame, and the received data is determined based on the exclusive OR of the corresponding check bit and data bit in the received successive frames. It is characterized by checking the correctness of.

Hereinafter, embodiments of the present invention will be described in detail using the drawings from FIG. 4 onwards.

FIG. 4 is a diagram showing the structure of a time division multiplexed signal S1 transmitted in an embodiment of the data transmission system according to the present invention. Note that the electrical configuration for transmitting and receiving the signal S1 is exactly the same as that shown in FIG.

As shown in FIG. 4, the time division multiplex signal S1 used in this data transmission system has substantially the same configuration as the time division multiplex signal S used in the conventional data transmission system shown in FIG.

However, in this embodiment, instead of the parity bit PB added to the signal S for error detection, a check bit CB of one bit is provided for each slot.

Then, the contents of the check bit CB are as follows: In the N-1th frame, "IQ
11. In the Nth frame, '1'' in each slot, N+1th
In the frame, the logical value of the check bit CB is sequentially inverted and outputted for each frame, such as "0" in each slot.

FIG. 5 is a flowchart showing the structure of a processing program for setting the logical value of the check bit CB, among the system programs executed in the micro combi coater 6 in the transmitting station 2.

In the same figure, in step (1), a predetermined frame counter FC counts the number of frames in the signal S1.
Determine whether the content of is an even number. If the determination result is YES, the process advances to step (2) and the throwers l-SL O to SL2 included in the frame are
If the answer is No, the process proceeds to step (3) and sets each check bit CB of the slot in the frame to "1".

Next, by processing steps <4) and (5), each slot SLO to S L,
2 are sequentially output, and when the output of one frame is completed, the process proceeds to step (6) and the frame counter FC is incremented.

On the other hand, on the receiving station 3 side, when the time division multiplexed signal S1 configured and output as described above is received, the correctness of the received data is checked based on the check bit CB.

FIG. 6 is a flowchart showing the contents of the received data correctness checking process in the system program executed by the microcomputer 13 on the receiving station 3 side.

The above correctness checking operation will be explained below according to this flowchart. For ease of understanding, here, in the receiving station 3, slot 5LON in the Nth frame of the time division multiplexed signal shown in FIG.
is assumed to have been received.

In the flowchart 1 of FIG. 6, in step (7), the received data is read in slot units, and the corresponding one of the latest slot storage registers NRO, NR1, and NR2 provided for each channel in each frame is read. Processing is performed to store the information in the register of the corresponding channel.

That is, the contents of slot 5LON shown in FIG. 4 are stored in the register NRO.

On the other hand, the previous stage slot storage registers (N-1) RO, (N
-1>'R1, (If-1)R2 stores each slot in the N-1ffi-th frame that has been received previously, and in step (8), the above step (
Exclusive OR of the slot read in step 7) and the slot stored in the register of the same channel among the preceding slot storage registers is performed for each pin 1 (however,
Start bits 1 to ST (excluding stop bit SP) are calculated.

That is, slot 5LON and slot 5 shown in FIG.
The exclusive OR of corresponding bits is calculated between LON-1.

Next, in step (9), the received data bits D in the throwers 1 to 1 are processed. - It is determined whether there is an error in D5.

That is, if there is no error in the received data, the logical values of the check bits in slots 5LON and 5LON-1 in successive frames must be different.
From this, if only the exclusive OR of the check bits obtained in step (8) above is '1°', then
It is determined that the received data is correct data, and in step (10), an original control signal is formed from the received data and output.

On the other hand, due to the influence of noise etc., the check bit CB
If the logical value of is reversed, the above slot 5
Since the exclusive OR of the check bits of LON and 5LON-1 is OIf, it is determined that an error has occurred in the data bits DO to D6 in the received data, and the received data is removed. Ru.

In such a data correctness check method, for example, if the data transmission rate is 10 Ksit/sec, the time required to transmit one frame is 3 x 10
-' seconds, and the control signal from the input circuit 1 in FIG.
If it is output for 1 second (switch output time when a human operates the switch), the same data will be continuously transmitted for 30 frames or more.

Therefore, as described above, it is possible to check whether the data is correct using two consecutive frames.

Furthermore, if the data transmission method using this check method is applied to the steering switch system shown in FIG. Since the transit time of the spoke 21a is long with respect to the output cycle of the data, even if the same error occurs in a plurality of consecutive frames, this data error can be detected.

FIG. 7 is a diagram showing the structure of the time division multiplexed signal 82 transmitted in the second embodiment of the present invention.

It is assumed that the electrical configuration for transmitting and receiving this signal $2 is exactly the same as that shown in FIG.

As shown in FIG. 7, the time division multiplex signal S2 used in this data transmission system has a start bit ST and a stop bit S'P, similar to the time division multiplex signal 81 of the first embodiment shown in FIG. 7 data bits D o
``□Ds'' and a 1-bit check bit CB are sandwiched in between.

However, in this embodiment, in each slot of the N-1th frame and each slot of the Nth frame, the data bit D o
``-D6'' and the logical values of check bit CB are all inverted.

FIG. 8 is a flowchart showing the contents of the process of inverting the logical value for each frame, which is executed by the microcomputer 6 in the transmitting station 2.

In the same figure, in step (11), each thrower 1 to 8
"' to each check bit CB in 10~SL2
Processing to set the value to 1' is performed.

At this time, the data pitch in each slot hD o ”□
Control data is set in D6 by positive logic.

In step (12), the same process as step (1) in the flowchart shown in FIG. 5 is performed to determine whether or not the content of the frame counter FC is an even number. Then, the process proceeds to step (13), where a process of inverting the logical value of the data in each slot is performed.

As a result, the control data in each slot becomes negative logic data, and the logic value of the check bit CB becomes 0''.

Moreover, if the above-mentioned determination result is NO, the logical value inversion process of the data is not performed.

In steps (11) and (15), processes similar to those in steps ('l) and (5) in FIG. 5 are performed, and 1
One frame's worth of data is sequentially output. When the output of one frame is completed, the frame counter FC is incremented in step (16).

Next, on the receiving station 3 side, a process similar to that shown in the flowchart of FIG. 6 is executed to check whether the received data is correct or incorrect.

However, in step (9) in FIG. 6, it is determined whether only the exclusive OR of the check bits CB is 1'', but in this embodiment, the N-1st frame and It is determined whether the exclusive ORs of the data bits Do to DS in the Nth frame are all "1".

In other words, if the received data is correct data, the logical values of the data bits and check bits of the Nth frame and N-1th frame should all be inverted, so the exclusive OR of each bit is should all be 1″,
If there are errors in the received data due to noise, etc.,
If all the above exclusive ORs are not 1°', ii O++
It is possible to check that there is an error in the received data.

At this time, even if there is no error in the check bits and an error occurs only in the data bits, this error can be detected.

In other words, in the steering switch system shown in FIG. 3, if the same error occurs in bits other than the check bit over a plurality of consecutive frames, the data bits Do~ which should be reversed in each frame. Since bits with the same logical value appear in D6 and the exclusive OR of these bits becomes "'O", it can be determined that the received data is erroneous.

FIG. 9 is a diagram showing the structure of the time division multiplexed signal S3 propagated in the third embodiment of the present invention.

Note that the electrical configuration for transmitting and receiving this signal S3 is similar to that shown in FIG.

As shown in FIG. 9, the time division multiplex signal S3 used in this data transmission system has one check bit CB equal to l:J in the time division multiplex signal S1 of the first embodiment shown in FIG. The data bits are increased to 2 bits and 1~, and instead the data bits are reduced by 1 bit to 6 bits.Do''B5.

The two check bits CB+ and CB2 in each thrower 1 to SLO to SL2 have different logical values, and in the N-1th frame, the check bits 1 to B+ are 40'' and checked.゛1° to bit CB2
°, in the Nth frame, check bit CB+ is 1'', check bit CB2 is 'O', in the N+1 frame, check bit CB+ is '0'', check bit CB2 is
The logical values of check bits CB+ and CB2 are sequentially inverted for each frame, such that the check bits are "1".

Therefore, the microcomputer 6 in the sending station 2 checks the check bit CB+.

The process of setting the logical value of CB2 is performed in substantially the same way as the process shown in the flowchart of FIG.

However, instead of the process in step (2) in the figure, a process of setting "l'Q11" in check bit CB+ and 1 in check bit CB2 is performed, and instead of process in step (3), A process is performed in which check bit CB+ is set to "i 111." Check bit CB2 is set to "0°."

Further, the micro combination check process on the side of the receiving station 3 is also performed in substantially the same manner as the Iζ process shown in the flowchart of FIG.

However, instead of the process in step (9) in the figure, the check bit CB in the Nth frame and the N-1th frame
A process of determining whether the exclusive OR of + and CB2 is both IILI+ is executed, and if both are "1'', it is determined that the received data is correct, and step (10)
If both 11011 or either one becomes ``O'', it is determined that there is an error in the received data, and the received data is rejected.

This further improves the accuracy of detecting errors in received data.

In other words, errors that occur in received data due to noise superimposition, etc., occur only in one bit with a frequency of <k'<
, often occur over two or more consecutive bits, so for example, in the first embodiment, data bit D4 . Suppose that "1" pulse noise is superimposed over 4 bits of D5D6 and check bit CB, and if this frame happens to be in an odd-numbered frame and 1" is set in the check bit. In this case, the error in this received data will not be detected.

How to use this example: 1. When noise similar to the above is superimposed, that is, data picks 1 to c4. , cffi and
l across 4 bits of check bits CB+ and CB2.
Even if the noise of the ll II pulse is superimposed, one of the exclusive ORs of the check bits CBI and C'82 becomes ii O++, and it is possible to detect that there is an error in the received data.

As shown in FIG. 10, as in the first and third embodiments, each slot has two check bits CBI and CB.
2, and check bits CB1.2 of each slot are provided. C
B2 is configured to set mutually different logical values,
In this case, the configuration may be such that the logical value is output without being inverted for each frame, and the receiving station determines whether the logical values of check bits CB+ and CB2 in one slot are different from each other. , it is possible to check the correctness of received data.

As a result, as in the third embodiment, it is possible to check the correctness when an error occurs in a plurality of consecutive bits. Furthermore, in this case, it is not necessary to calculate the exclusive OR of two consecutive frames, but rather the two check bits CB+ in one slot.

It is possible to check whether the received data is correct or not by simply determining whether the logical values of CB and 2 are different.

'As described above in detail, in the data transmission system of the present invention, the accuracy of received data can be checked more reliably than in the conventional parity check system.

Therefore, especially when used in applications where safety is important, such as controlling on-vehicle loads in vehicles, it is possible to significantly reduce the probability that on-vehicle loads will malfunction due to failure to detect errors in receiving data. It has advantages such as:

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the electrical configuration of an example of a data transmission system, Figure 2 is a diagram showing the configuration of signals transmitted in a conventional data transmission system, and Figure 3 is a diagram showing the configuration of a vehicle steering switch system. FIG. 4 is a sectional view showing the structure of the signal transmitted in the first embodiment of the data transmission system according to the present invention, and FIG. 5 shows the process of setting the logical value of the check bit in the signal. Flowchart, Figure M6 is a flowchart showing the process of checking the correctness of received data, Figure 7 is a diagram showing the structure of the signal transmitted in the second embodiment of the present invention, and Figure 8 is the process of inverting the logical value of the same signal. FIG. 9 is a diagram showing the structure of the signal transmitted in the third embodiment of the present invention, and FIG. 10 is a diagram showing the structure of the signal in the second embodiment. 2・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・Transmission station 3・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・Receiving station F・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・Frame 810~SL2・・・・・・
・・・・・・Slot D o ”-D 6・・・・・・
・・・・・・・・・・・・Data bit CB, CB+
', CB2...Check pick 1 ~ Patent applicant Nissan Motor Co., Ltd. Figure 5 Figure 6 Figure 7 (14) (16)

Claims (1)

[Claims] (1) In a data transmission method in which a frame consisting of a plurality of data slots is cyclically transmitted in series; each data slot is provided with at least one check bit in addition to the data bit, and the logical value of the check bit is set. The data bits are sequentially inverted and transmitted frame by frame, and based on the exclusive OR of the corresponding check bits and data bits in the received successive frames,
A data transmission method characterized by checking whether received data is correct.