JPH04267631A - Parity bit addition system - Google Patents

Abstract

PURPOSE:To detect it as a fault at a receiver side even when a transmission data is fixed to 'all 1s' or 'all 0s' due to occurrence of the fault with respect to the system adding a parity bit to the transmission data. CONSTITUTION:The parity rule of a parity generating means 1 is selected and set by an even/odd setting means 2 to generate a parity bit according to a prescribed parity rule from a transmission data by the parity generating means 1. A parity bit generated according to the prescribed parity rune is added to the transmission data and the result is sent. The even/odd setting means 2 is provided with a setting inversion means 3 to invert alternately the parity rule into the even parity or the odd parity periodically.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a method for adding parity bits to transmission data, and in particular, the present invention relates to a method for adding parity bits to transmission data.
The present invention relates to a parity bit addition method that can be detected even when the parity bit is fixed to "l1" or "all0".

In recent years, with the advancement of microcomputers, it has become common to process, process, transmit, etc. all information using digital signals. Along with this, it is necessary to improve the reliability of the data itself, as well as to detect and respond to abnormalities at an early stage when they occur during data transmission.

[0003] Abnormality detection during data transmission is often performed by adding a parity bit. In this case, the parity bit addition method detects an abnormality even when the transmitted data is fixed to "all1" or "all0". It is desired that it be detectable as

0004

[Background Art] In order to check the normality of transmitted data in a parity bit addition method, a parity bit is added to each transmitted data unit before transmission, and the receiving side checks the normality of parity in the transmitted data to determine whether the received data is normal. This is done by checking. However, due to transmission equipment failures, transmission line failures, etc., the transmitted data
If it is fixed to "ll1" or "all0", this cannot be detected as an abnormality, and early detection of a failure is difficult.

FIG. 4 shows an example of a conventional parity bit addition method, illustrating the case of 8-bit parallel data transmission. circuit, 12 is a transmission data transmitter, 13
14 is a parity generation circuit that generates a parity bit, and 14 is an even-odd setting section that sets the parity rule to be an even number or an odd number.

The transmission data generated by the transmission data generation circuit 11 passes through the transmission data transmitting section 12 and is output as parallel data D0 to D7 for each frame. The parity generation circuit 13 generates a parity bit P for each 8-bit parallel transmission data and adds it to the data D0 to D7. Parallel data consisting of output data D0 to D7 and parity bit P is output as transmission data to various I/Os or opposing devices.

[0007] At this time, the even/odd setting section 14 sets the even parity or the odd parity according to the number of "1" or "0" in the parallel transmission data according to the even or odd setting of the parity rule from the outside. A parity bit P is generated so that

FIG. 5 shows another example of the conventional parity bit addition method, illustrating the case of 8-bit serial data transmission. In the figure, the same parts as in FIG. 4 are designated by the same numbers; 15 is a parallel/serial converter that converts parallel data to serial data; 16 is a parity inserter that inserts a parity bit into the converted serial data.

Transmission data consisting of parallel data generated by the transmission data generation circuit 11 is converted into serial data frame by frame in a parallel/serial conversion section 15 and input to a parity insertion section 16 . The parity generation circuit 13 is
A parity bit P is generated for each 8-bit parallel transmission data and added to the parity insertion section 16. The parity insertion section 16 inserts a parity bit P into the output data of the parallel/serial conversion section 15 to generate output data Data consisting of serial data, and together with the clock signal Clk,
Output as transmission data to various I/Os or opposing devices.

[0010] At this time, the even/odd setting section 14 sets the parity to even parity or odd parity according to the number of "1" or "0" in the serially transmitted data according to the even or odd setting from the outside. Then, a parity bit P is generated.

[0011]

[Problem to be Solved by the Invention] In the parity bit addition method for parallel data shown in FIG. 4 or the parity bit addition method for serial data shown in FIG. 5, for example, the parity rule is set to even parity. In this case, when the transmission data is "01010101", the parity bit is set to "0" and is transmitted to various I/O or opposing devices. The receiving side expects the value of the parity bit to be “0” based on the number of “1” or “0” in the transmitted data, and the added parity bit is “0”.
”, it is determined that there is no abnormality in the transmitted data. On the other hand, in the case of “1”, it is determined that there is an abnormality in the transmitted data, and recovery processing such as stopping data transmission or retransmission is executed.

However, a failure or the like occurs after the transmission data transmitter 12, and the transmission data becomes "11111111".
or "00000000", if it becomes "all1" or "all0" and continues, the receiving side detects even parity, so it is judged that the parity detection result is normal, and it is abnormal. A problem arises in that the occurrence cannot be detected.

The same applies to the method of adding parity bits to serial data shown in FIG. If the number is even and the added parity bit is "0", it is determined that the transmitted data is normal, so if a failure occurs after the parallel/serial converter 15 and the transmitted data is “11111111
” or “00000000”, “all1”
Or if it becomes “all0” and continues,
Since the receiving side performs even parity detection, a problem arises in that the parity detection result is determined to be normal and the occurrence of an abnormality cannot be detected.

[0014] The present invention is an attempt to solve the problems of the prior art, and is aimed at solving the problem of the prior art. In the parity bit addition method for parallel data or serial data, transmission data becomes "all1" or "all" due to the occurrence of a failure or the like. a
The object of the present invention is to provide a parity bit addition method that can detect this as an abnormality on the receiving side even if the parity bit is fixed to "ll0" and continues.

[0015]

[Means for Solving the Problems] The present invention includes parity generation means for generating parity bits from transmission data according to a predetermined parity rule, and even-odd setting means for switching and setting the parity rule in the parity generation means,
A parity bit addition method for adding generated parity bits to transmission data and transmitting the data is characterized in that the even/odd setting means is provided with setting inversion means for periodically inverting the parity rule alternately between even parity and odd parity. That is.

[0016]

[Operation] FIG. 1 shows the basic structure of the present invention. In the parity bit addition method, parity generation means 1 generates parity bits from transmission data according to a predetermined parity rule, and even/odd setting means 2
By switching and setting the parity rule in the parity generating means 1, a parity bit generated according to a given parity rule is added to the transmission data and transmitted. In such a parity bit addition system, the even-odd setting means 2 is provided with a setting inversion means 3 to periodically and alternately invert the parity rule to even parity and odd parity.

Therefore, according to the present invention, the parity rule is periodically and alternately switched between even parity and odd parity, and parity bits are added to the transmission data before being transmitted. Data abnormalities due to transmission line related failures, especially “all1”
Alternatively, even if "all0" occurs, it is possible to detect this in units of transmission data.

[0018]

[Embodiment] FIG. 2 shows the configuration of an embodiment of the present invention, in which the same parts as in FIG. 4 are designated by the same numbers, and 21, 22, and 23 are examples of different parity rule setting units This is what is shown. Parity rule setting units 21, 22
, 23, 31 is a setting inversion unit that switches between even parity and odd parity, 32 is a transmission data counting unit that counts the number of transmitted data, and 33 is a P that generates a PN pattern.
This is an N pattern generation section.

In the case of the embodiment including the parity rule setting unit 21, the setting inversion unit 31 changes the parity rule in the even-odd setting unit 14 for each frame of transmission data according to the amount of data to be transmitted in the transmission data generation circuit 11. to have even parity and odd parity. The parity generation circuit 13 alternately inserts even parity bits and odd parity bits as parity bits P for each frame of transmission data.

[0020] On the receiving side (various I/Os or opposing devices), the normality of the transmitted data is checked by switching between an even parity check and an odd parity check in synchronization with the reversal of the parity rule on the transmitting side. can do. If the transmission data or the transmission data and the parity bit are fixed to "all1" or "all0" due to a failure of the transmission data transmitter 12 or later, for example, when even parity is set, the receiving side will not accept this as described above. Even if it cannot be detected as an abnormality, when odd parity is set, the receiving side will detect “
Since the number of 1's or 0's does not match the added parity bit, it can be detected as an abnormality.The same applies to the opposite case.

In the case of the embodiment including the parity rule setting section 22, the transmission data counting section 32 is connected to the transmission data generating circuit 11.
By counting the number of data generated by
Invert the parity rule in 1. Thereby, the even-odd setting unit 14 inverts the generation of even parity and odd parity in the parity generation circuit 13 for each block of transmission data. Therefore, even parity bits and odd parity bits are alternately inserted as parity bits P under the control of the even/odd setting section 14.

[0022] If the transmission data becomes "all1" or "all0" and continues to do so based on a failure or the like after the transmission data transmitter 12, for example when even parity is set, the receiving side detects this as an abnormality. Even if this is not possible, it can be detected as an abnormality because the number of "1"s and "0"s in the transmission data and the added parity bits do not match on the receiving side when odd parity is set.

In the case of the embodiment including the parity rule setting section 23, the transmission data counting section 32 is connected to the transmission data generating circuit 11.
Count the number of data generated. The PN pattern generation section 33 generates a PN pattern (pseudorandom pattern) with a constant period according to the result of counting the number of data in the transmission data counting section 32, and the setting inversion section 31 generates a parity rule according to this PN pattern. Invert. The even-odd setting section 14 inverts the insertion of even parity and odd parity in the parity generation circuit 13 according to the setting of the setting inversion section 31. As a result, as the parity bit P,
Even parity bits and odd parity bits are inserted alternately according to "1" and "0" of the PN pattern.

[0024] If the transmission data becomes "all1" or "all0" and continues to do so based on a failure of the transmission data transmitter 12 or later, for example when even parity is set, the receiving side detects this as an abnormality. Even if this is not possible, it can be detected as an abnormality because the number of "1"s and "0"s in the transmission data and the added parity bits do not match on the receiving side when odd parity is set.

FIG. 3 shows the structure of another embodiment of the present invention, in which the same parts as in FIGS. 2 and 5 are designated by the same numbers. Also, parity rule setting units 21, 2
The configurations and operations of the setting inversion section 31, transmission data counting section 32, and PN pattern generation section 33 in 2 and 23 are also the same.

In the case of the embodiment including the parity rule setting section 21, the setting inversion section 31 changes the even parity in the even-odd setting section 14 for each frame of transmission data, depending on the amount of data to be transmitted in the transmission data generation circuit 11. and reverse the odd parity setting. As a result, the parity generation circuit 13 alternately generates an even parity bit and an odd parity bit as the parity bit P for each frame of transmission data, and the parity insertion unit 16 inserts this parity bit P into the transmission data. .

Therefore, based on a failure or the like after the parallel/serial converter 15, the transmission data output from the parity inserter 16 may be "11111111" or "0000000".
0", "all1" or "all0" continues, for example, when even parity is set, even if the receiving side cannot detect this as an abnormality as described above, odd parity is set. Sometimes, on the receiving side, the number of 1's and 0's in the transmitted data does not match the added parity bits, so it can be detected as an abnormality.

In the case of the embodiment including the parity rule setting section 22, the transmission data counting section 32 is connected to the transmission data generating circuit 11.
By counting the number of data generated by
Invert the parity rule in 1. As a result, the even-odd setting section 14 inverts the generation of even parity and odd parity in the parity generation circuit 13 for each block of transmission data, and the parity insertion section 16 inserts this parity bit P into the transmission data.

[0029] If the transmitted data becomes "all1" or "all0" and continues to do so based on a failure etc. after the parallel/serial converter 15, for example when even parity is set, the receiving side will detect this as an abnormality. Even if this is not possible, it can be detected as an abnormality because the number of "1"s and "0"s in the transmission data and the added parity bits do not match on the receiving side when odd parity is set.

In the case of the embodiment including the parity rule setting section 23, the transmission data counting section 32 is connected to the transmission data generating circuit 11.
Count the number of data generated. The PN pattern generation section 33 generates a PN pattern (pseudo-random pattern) with a constant period according to the result of counting the number of data in the transmission data counting section 32, and the setting inversion section 31 generates an even-odd setting section according to this PN pattern. Invert the parity rule in 14. The even-odd setting section 14 includes a parity generation circuit 13
The parity inserting unit 16 inverts the generation of even parity and odd parity in , and inserts this parity bit P into the transmission data.

[0031] If the transmitted data becomes "all1" or "all0" and continues to do so due to a failure etc. after the parallel/serial converter 15, for example when even parity is set, the receiving side will detect this as an abnormality. Even if this is not possible, it can be detected as an abnormality because the number of "1"s and "0"s in the transmission data and the added parity bits do not match on the receiving side when odd parity is set.

[0032]

As explained above, in the parity bit addition method that adds parity bits to detect abnormalities and errors in transmission data, data abnormalities due to failures in transmission line related parts, especially "All1" or "All0", can be detected. Even if an error occurs, it can be detected in a transmission unit of a predetermined amount of transmitted data, and therefore recovery processing can be performed immediately after the occurrence of an error, which improves the reliability and reliability of the device. It becomes possible to ensure the reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 4 is a diagram showing an example of a conventional parity bit addition method.

FIG. 5 is a diagram showing another example of a conventional parity bit addition method.

[Explanation of symbols]

1 Parity generation means 2 Even-odd setting means 3 Setting reversal means 4 Transmission data counting means 5 PN pattern generation means

Claims (4)

[Claims] Claim 1: Parity generation means (1) for generating parity bits from transmission data according to a predetermined parity rule.
and an even/odd setting means (2) for switching and setting the parity rule in the parity generating means (1), and in which the generated parity bit is added to the transmission data and transmitted. A parity bit addition method characterized in that the even/odd setting means (2) is provided with a setting reversing means (3) for periodically and alternately reversing the parity rule between even parity and odd parity. 2. The parity bit addition method according to claim 1, wherein the setting inversion means (3) inverts the parity rule for each frame of transmission data. 3. The setting inversion means (3) includes transmission data counting means (4) for counting the amount of transmission data, and inverts the parity rule every time one block of transmission data packets or the like is counted. The parity bit addition method according to claim 1. 4. The setting inversion means (3) includes a transmission data counting means (4) for counting the amount of transmitted data, and a PN that generates a PN pattern according to the result of counting the amount of transmitted data.
2. The parity bit addition method according to claim 1, further comprising a pattern generating means (5) for inverting a parity rule according to a PN pattern with respect to an amount of transmitted data.