JP2864611B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory having a configuration for processing a plurality of bits of data in parallel.

[Conventional technology]

Conventionally, this type of semiconductor memory has a mainstream of up to 8 bits, and a small number of multi-bit systems of 9 bits or more are often produced at present.

Factors that determine the number of bits in a semiconductor memory include bit matching with a microcomputer. At present, the mainstream of microcomputers has already shifted to 16 bits. Therefore, semiconductor memory will soon be 16 bits, or
It is presumed that it will shift to a 32-bit multi-bit system.

For a multi-bit semiconductor memory of 9 bits or more, it is advisable to manufacture data input / output terminals according to the number of bits of the microcomputer. For example, a 16-bit microcomputer is used for data input and output. There are 16 terminals each.

[Problems to be solved by the invention]

The conventional semiconductor memory described above is currently used because the number of data input / output terminals is determined according to the number of bits of the microcomputer, and the mainstream of microcomputers has shifted from 8 bits to 16 bits. A test device for an 8-bit semiconductor memory cannot be used, and a new test device for a 16-bit semiconductor memory must be newly installed, which causes a problem that manufacturing costs increase.

An object of the present invention is to provide a semiconductor memory which can be tested using an existing 8-bit test apparatus even if it is 16 bits or 32 bits, and which can suppress an increase in manufacturing cost. .

[Means for solving the problem]

The semiconductor memory according to the present invention has an output terminal having the same number of bits as the number of bits of the data for correspondingly outputting a plurality of bits of the parallel processed data, and exclusive use of a predetermined plurality of bits of the plurality of bits of data. An exclusive-OR circuit for performing an exclusive-OR operation, a transfer circuit for transmitting output data of the exclusive-OR circuit to a predetermined output terminal among the plurality of output terminals according to a test signal, and the test signal And a plurality of output circuits that are activated and controlled by the output control signal and transmit the plurality of bits of data to the corresponding output terminals.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment performs an exclusive OR operation on the n-bit data with the same number of output terminals TO1 to TOn as the number of bits of the n-bit data to output correspondingly processed n-bit data. An exclusive OR circuit 1, an inverter and a transfer gate are provided, and output data of the exclusive OR circuit 1 is output to the output terminal TO according to a test signal TST.
A transfer circuit 2 for transmitting to a predetermined output terminal TO1 of 1 to TOn, and an output control signal DOE according to a test signal TST.
, And data amplifiers 51 to 5n and output buffers 61 to 6n, respectively, corresponding to the output terminals (TO1 to TO1 to TOn) is provided with a plurality of output circuits 41 to 4n.

 Next, the operation of this embodiment will be described.

First, n-bit data DI1 to DIn processed in parallel are:
The processing is performed by the exclusive OR circuit 1.

Next, when the signal TST is at a low level, the transfer circuit 2 is turned off, the output data of the exclusive OR circuit 1 is not transmitted to the output terminal TO1, and the data output control circuit 3 outputs the output control signal DOE. High level output circuit 41 ~ 4
Activate n. Therefore, a normal operation state is set, and the n-bit data DI1 to DIn processed in parallel are output to the output circuits 41 to
The signal is transmitted to output terminals TO1 to TOn via 4n.

Next, when the test signal TST is at a high level, the transfer circuit 2 is turned on and transmits the output data of the exclusive OR circuit 1 to the output terminal TO1. At this time, the output control signal DOE output from the data output control circuit 3 becomes low level, and the output circuits 41 to 4n are deactivated, so that transmission of the data DI1 to DIn to the output terminals TO1 to TOn is cut off. You.

Therefore, for example, by writing each bit of data at the same logical level in advance and then reading it out and passing this circuit to check the level of the output terminal TO1, it is possible to check the quality of the writing and reading operations of this semiconductor memory. be able to.

 FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the n-bit data DI1
The ~DIn, DI1~DIk, divided into two groups of DI (k + 1) ~DIn, the provided these are for the two groups performs exclusive processing exclusive OR circuit 1 _A, 1 _B, these Exclusive OR circuits 1 _A , 1 _B output data TO
It is designed to be transmitted to each of TO1 and TO2.

In this embodiment, there is an advantage that when there is a malfunction, the range of the portion where the malfunction has occurred can be limited to a narrow range. This advantage increases as the number of groups to be divided increases.

〔The invention's effect〕

As described above, according to the present invention, at least one exclusive OR circuit for performing exclusive OR processing of a predetermined plurality of bits of data of a plurality of bits processed in parallel is provided, and this output is transmitted to a predetermined output terminal. By having a configuration that
The quality of the data of a plurality of bits subjected to exclusive OR processing can be determined based on the level of the output terminal, so that the quality of the data processed in parallel can be checked with a small number of output terminals. The 8-bit test device can be used for a 16-bit, 32-bit, or other multi-bit semiconductor memory, which has the effect of suppressing an increase in manufacturing costs.

[Brief description of the drawings]

FIG. 1 and FIG. 2 are circuit diagrams showing first and second embodiments of the present invention, respectively. 1, 1 _A , 1 _B ... exclusive OR circuit, 2, 2 _A ... transfer circuit, 3 ... data output control circuit, 41-4n ... output circuit, 51-5n ... data amplifier, 61- 6n Output buffer, TO1 to TOn Output terminals.

Claims (1)

(57) [Claims] An output terminal having the same number of bits as a plurality of bits of data for outputting a plurality of bits of data processed in parallel, and an exclusive logic of a predetermined plurality of bits of the plurality of bits of data. An exclusive-OR circuit for performing a sum process, a transfer circuit for transmitting output data of the exclusive-OR circuit to a predetermined output terminal among the plurality of output terminals in response to a test signal, A semiconductor device comprising: a data output control circuit that outputs an output control signal to the output terminal; and a plurality of output circuits that are activated and controlled by the output control signal and transmit the plurality of bits of data to the corresponding output terminals. memory.