GB2027958A - Microprogrammed control unit - Google Patents

Abstract

A microprogrammed control unit includes a memory 52 simultaneously feeding a microinstruction to an execution buffer (not shown) and to error detection and correction (EDAC) circuitry 58. If a correctable error is detected, the correct microinstruction is fed to the execution buffer in place of the next microinstruction. If an uncorrectable error is detected the operation in progress is aborted. Two three state busses are employed, the first of which is used to transmit memory data to the second bus and to the execution buffer. The second data bus transmits input data to the memory microinstructions from the first bus to the EDAC unit, and also transmits corrected data from the EDAC unit to the first bus. <IMAGE>

Description

SPECIFICATION Microprogrammed control unit This invention relates generally to data processing systems, and more particularly, to a method and apparatus for transmitting an accurate data group from an execution unit control store to the instruction buffer of a central processing unit by means of two three-state data busses.

In data processing systems wherein various subsystems must communicate with each other, errors, for example those caused by a presence of noise, sometimes result in the receipt of data which is not the same as that which was transmitted. To overcome this, error detection and correction (EDAC) techniques have been developed, as is well known.

It is well known to employ error detection and correction (EDAC) apparatus to check and correct data extracted from a main memory system and bound for other subsystems in the data processing systems, for example, the central processing unit.

However, in the past, such apparatus was not employed to verify and correct micro-instructions from the instruction unit control store to an execution buffer; the process would simply be aborted and re-executed since it was generally felt that the error was the result of a transient transmission problem.

The object of the present invention is to provide an EDAC system in a microprogrammed control unit without incurring too heavy a speed penalty.

Accordingly the present invention provides a data processing system, a microprogrammed control unit in which microinstructions are read out from a microprogram memory during sequential clock periods to an execution buffer to control the operation of the system, and to an error detection and correction unit which, on detecting an error in a microinstruction, corrects the error and causes the corrected microinstruction to be placed in the execution buffer instead of the next microinstruction from the memory, and aborts the operation in progress if the error is uncorrectable.Preferably the unit includes first and second data busses, the first data bus receiving data from the memory and feeding the second data bus and the execution buffer, and the second data bus receiving data from the error detection and correction unit and feeding the first data bus and the error detection and correction unit.

A microprogrammed control unit embodying the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a functional block diagram of part of an execution unit; Figure 2 is a functional diagram of a portion of a central processing unit including the execution unit; Figure 3 is a block diagram of a prior art arrangement employing in-cycle EDAC; and Figure 4 is a block diagram of the present arrangement employing out-of-cycle EDAC.

Figure 2 is a block diagram of those hardware elements of a CPU (Central processing unit) which are relevant for present purposes. Instructions are received over an instruction buffer channel ZIB 26 from a main memory controller (not shown) and are transmitted through ZIB switch 28 to RBIR 30 for storage therein. The control unit control store word which is stored in control unit control store CCS 32 comprises 32 bits. A 13 bit field consisting of bit positions 0 to 12 is the address of the starting location for the microprogram specified by the operation code of the instruction word in instruction register RBIR 39, i.e. the address of the initial microinstruction of the microprogram.

When the operation code from an instruction is applied to CCS 32 from RBIR 30, the control unit control word stored at the address corresponding to the OP code is read and the contents of bit positions 0 to 12 are applied to the execution unit control store (ECS) 34 through switch CCS-ADR 36.

The receipt of the address of the microinstruction by ECS 34 causes the microinstruction stored at that address to be transferred to the execution buffer 38 where selected fields of the microinstruction are decoded by decoder 40 to provide the necessary control signals or information to the various subsystems, or components, of the CPU.

To avoid unnecessary detail, the clock and the conductors that apply the clock signals to the various components of the CPU are not shown in Figure 2.

When the first microinstruction has been loaded into the execution buffer 38, and during the next clock period, the microinstruction will be decoded in decoder 40 to provide the necessary information and control signals to cause a scartchpad memory (not shown) to be addressed and a portion of its contents to be transferred, stored and operated upon.

The next or second microinstruction, which is produced as a result of the address of the first microinstruction which is stored in microinstruction register UIC 42 being incremented by one by adder 44 and applied through switch UlC+1,46wi1I cause the second microinstruction to be transferred to execution buffer 38.

Figure 3 illustrates EDAC function orientation in a prior art data processing system. An output from memory 61 is applied to data switch 65 and to EDAC circuitry 63. Data switch 65 then selects whether data from memory 61 or corrected data from EDAC 63 will be forwarded to the CPU.

In the present arrangement, as shown in Figure 4, data from memory 67 is applied to the CPU and to EDAC 69 simultaneously. If an error is detected and is not correctable, the operation in progress is aborted. If no error is detected, utilization of the data proceeds uninterrupted. This arrangement reduces control store access time by about 40% over that of M-cycle EDAC (Figure 3). This results in a 60% increase in system clock rate. Out-of-cycle EDAC permits simultaneous activities; i.e. the next memory request may be processed while the previous request is undergoing EDAC scrutiny. Additional speed enhancement is accomplished by a 3-state bus implementation described below.

Figure 1 is a functional block diagram of a portion of the present execution control store (34 in Figure 2). Two separate but inter-related three state data busses are used. The first, referred to as the memory data bus, is connected between the output of three state device 50, the input of three state device 54, the output of memory 52 and the input of execution buffer 38 (Figure 2). The second bus, referred to as the backpanel bus, is connected between the output of three state devices 56,62 and 54, and the inputs of data register 60, AND function 66 and three state device 50. It should be understood that each of the busses is composed of a plurality of lines for handling the parallel transfer of a plurality of data bits.

The error detection and correction (EDAC) em ployed is out of cycle detection and correction. To accomplish this, data from memory 52 to execution buffer 38 is assumed correct for any current cycle and is strobed into the execution buffer by the system clock. During the following cycle, this same data is checked for errors in EDAC circuitry 58. If a correctable error is detected, a signal is sent to another portion of the CPU, preventing the CPU from acting on the erroneous microinstruction, and cor rected data is placed on the bus to be restrobed into the execution buffer on the following clock. Any uncorrectable errors result in a system abort.

Two critical timing paths are involved in this scheme. It is first necessary to get data from memory 52 to the execution buffer before the system clcok occurs. The second involves making an error signal and the corrected data available to the execution buffer before the following clock.

The output of memory 52 is coupled to execution buffer 38 and to the input of a three state buffer 54 for transmission of the data to EDAC circuitry 58 via data register 60. During this time, three state buffer 54 is enabled by a read signal which originates in another portion of the CPU. Simultaneously, three state buffers 50, 56 and 62 are disabled and present a high impedance to their respective busses. That is, three state buffer 62 is disabled by the absence of a write signal on its input. Likewise, the absence of a write signal at a second input of AND function 66 prevents data bound for the EDAC circuitry from re-entering memory 52 via AND function 66. Similar ly, three state buffers 50 and 56 are disabled by the absence of a send correct data signal which origin ates in EDAC circuitry 58.Thus, data may be transmitted from three state buffer 54 to the EDAC circuitry without interference.

During a correction cycle, the same two bi directional busses transmit data from three state buffer 56 to the execution buffer via three state buffer 50. During this time, buffer 62 and AND function 66 are disabled by the absence of the write signal and three state buffer 54 and memory 52 are disabled by the absence of a read signal. Buffers 50 and 56 are enabled by a corrected data signal and transmit data from the EDAC circuitry 58 to the execution buffer. It should be noted that the memory data bus which connects buffers 50, 54 and memory 52 to the execution unit eliminates the need for a conventional data switch which would represent an extra stage of delay in the data path to the remainder of the CPU for either memory data or corrected data.

During write cycles, data from buffer 64 is trans mitted to memory 52 via buffer 62 and AND function 66. During this operation, three state buffers 50, 54 and 56 are disabled as described above.

During a write cycle, data to be written into the memory is applied to AND function 66. This data passes through the AND function 66, when the write signal is activated, to memory 52 where it is stored therein by write control 51.

During a read cycle, the write signal is disabled preventing data from passing through three state buffers 62 and AND fucntion 66. When memory 52 has a read control signal 53 and an address applied thereto, the memory outputs the data stored in that address. This data travels two paths. The first is to the remainder of the CPU as is shown at the extreme right of Figure 1. Simultaneously, the data from memory 52 is applied to the three.state buffer 54, which is also fed with a read enable signal which, when activated, allows data to pass through the buffer. When the read signal is disabled, the buffer appears as a set of high impedance nodes.

Assuming the read signal is enabled and the write signal disabled, data from memory 52 passes through three state buffer 54 and is applied to the inputs of data register 60 (Figure 6). The data in data register 60 is applied to the EDAC circuitry 58 as described above, where it is determined whether there is an error in the data and whether or not the error is correctable. Two signals are sent from the EDAC circuitry to another portion of the CPU. These signals are shown as an error signal and an error correctable signal which indicates that while there is an error, the error is correctable.

If the error is correctable, the same correct data signal is applied to three state buffer 56. The corrected data is likewise applied to three state buffer 56 and passes therethrough to the inputs of three state devices 50. During this period of time, the write signal is disabled thus preventing the data from passing through AND function 66 back to memory 52.

The same correct data signal, described previously, is applied to three state buffer 50 to enable passage of the data to the CPU. During this period of time, the read signal is disabled to prevent the corrected data from passing through three state buffer 54.

Thus, the above described arrangement permits three electrical functions to be performed on one bus, referred to as the backpanel bus. These functions are transmitting memory data to the EDAC circuitry, transmitting corrected data from the EDAC circuitry to the data output circuits and transmitting input data to the memory.

The memory data bus permits transmission of data to both the CPU and the EDAC circuitry. In addition, the memory data bus provides for transmission of corrected data from the EDAC circuitry to the CPU. Both busses minimize the need for any additional gates or switches and thus present the fastest possible data paths where critical timing is involved.

Claims (6)

1. In a data processing system, a microprogram med control unit in which microinstructions are read out from a microprogram memory during sequential clock periods to an execution buffer to control the operation of the system, and to an error detection and correction unit which, on detecting an error in a microinstruction, corrects the error and causes the corrected microinstruction to be placed in the execution buffer instead of the next microinstruction from the memory, and aborts the operation in progress if the error is uncorrectable.

2. A microprogrammed control unit according to Claim 1 including first and second data busses, the first data bus receiving data from the memory and feeding the second data bus and the execution buffer, and the second data bus receiving data from the error detection and correction unit and feeding the first data bus and the error detection and correction unit.

3. A microprogrammed control unit according to either previous claim including writing means for writing information in the memory.

4. A microprogrammed control unit according to Claims 2 and 3 wherein the writing means comprise an input data buffer feeding the second data bus and gating means coupling the second data bus to the memory.

5. A microprogrammed control unit according to any one of Claims 2 and 4 wherein the first data bus feds the second data bus, the second data bus feeds the first data bus, the second data bus feeds the error detection and correction unit, and the input data buffer (if present) feeds the second data bus through respective sets of tri-state gates which, when enabled, pass data applied to their input, and, when disabled, present high impedances at their outputs.

6. A microprogrammed control unit substantially as described herein with reference to Figures 1,2 and 4.