JPH0198033A - Data error detection circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method for detecting data errors in an information processing device, and includes a circuit for selecting one of two sets of data to check for data errors. The purpose is to provide a means that can also check whether or not the desired data has been selected correctly, by adding an even parity bit to one of the two sets of binary data. A means is provided for adding an odd parity bit to the other binary data, and a means is provided for switching between performing an even parity check and performing an odd parity check depending on which of the two sets of binary data is selected. It consists of:

[Industrial Field of Application] The present invention relates to a data error detection circuit in an information processing device, and in particular, the present invention relates to a data error detection circuit in an information processing device. The present invention relates to a configuration of a circuit that is configured to perform a parity check and is capable of identifying whether or not target data has been correctly selected based on a data error detection result.

[Prior Art] Binary data (hereinafter also simply referred to as data) handled by an information processing device may cause errors due to internal circuit failures, noise, and the like. In other words, binary data is “1”
Normally, the difference between the voltage of a signal that is “1” and the voltage that is “ON” on a logic circuit is minute, and the speed at which this signal is transferred is fast, so it is '0' may change to '1' or '0' may change due to external noise etc.
There is always a possibility that a ``1'' may be missing and become a ``0''.

Therefore, in an information processing device, the data sending side adds information (additional bits, etc.) to check whether the data is correct for each data of a certain length, and this allows the data receiving side to A method is used to check the validity of the data.

Parity check is one of the methods for checking such data. This is done by adding 1 bit (called a parity bit) to each certain size of data (for example, 1 byte) on the data sending side, so that the number of "1"s in the data and the added bits is always an even number. This is a method in which the data is sent out in such a manner that the data is correct, and when the data receiving side checks it, if the number of "1"s is an even number, the data is correct, and if it is an odd number, an error has occurred. This is called even parity.

When transmitting data, the number of "1"s in the data including parity bits is an odd number, and error detection similar to the above is performed is called odd parity.

[Problems to be Solved by the Invention] In a circuit that employs the parity check method as described above, consider a configuration in which one of two sets of data to which parity bits have been added is selected to perform a parity check. .

FIG. 2 is a diagram showing an example of such a conventional circuit,
51.52 are registers, 53.54 are parity bits,
55 is a multiplexer, 56 is a register, 57 is a parity bit, and 58 is a parity check circuit.

In the figure, the multiplexer 55 has a selection signal (SE
L) selects either register 51 or register 52 and stores its contents in register 56.

A parity bit 53 or 54 is added to the contents of the register 51 or 52, respectively, so that the number of "1"s in the information including the data and the additional bit is always an odd number (herein explained as odd parity). It is controlled as follows.

The parity check circuit 58 performs a check on the data selected by the multiplexer 55 and stored in the register 56.
It is checked whether the number of "1"s is an odd number, and if it is an odd number, the data is determined to be correct, and if it is an even number, an error is assumed to have occurred and appropriate processing is performed.

In the circuit described above, even if the selection signal (SEL) is incorrect or the multiplexer 55 malfunctions and the register that should have been selected is not selected and a different register is selected, the parity If the result of the parity check in the checking circuit 58 is correct, the data is treated as correct.

Therefore, when such a situation occurs, extremely serious problems such as erroneous processing results or runaway software may occur in subsequent processing.

In view of these conventional problems, the present invention provides a circuit configured to perform a parity check by selecting one of two sets of binary data to which parity bits have been added. It is an object of the present invention to provide a circuit that can detect whether or not target data has been correctly selected.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims. That is, the present invention provides 2
In a circuit configured to perform a parity check by selecting one of the sets of binary data to which parity bits have been added,
In addition to providing means for adding an even parity bit to one binary data and adding an odd parity bit to the other binary data, an even parity check is performed depending on which of the two sets of binary data is selected. This data error detection circuit is provided with means for switching between performing an odd parity check and an odd parity check.

[Operation] In the above means, an even parity bit is added to one of the two sets of data, and an odd parity bit is added to the other data, so the selection is made by performing a parity check. It is possible to easily know whether the selected data was selected correctly or incorrectly. At this time, if the result of the parity check is determined to be negative, there are two possibilities: an error in the data itself or an error in the selection, but in either case, the data cannot be used, it is possible to normalize the process by retrying or other processing, and to prevent erroneous results from being introduced into subsequent processing.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention, including 1.
2 is a register, 3 is an even parity bit, 4 is an odd parity bit, 5 is a multiplexer, 6 is a register, 7 is a parity bit, 8 is a parity check circuit, and 9 is a parity check control circuit.

In the figure, multiplexer 5 outputs a control signal (SEL)
According to the instruction, register 1 or register 2 is selected and stored in register 6.

The data stored in the register 6 is sent to the parity check circuit 8.
The parity is checked by , and if it is normal, it is output to the next stage.

Here, the data in register 1 has an even parity bit of 3.
is added, and odd parity bit 4 is added to the data in register 2. Then, the parity check circuit 8 checks the selected data as an even parity or an odd parity depending on whether the data selected by the instruction from the parity check control circuit 9 is the data of the register 1 or the data of the register 2. I am switching between what I do and what I do.

Therefore, not only when an error occurs in the data in register 1 or register 2, but also when data selection by multiplexer 5 is incorrect, the malfunction is detected by the check of parity check circuit 8.

This embodiment is also particularly useful when applied to cases in which the contents of register 1 and register 2 are always read out alternately, and in this case, the parity check control circuit is
This can be easily realized with one flip-flop 71 circuit driven in synchronization with a signal.

[Effects of the Invention] As explained above, according to the present invention, in a circuit configured to perform a parity check by selecting one of two sets of binary data to which parity bits have been added, By simply adding a small control circuit to determine whether to perform an even parity check or an odd parity check on the selected data, not only the data but also the control information for register selection can be corrected. Even if this occurs, it can be detected as an internal data parity error, and this has a great effect on increasing the reliability of information processing equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a diagram showing an example of a conventional circuit. 1.2...Register, 3...Even parity bit, 4...Odd parity bit, 5...
...Multiplexer, 6...Register,
7... Parity bit, 8... Parity check circuit, 9... Parity check control circuit representative

Claims (1)

[Claims] In a circuit configured to perform a parity check by selecting one of two sets of binary data to which parity bits have been added, A means is provided for adding an even parity bit to binary data and an odd parity bit to the other binary data, and an even parity check is performed depending on which of the two sets of binary data is selected. 1. A data error detection circuit comprising means for switching between performing a parity check and an odd parity check.