JPH0198033A - Detecting circuit for data error - Google Patents

Detecting circuit for data error

Info

Publication number
JPH0198033A
JPH0198033A JP62255674A JP25567487A JPH0198033A JP H0198033 A JPH0198033 A JP H0198033A JP 62255674 A JP62255674 A JP 62255674A JP 25567487 A JP25567487 A JP 25567487A JP H0198033 A JPH0198033 A JP H0198033A
Authority
JP
Japan
Prior art keywords
data
register
parity check
circuit
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62255674A
Other languages
Japanese (ja)
Inventor
Kiyotaka Fujimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62255674A priority Critical patent/JPH0198033A/en
Publication of JPH0198033A publication Critical patent/JPH0198033A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To define even an error of the control information as an ordinary data parity error by adding a control circuit to the selected data to decide the execution of the even or odd parity check.
CONSTITUTION: A multiplexer 5 selects a register 1 or 2 by the instruction of a control signal and stores it in a register 6. The data stored in the register 6 undergo the parity check through a parity check circuit 8 and are delivered to the next stage as long as the normal result is obtained from the parity check. Then an even bit 3 is added to the data of the register 1 and an odd parity bit 4 is added to the data of the register 2. The circuit 8 decides whether the even or odd parity check should be carried out according to a fact whether the data selected by an instruction given from a parity check circuit 9 belongs to the register 1 or 2. Thus it is possible to detect a malfunction through the function of the circuit 8 in case the data of the register 1 or 2 has an error and also in case the multiplexer 5 selects the wrong data.
COPYRIGHT: (C)1989,JPO&Japio
JP62255674A 1987-10-09 1987-10-09 Detecting circuit for data error Pending JPH0198033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62255674A JPH0198033A (en) 1987-10-09 1987-10-09 Detecting circuit for data error

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62255674A JPH0198033A (en) 1987-10-09 1987-10-09 Detecting circuit for data error

Publications (1)

Publication Number Publication Date
JPH0198033A true JPH0198033A (en) 1989-04-17

Family

ID=17282042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62255674A Pending JPH0198033A (en) 1987-10-09 1987-10-09 Detecting circuit for data error

Country Status (1)

Country Link
JP (1) JPH0198033A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262358A (en) * 1989-11-13 1993-11-16 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. Method for producing a silicate layer in an integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61148539A (en) * 1984-12-24 1986-07-07 Nec Corp Information processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61148539A (en) * 1984-12-24 1986-07-07 Nec Corp Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262358A (en) * 1989-11-13 1993-11-16 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. Method for producing a silicate layer in an integrated circuit

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