JPH036760A - Ram fault processing system - Google Patents

Abstract

PURPOSE:To deal with the fault of a RAM in real time with use of a simple circuit by multiplexing the RAM and setting the correct data to a register based on the result of the parity check of the read data. CONSTITUTION:The same data are written into the same addresses of a RAM 1-1 and a RAM 2-1 respectively. If the read data of the RAM 1-1 includes a parity error, a parity check circuit 1-2 reports the presence of the parity error to a RAM deciding circuit 6. At the same time, a parity check circuit 2-2 reports a fact that the read data of the RAM 2-1 is normal. As a result, the circuit 6 decides that the output of the RAM 2-1 is effective and selects the read data given from the RAM 2-1 to set it to a register 7. Thus it is possible to deal with the fault of a RAM in real time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is a RAM fault handling method that supplies all correct data in real time when a fault occurs in the RAM.

[Conventional technology]

Conventionally, as described above, when a failure occurs in the RAM and the data is read out, two methods have been known in which error bits are corrected using a Howe error correcting code (FCC). By the way, when all erroneous bits are corrected using EOO money, a generation circuit for generating gCCCC code acid is required when storing data in RAM.

When reading data from the RAM, a detection circuit that detects which bit of the data has an error based on all Ecc codes and an inversion circuit that inverts the error bit are required.

[Problem to be solved by the invention] Hereinafter, the problem to be solved by the invention is
C code generation circuit The circuit for detecting and correcting errors (detection circuit and inversion circuit) is very complicated and requires a huge number of gates.

As mentioned above, since the error detection and correction circuit is complicated,
The delay when reading data becomes large, and errors cannot be corrected within one machine cycle, resulting in 2 to 3
Mistakes will be corrected during the machine cycle, and control must be performed to stop other processing while the error is being corrected.

In this way, even if a fixed failure occurs in the RAM, the above-described 7'C error p detection, correction, and stop control are always performed, resulting in a substantial performance drop of the computing system.

Furthermore, in the case of error correction using zCal.

There is a problem that if a large number of pits are erroneous in data within the same address or a fault occurs in the entire RAM, it is impossible to detect and correct the error.

SUMMARY OF THE INVENTION An object of the present invention is to provide an entire fault handling method with a simple circuit configuration that does not lead to a decrease in the performance of a computing system.

Another object of the present invention is to provide a fault handling system that can substantially detect and correct errors even if a fault occurs in the entire RAM.

Means for Solving All Problems C] According to the present invention, at least two RAM'i are provided, and read data from each of the RAM's is independently read from each of the RAM's for writing the same data to the same address of the RAM. a parity check means for performing a parity check; and a parity check means for performing a parity check;
A RAM fault handling method is obtained, which is characterized by having a RAM determining means for selecting one of M.

Furthermore, according to the present invention, at least three RAMs 1 are provided, the RAM 2 includes a write means for writing into the at least three RAMs, and a majority decision data bit that compares read data from each of the RAMs pit by pit and determines the majority. A RAM fault handling method is obtained, which is characterized in that the pit value is selected based on the result of the majority decision.

〔Example〕

Next, the present invention will be explained with reference to examples.

Referring to FIG. 1, a system to which the present invention is applied is equipped with at least two RAMs 1 (in FIG.
1-1 and 2-1 are all included). When writing to the RAMs 1-1 and 2-1, a write address is set in the address register 3 and write data is set in the write register 4. Then, by setting write enable (wa) si, RAM1-
The same data is written to the same address of RAM 2-1 and RAM 2-1.

When reading data from RAM 1-1 and 2-1, the address of the data to be read is set in the address register 6.
RAM1-1 and RAM2
The data of the corresponding address written in -1 is output.

The read data from RAMs 1-1 and 2-1 is applied to parity check circuits 1-2 and 2-2, respectively, where they undergo a parity check. Parity check circuits 1-2 and 2-211: Report to the tRAM decision circuit 6 that there is no error. In this case, the RA, M determining circuit 6 selects a predetermined R out of the RAMs 1-1 and 2-1.
Select the AM output and set it in the read register 7.

For example, if there is a parity error in the read data of RAM 1-1, the parity check circuit 1-2 will
A parity error is reported to the AM decision making circuit. On the other hand, the parity check circuit 2-2 reports that the read data from the RAM 2-1 is normal. As a result, R
The AM determining circuit 6 determines that the output of the RAM 2-1 is valid, selects the read data from the RAM 2-1, and stores it in the read register 7.

In the above embodiment, the case where pAMffi is duplicated is explained, but by duplicating all n RAMs (n≧2), failures of n-1 RAMs can be coped with.

Next, a second embodiment of the present invention will be described.

Referring to FIG. 2, the system to which the present invention is applied includes at least five RAM'i.

When writing to RAMs 1-1, 2-1 and 8-1, a write address is set in the address register 5 and all write data is set in the write register 4. Then, write enable (not shown) is set and the RAM 1-1, RAM 2-1, and RAM
Write the same data to the same address for 8-1.

When reading sound data from RAM 1-1.
The data of the corresponding addresses written in 2-1 and 8-1 are output.

These read data are respectively input to the majority decision circuit 6, and a majority decision calculation is performed for each data. RAM 1
-1.2-1 and 8-1 are operating normally, when any bit of the read data is read out, the respective outputs are (0°0.0n or (r,1. 1) 9. When the output of the majority circuit 6 is (0, 0, CI), it is "0" (1
, 1, 1), it becomes "1".

If the read data of RAM 1-1 is incorrect, R
The outputs of AM 1-1.2-1 and 8-1 are (1,010) or (Q, ?, 1) in terms of arbitrary bits. At this time, the majority circuit 6 is "0" when (1, Q, O),
When it is (0, 1, 1), it outputs "1". That is, by taking a majority vote of arbitrary bits, the one with the largest value is determined to be the correct value, and the result is stored in the read register 7.

In the second embodiment, a case was explained in which the RAM is quintupled, but by multiplying the RAMfn (n≧3), integet((n - 1)
/2) errors can be corrected.

〔Effect of the invention〕

As explained above, in the present invention, RAM 1 is multiplexed and the correct data is set in the gold register based on the result of parity check of each read data, so there is an effect that RAM failure can be dealt with in real time with a simple circuit. .

In addition, if the read data is subjected to all majority calculations for each bit, even if many errors occur in the data at the same address in RAM, the read data can be read in real time.
This has the effect of being able to deal with AM failures. Therefore, there is no deterioration in the performance of the calculation system.

Furthermore, in the future, the reliability and operation rate of the system will be improved by increasing the degree of integration of LSIs, especially RAMs.

FIG. 2 is a configuration diagram of another embodiment of the present invention.

1-1.2-1.8-1...RAM, 1-2.2-1
... Parity check circuit, 5... Address register, 4... Write data register, 6... RAM decision circuit, 7... Read register, 9... Majority decision circuit.

[Brief explanation of the drawing]

Fig. 1 is a completed drawing of an embodiment of the present invention, Fig. 2 is a drawing of an embodiment of the present invention. 1 figure Coffin 2

Claims (1)

[Scope of Claims] 1. Writing means that includes at least two RAMs and writes the same data to the same address of the RAMs, and parity check means that independently performs a parity check on data read from each of the RAMs. and RAM determining means for selecting one of the RAMs based on the result of the parity check.
M's failure handling method. 2. It is equipped with at least three RAMs, and has a write means for writing the same data into the same address of the RAM, and a majority means circuit that compares the read data from each RAM bit by bit and takes a majority decision, A fault handling method for a RAM, characterized in that a bit value is selected based on a majority vote result.