JPH01162300A - Rom checking circuit testing system - Google Patents

Abstract

PURPOSE:To easily detect the defect of a ROM checking circuit by storing the inversion data of a cyclic redundancy checking (CRC) besides ordinary CRC data and generating a ROM checking error intentionally when the ROM checking circuit is normal. CONSTITUTION:The title system has a mode to execute a ROM checking by the ordinary CRC and another mode to execute the CRC in an inversion data storing area and test whether the ROM checking circuit is operated correctly or not. For example, the CRCs of 0-(n-2) addresses are calculated, and the CRCs are compared with the contents of an (n-1) address. When the ROM checking circuit is operated normally, since the inversion data of correct data are stored in the (n-1) address, the ROM checking error surely occurs, and when some abnormality exists in the ROM checking circuit, and the ROM checking circuit is not operated, the ROM checking error cannot be detected. In such a case, it is decided that the ROM checking circuit is defective.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a ROM check circuit test method, particularly a ROM that stores program data to which cyclic redundancy check (hereinafter referred to as CRC) data is added, and a method for testing a ROM check circuit. The present invention relates to a ROM check circuit test method in a system having a circuit for checking CRC data.

[Conventional technology]

Conventionally, in a system having a ROM check circuit,
If the ROM check test was not operating due to a defect in this circuit, the test result would only appear to be in the same state as a normal completion.

[Problem that the invention seeks to solve]

In the conventional method described above, it is impossible to distinguish between normal termination and a defective ROM check circuit, so even if the ROM check circuit is defective, the circuit defect is discovered late, and the ROM check is not performed correctly during that time. There is.

An object of the present invention is to discover circuit abnormalities as early as possible by testing a ROM check circuit.

[Means for solving problems]

The method of the present invention is a ROM check circuit test method for a system having a ROM storing program data to which cyclic redundancy check data has been added, and a circuit for checking the cyclic redundant data. The inverted data of the calculation result of the cyclic redundant data in the program data stored at the previous address is stored, and the ROM check is performed using a normal CRC check, and the CRC check is performed in the inverted data storage area. and a mode for testing whether the ROM check circuit is operating correctly.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a ROM address space for implementing the ROM check circuit testing method of the present invention.

In FIG. 1, ROM address space 1 is an address O~ which stores program data with CRC data added.
Program data storage area 2 at (n-2) and CR at address (n-1) where inverted data for the CRC data in the program data at addresses 0 to (n-2) is stored.
C inverted data storage area 3 and address O~(n-1)
It consists of a CRC data storage area 4 in which CRC data of No.F-9 is stored.

FIG. 2 is a flow diagram of one embodiment of the present invention.

First, check the ROM using a normal CRC check.
Select whether to test the ROM check circuit 1.0
), for normal ROM check (mode 1),
Calculate the CRC of addresses O~(n-1) in Figure 1,
Compare with the contents of address n (20), and if there is an error, output an error (4o).

50).

Further, when the ROM check circuit test mode is selected (mode 2), a ROM check circuit test is performed (30), the details of which are shown in FIG.

In Figure 3, the CRC of addresses 0 to (n-2) in Figure 1
Calculate 60) and compare it with the contents of address (n-1) (
70). If the ROM check circuit is working properly,
Since the inverted data of the correct data is stored at address (n-1), a ROM check error will always occur, but R
If there is an abnormality in the OM check circuit and the ROM check does not operate, r(0M check error cannot be detected).

At this time, the present invention determines that the ROM check circuit is defective (80.90).

〔Effect of the invention〕

As explained above, in the present invention, in addition to normal CRC data, inverted CRC data is stored in advance, and when the ROM check circuit is normal, R
By generating an OM check error and checking whether the ROM check circuit can detect the error, there is an effect that a defect in the ROM check circuit can be discovered.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the ROM address space for carrying out the ROM check circuit test method of the present invention, Figure 2 is a flowchart of an embodiment of the present invention, and Figure 3 is a block diagram of the ROM check circuit test method of the present invention.
A detailed flowchart of the OM check circuit test portion is shown respectively. 1... ROM address space, 2... Data storage area, 3... CRC inverted data storage area, 4... CRC
Data storage area.

Claims (1)

[Claims] A ROM in a system that includes a ROM that stores program data to which cyclic redundancy check data is added, and a circuit that checks the cyclic redundancy data.
This is a check circuit test method, in which inverted data of the calculation result of the cyclic redundant data in the program data stored at the previous address is stored in an unused area on the ROM, and the test is performed using a normal CRC check. A mode for performing a ROM check, and a mode for performing a CRC check in the inverted data storage area.
1. A ROM check circuit test method comprising a mode for testing whether a check circuit is operating correctly.