JPH07191914A - Data error correction device - Google Patents

Abstract

PURPOSE:To improve the reliability of stored data by writing prescribed data in the error occurrence address of data read out from a storage device and reading it out and correcting held data based on unmatched contents. CONSTITUTION:An ECC part 7 discriminates whether data read I out from a main storage device 4 is abnormal or not; and if it is abnormal, this data is stored in a read register 9. Plural check data generated by a data error correcting device 3 are written in the address where the abnormality occurs in the main storage device 4, and these check data are read out from this address, and data of bit positions where the written data and read data are unmatching with each other are stored in check data registers 10 and 11. The data error correcting device corrects corresponding bits of data stored in the read register 9 based on unmatching position data stored in check data registers 10 and 11 and transfers corrected data to a CPU 1 through a bus 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data error correction device for correcting an error generated when reading data stored in a main storage device of an information processing device.

[0002]

2. Description of the Related Art In an information processing apparatus or the like, a parity check type error detection circuit or an EC is used for the purpose of detecting or correcting an error that occurs when data is read from a main memory.
An error correction circuit of C (Error Checking and Correction) system is added so that when an error occurs in the data read from the main storage device, this can be detected and corrected.

In this case, when the parity check type error detection circuit writes data to the main storage device, the sum of each bit of this data and one redundant bit (parity bit) is an even number or an odd number. If a parity bit is added and stored in a specified address of the main memory and data is read from this specified address, whether the sum of the parity bit added to this data and each bit of the data is an even number or an odd number It is checked whether or not the data is correct data based on the check result.

In addition, the ECC error correction circuit adds several redundant bits obtained by performing a predetermined operation to this data when writing data of a predetermined width to the main memory device. When data is stored in a predetermined address of the storage device and data is read from the predetermined address, an operation is performed based on the redundant bit added to the data and the data, and whether the data is correct based on the operation result. Check if If the data is not correct, the data is corrected based on the calculation result.

[0005]

However, in the above-mentioned conventional error detection circuit and error correction circuit,
There were the following problems.

That is, since the parity check type error detection circuit has only a function of checking whether the sum total of each bit of the data read from the main storage device is correct, which bit of the read data is abnormal. There was a problem that it was not possible to know if there was any, and the error could not be corrected.

In the ECC type error correction circuit,
Detect which bit of the data is abnormal based on the result of the operation performed based on the data read from the main memory and the redundant bit added to this data, and based on this detection result Although the error of the data is corrected, there is a problem that only a few bits can be detected as the number of abnormality detection bits and only about two bits can be detected as the number of bits that can be abnormally corrected.

The present invention has been made in view of the above circumstances, and an object thereof is to detect whether or not data read from a storage device is abnormal for all bits with a simple circuit configuration. In addition to the above, it is possible to correct all of these bits, thereby providing a data error correction device capable of greatly improving the reliability of data stored in a storage device.

[0009]

In order to achieve the above object, a data error correction apparatus according to claim 1 of the present invention is an error detecting whether or not there is an error in data read from a storage device. When an error is detected by the detecting means and the error detecting means, a data holding means for holding the read data, and when an error is detected by the error detecting means, an error occurs in the storage device. After writing preset data to the specified address, the write data is read from the address and the data comparing means compares the read data with the write data, and the comparison result, the read data and the write data. If there is a disagreement between the data, the data correction means for correcting the data held in the data holding means based on the content of the disagreement is provided. It is characterized by a door.

In order to achieve the above object, the data error correction device according to claim 2 of the present invention comprises an error detection means for detecting whether or not the data read from the storage device has an error. When the error detection unit detects an error in the number of bits that can be corrected by the ECC function in one of the two blocks of data read from the storage device, the data holding unit holds the data,
After writing preset data to a plurality of addresses in which an error has occurred in the storage device, the data is read from the addresses, and the data is held in the data holding unit based on the content of the mismatch of these data. Bit error position detecting means for detecting a bit error position of existing data, and a plurality of error bits detected by the bit error position detecting means are allocated to the data of each block, and then written to each address of the storage device. And a data changing means.

[0011]

In the above structure, according to the first aspect, when the data read from the storage device has an error, the data is held and the address of the storage device in which the error occurs is set in advance. After the written data is written, the write data is read from the address and the read data is compared with the write data. If there is a mismatch between the read data and the write data as a result of the comparison, the data held in the data holding means is corrected based on the contents of the mismatch.

According to a second aspect of the present invention, one of the two blocks of data read from the storage device has an EC
When there are more errors than the C function can correct,
While holding this data, after writing preset data to a plurality of addresses in which an error has occurred in the storage device, the data is read from the addresses, and the data is held based on the contents of inconsistency of these data. The bit error position of the data being detected is detected. When the bit error position is detected, a plurality of detected error bits are allocated to the data of each block and then written to each address of the storage device. With this, with a simple detection and correction circuit,
It detects whether or not the data read from the storage device is abnormal for all bits and corrects all these bits, thereby significantly improving the reliability of the data stored in the storage circuit. Let

[0013]

1 is a block diagram showing an example of an information processing apparatus to which an embodiment (first embodiment) of a data error correction apparatus according to the present invention is applied.

The information processing apparatus shown in this figure has a CPU 1
And a data error correction device 3 connected to the CPU 1 via a system bus 2, and a main storage device 4 connected to the data error correction device 3.

The CPU 1 serves as a control center of the information processing apparatus, and performs information processing, display processing, data storage, reading processing, etc. which are programmed in advance based on various commands and various data output from a keyboard or the like. Executes various processes.

Further, the data error correction device 3 includes a CPU
The input / output unit 5 serving as an interface circuit connected to
An input / output unit 6 serving as an interface circuit connected to the main storage device 4, an ECC unit 7 for performing error correction processing by the ECC function, and three registers (readout register 9,
A register section 8 having a first check data register 10 and a second check data register 11),
When the write command is output from the CPU 1, the data output together with the write command is fetched based on the write command and stored in the designated address of the main storage device 4, and the read command is output from the CPU 1. At this time, the data stored in the designated address of the main storage device 4 is read based on the read command, and the data is error-corrected and supplied to the CPU 1.

The ECC unit 7 has a function of detecting an error in the data read from the main storage device 4 and, if an error is detected, check data written in the main storage device 4 as described later ( It has a comparison / correction function of comparing the write data) with the read data of the check data (read data) to correct the data at the error location.

Read register 9 constituting the register unit 8
Is a register used when error correction is performed on the data read from the main storage device 4, and when the data is read from the main storage device 4 and the ECC unit 7 determines that this data has an error. This data is captured and stored in.

The first check data register 10 constituting the register unit 8 has the same structure as the read register 9:
It is a register used when performing error correction of the data read from the main storage device 4. When the ECC unit 7 detects a data error, the data in the main storage device 4 is stored. After writing "1" to all bits of the address, read this data and compare it with the original data. If there is a mismatch bit, "1" is set at that position (mismatch position data). Capture and hold.

Further, the second check data register 11 constituting the register unit 8 is used when correcting the error of the data read from the main storage device 4, like the read register 9 and the first check data register 10. When a data error is detected by the ECC unit 7, after writing "0" to all the bits of the address in the main memory 4 where the data is stored, As a result of reading this and comparing it with the original data, the data in which "1" is set at the position of the mismatch bit (mismatch position data) is fetched and held.

The main memory 4 is provided with a semiconductor memory element used as a work area of the CPU 1 and the like, and when a write command is output from the data error correction device 3, it is output together with this write command. The data is stored in the designated address, and the data error correction device 3
When a read command is output from, the data stored in the address specified by this read command is read,
This is supplied to the data error correction device 3.

Next, the procedure of the error detection / correction processing of this embodiment will be described with reference to the flow chart shown in FIG.

First, the ECC section 7 determines whether or not there is an abnormality in the data read from the main storage device 4 (step ST
1, ST2), if there is no abnormality, this data is transferred to the CPU 1 (step ST3), and the next data is read from the main memory 4 to determine whether or not there is an abnormality.
On the other hand, if there is an abnormality in the data and this is detected by the ECC unit 7, the data in which this abnormality has occurred is captured and stored in the read register 9 (step ST
4).

Next, the data error correction device 3 generates check data in which all the bits are "1" and writes the check data in the address in the main storage device 4 where the abnormality occurs, and then the check is performed from this address. The check data is read out, and these check data, that is, the written check data is compared with the read check data (steps ST5 and ST6). If there is a mismatched bit as a result of the comparison, data in which "1" is set at this bit position (mismatched position data) is generated and stored in the first check data register 10 (step ST7). .

Next, the data error correction device 3 generates check data in which all the bits are "0" and writes the check data in the address in the main storage device 4 where the abnormality occurs, and then the check is performed from this address. The check data is read out, and these check data, that is, the written check data is compared with the read check data (steps ST8 and ST9). If there is a mismatched bit as a result of the comparison, data in which "1" is set at this bit position (mismatched position data) is generated and stored in the second check data register 11 (step ST10). .

Then, when these processes are completed, the data error correction device 3 causes the read register 9 to read the data based on the position of the bit "1" of the mismatch position data stored in the first check data register 10. The corresponding bit of the stored data is modified, and the data stored in the read register 9 based on the position of the bit which is "1" of the data stored in the second check data register 11. Corresponding bit is corrected (step ST11).

As a result, even if the data stored in the read register 9 has an error of 3 bits or more, it is corrected to be correct data. The corrected data is transferred to the CPU 1 via the bus 2 (step S
T12).

The above process will be described in more detail with reference to FIG. 3. Assuming now that an error of 16-bit read data is detected by the ECC unit 7, FIG.
As shown in (a), this 16-bit data “00101010
"10101011" is stored and held in the read register 9. At this point, it is unknown which bit is in error.
Check data in which all 6 bits are "1" is written to the corresponding address of the main storage device 4 where the data error has occurred, and this write data is read. Then, the write data and the read data are compared with each other, and if there is a non-coincidence portion, non-coincidence position data with "1" is generated and stored in the first check data register 10. In the example of FIG. 3B, “1” is set in the upper 2nd bit, and it can be seen that there is a data error in this bit. Next, the check data in which all 16 bits are "0" is written to the corresponding address of the main storage device 4 where the data error has occurred, and this write data is read out. Then, the write data and the read data are compared, and if there is a disagreement, "1"
The non-coincidence position data that has been set is generated and stored in the second check data register 11. In the example of FIG. 3C, "1" is set in the lower 2nd bit, and it can be seen that there is a data error in this bit.

The above two check data registers 10,
It can be determined from the data stored in 11 that the data held in the read register 9 has an error in the data of the upper 2nd bit and the data of the lower 2nd bit, and as shown in FIG. The data in register 9 is "011010101010".
After being corrected to 1001 ″, it is transferred to the CPU 1.

As described above, in this embodiment, when the data read from the main storage device 4 has an error, all bits are "1" for the address in the main storage device 4 where the data is stored. The check data set to "0" is written / read / compare, the check data set to "0" in all bits is written / read / compare, and read from the main memory 4 based on the comparison result of these data. Since the data error is corrected, whether or not the data read from the main storage device 4 is abnormal can be detected for all bits with a simple circuit configuration, and at the same time, all of these bits can be detected. Corrections can be made, which can greatly improve the reliability of the data stored in the main storage device 4.

FIG. 4 is a block diagram showing an example of an information processing apparatus to which another embodiment (second embodiment) of the data error correction apparatus according to the present invention is applied. In addition, in this figure,
The same parts as those in FIG. 1 are designated by the same reference numerals.

The information processing apparatus of this embodiment is different from the information processing apparatus shown in FIG. 1 in that the system bus 2 as shown in FIG.
Data having a bit width of 2 (n + α) (α is the bit width of the check bit) with respect to the bit width of (n bits) of (n + α) is made into a block of (n + α) bit units, and this is a main memory device. Or write to 4,
In addition to reading, the ECC unit 7 provided in the data error correction device 3 performs 2-bit error detection and 1-bit error correction.

When the CPU 1 issues a read command, the data error correction device 3 reads two interleaved (n + α) -bit data (blocks) from the main storage device 4 and outputs them. De-interleave to reproduce 2 (n + α) -bit data (block), and when there is a 1-bit error in each of these blocks, the ECC unit 7 directly corrects this and supplies it to the CPU 1. When there is a 2-bit error in either one of the deinterleaved 2 (n + α) -bit blocks, the error is corrected by the same error correction method as in the first embodiment and supplied to the CPU 1. At the same time, after interleaving the two erroneous bits and distributing them into each block of (n + α) bits, they are stored in the main storage device 4. It can included, which again, when reading is adapted to correct this directly by the ECC unit 7.

In this case, specifically, data error detection and error correction are performed by the procedure described below.

First, as shown in the flow chart of FIG.
When a read command is output from the CPU 1 and is supplied to the data error correction device 3 via the system bus 2, the data error correction device 3 causes the two addresses specified by the read command in the main storage device 4. Two pieces of stored data ((n + α) -bit data) are read (step ST21), deinterleaved to form two (n + α) -bit blocks, and then converted into α-bit check bits. Based on this, error detection processing and error correction processing are performed for each block (step ST22).

Then, the above-mentioned 2 which has been de-interleaved
If the (n + α) -bit block is a 1-bit error that can be corrected by the ECC unit 7, the ECC unit 7 directly corrects the error to correct 2n-bit data (steps ST22 and ST23), and then n bits. Units are sequentially supplied to the CPU 1 via the system bus 2 (step ST13).

If the block of 2 (n + α) bits is an error of 3 bits or more among the errors that cannot be corrected by the ECC unit 7, the error is 3 bits or more (step ST2).
4) The data error correction device 3 determines that a system error or the like has occurred, and the determination result is transmitted to the CPU 1 for system error processing (step ST11).

If the 2 (n + α) -bit block is a 2-bit error among the errors that cannot be corrected by the ECC unit 7 (step ST24),
The data error correction device 3 generates a busy signal (busy signal) indicating that processing is currently being performed,
The CPU 1 is prevented from making a new access (step ST25).

Thereafter, the data error correction device 3 sets all the bits to "1" for the two addresses in the main storage device 4 where the respective data were stored, as in the above-described embodiment. After the check data is written / read / compared, all the bits are set to “0”, and the check data is written / read / compared and read out from the main memory 4 based on the comparison result. (N +
The position of the bit error in the (α) -bit data is detected, and the error is corrected (step ST26, S
T12) After being converted into correct 2n-bit data, the data is supplied to the CPU 1 via the system bus 2 (step ST13).

In parallel with this operation, the data (2 (n
The error bit position of the first bit in (+ α) -bit data) is interleaved and assigned to one block ((n + α) -bit data)
At the same time (step ST27), the error bit position of the second bit in the error-corrected data (2 (n + α) -bit data) is interleaved and in the other block ((n + α) -bit data). Is assigned (step ST28).

Thereafter, the data error correction device 3 performs error-corrected data (2 (n + α) -bit data) so that the bit width of the one block becomes equal to the bit width of the other block. The remaining bits constituting the block are allocated to each block, and the (n + α) -bit data obtained thereby is written to the two addresses in the main memory 4 where the data was stored (step ST29).

Next, the data error correction device 3 stops the output of the busy signal (busy signal), and the ready signal (rea) indicating that no processing is currently being performed.
dy signal) is generated, and the CPU 1 starts a new access (step ST30).

As described above, in this embodiment, when the data read from the main storage device 4 has an error, all bits are "1" for the address in the main storage device 4 where the data is stored. Write the checked data /
In addition to reading / comparing, writing / reading / comparing check data in which all bits are set to “0”, and an error of the data read from the main storage device 4 is corrected based on the comparison result. Therefore, it is possible to detect whether or not the data read from the main storage device 4 is abnormal for all bits by a simple detection and correction circuit, and it is possible to correct all these bits. Thus, the reliability of the data stored in the main storage device 4 can be significantly improved.

Further, in this embodiment, when the CPU 1 issues a read command, the data error correction device 3
Read out two interleaved (n + α) -bit data (blocks) from the main memory 4 and de-interleave this to obtain 2 (n +
When the α (bit) data (block) is reproduced and there is a 1-bit error in each of these blocks, the ECC unit 7
This is directly corrected and supplied to the CPU 1, and when there is a 2-bit error in any one of the deinterleaved 2 (n + α) -bit blocks, the same error correction as in the first embodiment described above is performed. Method, the error is corrected and supplied to the CPU 1, two error bits are interleaved, distributed to each block of (n + α) bits, then written to the main storage device 4, and read again. At this time, since the ECC unit 7 can directly correct this, even if the ECC unit 7 causes a 2-bit bit error that cannot be directly error-corrected by the ECC unit 7, When reading this again, the ECC unit 7 can directly correct it.

[0045]

As described above, according to the present invention, whether or not the data read from the storage device is abnormal can be detected for all bits with a simple circuit configuration, and all of these bits can be detected. Bit correction can be performed, which can greatly improve the reliability of the data stored in the storage device.

According to the second aspect of the present invention, even if a 2-bit error occurs in the block-unit data stored in the storage device, this can be directly corrected by the ECC function.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an information processing apparatus to which an embodiment of a data error correction apparatus according to the present invention is applied.

FIG. 2 is a flowchart showing error detection / correction processing in the embodiment shown in FIG.

FIG. 3 is an explanatory diagram showing an example of error detection / correction operation in the embodiment shown in FIG.

FIG. 4 is a block diagram showing an example of an information processing apparatus to which another embodiment of the data error correction apparatus according to the present invention is applied.

5 is a flowchart showing an error detection / correction process in the embodiment shown in FIG.

[Explanation of symbols]

 1 CPU 2 System Bus 3 Data Error Correction Device 4 Main Storage Device 5, 6 Input / Output Section 7 ECC Section 8 Register Section 9 Read Register 10 First Check Data Register 11 Second Check Data Register

Claims (2)

[Claims] 1. An error detecting means for detecting whether or not there is an error in data read from a storage device, and a data holding means for holding the read data when an error is detected by the error detecting means. When an error is detected by the means and the error detection means, preset data is written to the address in the storage device where the error has occurred, and then the write data is read from the address, and this read is performed. Data comparing means for comparing the data with the write data, and if the result of the comparison shows that there is a mismatch between the read data and the write data, the data held in the data holding means is corrected based on the contents of the mismatch. A data error correction device comprising: a data correction unit. 2. An error detecting means for detecting whether or not there is an error in the data read from the storage device, and 2 read from the storage device by the error detecting means.
When an error of more than the number of bits that can be corrected by the ECC function is detected in one of the blocks of data, a data holding unit that holds this data, and a plurality of addresses in which an error occurs in the storage device, After writing preset data, the data is read from the address, and the bit error position detecting means for detecting the bit error position of the data held in the data holding means based on the content of the mismatch of these data And a data changing unit that writes a plurality of error bits detected by the bit error position detecting unit in the data of each block and then writes the data in each address of the storage device. Error correction device.