JPH0367346A - Address control circuit - Google Patents

Abstract

PURPOSE:To surely control the address of a memory by obtaining a duplex memory address control circuit and applying the read addresses after checking the coincidence/discordance of these addresses together with the parity check. CONSTITUTION:The buffers 12a and 12b and the RAM 14a and 14b are formed into a duplex structure, and the read outputs are selected by selectors 18 and 26. The comparators 24 and 32 check the coincidence/discordance of those read outputs. Furthermore the parity check circuits 22 and 28 check the presence or absence of parity errors. Then the logic circuits LOG 20 and 30 operate the selectors 18 and 26 with the outputs of the comparators 24 and 32 and the circuits 22 and 28 to attain the necessary selecting operations. Thus the addresses read out of a memory 10 are applied or not according to the results of the comparators 24 and 32 and the circuits 22 and 28. As a result, two types of checks are carried out and the error detecting factor is improved. Then the address of the memory 10 is correctly controlled.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding an address control circuit for a memory using a random write/random read method, the present invention aims to more reliably control the address of a memory using a random write/random read method. A FIFO buffer that generates a write address of the memory, and a RAM that generates a read address of the memory, and transfers the write address to the RAM and the read address to the I/O buffer.
In the random write/random read memory address control circuit that stores in the PIFO buffer, the FIFO
The FO buffer and the RAM are duplicated, and the duplicated FI
A selector that selects each readout output of the FO buffer and RAM, a comparator that detects coincidence/mismatch of each readout output, a parity check circuit for each readout output, and a selector that uses the outputs of these comparators and parity check circuits. The configuration includes a logic circuit for operation.

[Industrial application field]

The present invention relates to an address control circuit for a random write/random read type memory.

In a communication device, data is normally stored once and then read out and output when necessary, and various types of memories (RAM, PIFO, etc.) are used as data storage buffers. The present invention relates to address control of a random write/random read storage buffer using a RAM.

[Conventional technology]

An example of an address control circuit for a random write/random read buffer is shown in FIG. 3. 10 is a memory (data storage buffer RAM), and 12 is a FIFO (First
irst out) memory, and 14 is a RAM (Randos Access Me) that generates a read address.
Mory). PIFO12 has an address (RAM
14 is stored and read out in the order of storage, this becomes the write address of the memory 10. Input (IN) data is in memory 10, PIFOL
2 is written to the output address.

An address (this is the write address output by the FIFO 12) is also written in the RAM 14, and this is read out and becomes the read address of the memory IO.

This address writing/reading control is performed by the control section 16. The address output by the RAM 14 becomes the read address of the memory 10, and is also stored in the FIFO 12 and eventually becomes the write address.

If the address stored in FIPO 12 is the read address of memory IO, then the address in FIFO 12 is an empty address of memory IO, an address that has been read and is no longer needed, and writing new data to memory 10 is done using this empty address. This is done for the address, which allows efficient use of the memory 10. Control unit 16
manages which data is stored in which address of the memory IO, and controls so that the required data is output at the required timing.

There is also a sequential write/sequential read method for memory, but this method cannot be used if the data processing order is irregular. If they are not aligned, the only option is to perform a random read even if a sequential write is performed, and in order to use the memory effectively by performing a random read, a random write must be performed to the address vacated by the random read.

Many proposals have been made for memory address control.
JP-A-54-78036 is also an example.

This deals with duplication of memory, control of its addresses, etc. That is, the CPU communicates with the duplicated memories, collates and uses read data from both memories. To do this, first, a parity check is performed, and the read data with an error is rejected, and if there is no error in both, the read data are compared, and if they match, the read data is accepted. If there is a mismatch, a retry is performed, but this is not possible if there is an address error. Therefore, the read address output by the CPU is stored in the source address register, and sent from there to the address register of each memory to access each memory. Compare the contents,
Lead data that does not match will be rejected.

[Problem to be solved by the invention]

In the memory of the random write/random read system shown in FIG. 3, the write address and the read address form one loop, and the write address eventually becomes a read address, and the read address eventually becomes a write address. When an address is used cyclically in this way, a bit error that occurs somewhere during the cycle will be used repeatedly without being corrected.

For example, the addresses ADRO and ADRl in PIFO12
, ADR2, ...... are packed in this order, and first A
When DRO is output and becomes the write address of the memory 10, and when waiting for this to be sent to the RAM 14 and become the read address, if there is a bit error in this transfer path and ADRO becomes ADR2, the address will be stored in the RAM 14. Since there are two ADR2s and no address ADRO, the data of ADRo cannot be read forever.
That's what it comes down to. In addition, the control unit 16
Since R2 is recognized as ADRO, ADR2 is read twice (one is erroneous), this is written to PIFOI2, and ADR2 is written twice (data is destroyed).

In order to avoid such an abnormal state, the parity check described in the above-mentioned Japanese Patent Application Laid-Open No. 2002-121014 is usually considered, but this cannot completely prevent the abnormality. In the parity check method, the error detection rate is 50% because the judgment is between an even number and an odd number.

It is an object of the present invention to improve the above points and more reliably perform address control of a random write/random read type memory.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, the FIFO buffer 12 and RAM 14 are duplicated. 12a and 12b are part 2
The duplicated FIFO buffers 14a and 14b are duplicated RAMs.

These FIFO buffers and RAM are provided with output address selectors 18 and 26, comparators 24 and 32, and a parity check circuit 22, and logical judgments are made according to the comparison and parity check results.
A logic circuit 20.30 for controlling 26 is provided.

[Effect]

In such a configuration, if the bit error described above occurs at location (■) (the same applies if it occurs at location (■■■), etc.), when it becomes a read address, the comparison result of comparator 32 will be a mismatch. This mismatch result is sent to logic circuit 30, which also receives the parity check result from circuit 28. The logic circuit 30 operates the selector 26 by making logical judgments based on these human powers. In this example, the error address is the output address of the RAM 14b, and therefore the error will be detected by the parity check circuit 28 with a probability of 50%. Since the output of the comparator 32 is a mismatch and the output of the check circuit 28 is a parity error, the logic circuit 30 determines that the output of the RAM 14a is correct, causes the selector 26 to select the output of the RAM 14a, and stores it in the memory 10. This is the read address. It also raises an alarm to notify you of an abnormality.

Although the output of the comparator 32 does not match, when the parity check circuit 28 cannot detect a parity error and outputs that the parity is normal, it does not cause the selector 26 to select either output, but simply raises an alarm. In this case, R
It is preferable to provide a parity check circuit on the AM 14a side as well. If the comparison result is a mismatch, one parity is in error, and the other is normal, the logic circuit causes the selector to select the RAM output with normal parity.

In this way, not only a simple parity check but also a data comparison is performed to determine which RAM output (read address) to use, making it possible to output a read address more reliably. Also, if either the comparator or parity check circuit shows an abnormality, an alarm will be issued.
This makes it possible, for example, to check the contents of RAM or FIFO to find abnormal data and repair it.
This can prevent error data (addresses) from circulating.

Note that it is normal for the addresses in the RAM and FIFO to have all the addresses in the memory 10, although in different orders, but it is abnormal for there to be missing addresses or the same addresses. It can be done in principle.

〔Example〕

FIG. 2 shows an embodiment of the present invention. As in all figures, parts that are the same as in other figures are given the same reference numerals. In FIG. 2(a), the logic circuit 20 is composed of an OR gate 20a. Now, the output of FIFO12b is error, PIFOI
Assuming that the output of 2a is normal, the output of the parity check circuit 22 is a parity error "0", the output of the comparator 24 is a mismatch "O", the output of the OR gate 20a is 0", and the selector 18 is set to the 0 side (FIFOt When the outputs of both FIPOIs 2a and 12b are correct, the output of the circuit 22 is "1", the output of the comparator 24 is "1",
The output of the OR gate 20a is "1" and the output of the PIFO 12b is selected. That is, this circuit is fixed so that when both FIFOs are correct, the output of PIFO 12b is selected.

FIG. 2(b) shows both PIFOf 2 a, 12
An example is shown in which parity checks 22 and 26 are provided in b. In this case, the logic circuit 20 selects the selector 1 based on the following logical judgment.
You can manipulate the day. That is, (1) when the outputs of the comparator 24 match and the outputs of the check circuits 22 and 26 are both normal, one of FIFO I 2 a and l 2 b is selected; (2) when the outputs of the comparator 24 do not match, check If one of the circuits 22 and 26 is normal, select the normal FIFO. ■If the outputs of the comparator 24 do not match, and the outputs of the check circuits 22 and 26 are both normal, which FIFO is selected.
IFO is not selected either. (2) If the output of the comparator 24 is a match, but one or both of the check circuits 22 and 26 are in error, neither PIFO output is selected.

Although FIG. 2 shows the FIFO side, the RAM 14a.

The same applies to the 14b side.

Selector 18.26 to RAM 14a, 14b.

It is best to use a separate signal line from the output end of the selector for the signal line for address transfer to FIFOI 2a and 12b, to prevent bit errors caused by noise on both paths at the same time. can be avoided.

〔Effect of the invention〕

As explained above, in the present invention, the random write/random read memory address control circuit is duplicated, and depending on the match/mismatch of read addresses and the parity check result, which address is adopted or neither is adopted. , it is possible to improve the error detection rate and read/write data correctly compared to a method using only a parity check.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a random write/random read memory. In FIG. 1, 10 is a memory into which data is read/read;
12a and 12b are FIFO buffers; 14a; 14b is RAM, 18.26 is a selector, 24°32 is a comparator, 22.28 is a parity check circuit, 20.3
0 is a logic circuit.

Claims (1)

[Claims] 1. Memory to which data is written and from which it is read (1)
0) and a FIFO that generates the write address of the memory.
It includes a buffer (12) and a RAM (14) that generates a read address for the memory, and the write address is transmitted to the RAM.
In a random write/random read memory address control circuit that stores the read address in the FIFO buffer, the FIFO buffer and the RAM
selectors (18, 26) that select each readout output of the duplicated FIFO buffer and RAM, and comparators (24, 3) that detect coincidence/mismatch of each readout output.
2) and a parity check circuit (22,
28) and a logic circuit (20, 30) that operates the selector based on the outputs of these comparators and parity check circuits.
).