JP2943926B2 - Error recovery control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an error recovery device of a main storage control device that controls access to a plurality of main storage devices from a terminal device. In a system in which a plurality of main storage devices and a plurality of terminal devices are cross-bar-connected via two main storage control devices, with a view to avoiding and enabling access to the main storage device, A latch for storing a busy state of the bank corresponding to the total number of banks of the main storage device in the main storage control device, a local input port for receiving a request signal from each terminal device at an input portion, and a counterpart main storage control device. And a comparison circuit for comparing whether corresponding bits of the pair of latches match each other. The busy state due to the request from the terminal device is configured so that the same value is stored in the latch, and the output of the comparison circuit detects the occurrence of synchronization loss in which the corresponding bits of the pair of latches do not match. Then, all the contents of the latch are reset to each other.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error recovery device of a main storage control device that controls access from a terminal device to a plurality of main storage devices.

[Prior Art] FIG. 3 is a block diagram showing a configuration example of a conventional device. A plurality of main storage units (MSUs) 1 and a plurality of terminal devices 2 are cross-bar-connected via two main storage control units 3. The main storage control device 3 and the main storage device 1 are connected by an output port 3b, and the main storage control device 3 and the terminal device 2
Are connected at the input port 3c. Input port
3c is divided into a local port and a remote port, and one local port and the other remote port are connected to each other.

As the terminal device 2, a CPU, a vector processor VU, or the like is used. Reference numeral 3a denotes latches that store busy states corresponding to the total number of banks of the main storage device 1, and are provided in both main storage control devices 3, respectively.

FIG. 4 is a diagram showing a divided state of each main storage device.
One storage device is composed of, for example, 128 banks, and the hatched area in the figure is one bank. Access to this storage device is made on a bank-by-bank basis. In the example shown in FIG. 3, since there are four main storage devices, the total number of banks is 128 × 4 = 512. Therefore, the number of bits of the latch 3a is 512 bits, and the bit at the address corresponding to the bank being accessed becomes 1 in a busy state. Each terminal device 2 performs a busy check (Busy Check) when accessing the main storage device 1, and when the bank to be accessed is in a busy state (a state where 1 stands), the access is prohibited. The accessed bank is reset to 0 when writing or reading is completed. The bank that has become 0 can be accessed from the terminal device 2.

In this type of multiprocessor system, for example, MCU0
If there is a request from the CPU 0 on the side, the request enters the local input port 3c, and the same information enters the remote input port 3c on the other side (MCU1). Conversely, if there is a request from the CPU 2 of the MCU 1, the request enters the local input port 3 c and the same information enters the remote input port 3 c of the partner (MCU 0). Then, "1" indicating a busy state is written into the corresponding address of the latch 3a according to the request information input from each input port. As a result, data indicating the same busy state is written to both latches 3a. However, the actual access to the main storage device 1 is performed only from the local input port 3c.

The reason why such a multiprocessor system is used is that, in the case of a vector processing device, the throughput required in one cycle is high, and a request issued from a terminal device is made to a plurality of banks. This is because it is necessary to respond quickly to the request.

[Problems to be Solved by the Invention] In the system as described above, if all the contents of the busy latches 3a in the various storage control devices 3 do not match,
That is, when a synchronization loss occurs, an error has occurred in one of the main storage controllers, but there is no means for checking which of the main storage devices has caused the error. It often ends in a stopped state. Further, in this type of conventional system, a recovery process is required when a request is waited for a certain period of time, that is, when a hung state occurs, and a recovery means for this is provided.

The present invention has been made in view of such a problem, and an object of the present invention is to provide an error recovery control device that can improve reliability by avoiding a check stop or a hang state.

[Means for Solving the Problems] FIG. 1 is a principle block diagram of the present invention. The same components as those in FIG. 3 are denoted by the same reference numerals. However, the input port is 3c for the local port and 3c 'for the remote port. In the figure, reference numeral 3d denotes a comparison circuit for detecting the coincidence or non-coincidence of the bit data at the corresponding addresses of the two latches 3a, and 3e denotes an OR gate receiving the outputs of both the comparison circuits 3d. The outputs of these OR gates 3e are supplied to the respective latches 3a as all-busy reset signals. Although four main storage devices MSU0 to MSU3 are shown in the figure, the present invention is not limited to this, and any number may be used. CPU
And the like for the terminal device 2.

[Operation] The data at the corresponding addresses of the busy latches 3a in the two main memory controllers 3 are compared bit by bit by the comparison circuit 3d. If the check stops or the state before the hang state occurs, the latch A mismatch occurs in the busy data at the corresponding address of 3a. If any one of these mismatch states occurs, at least one of the comparison circuits 3d becomes "1". When at least one becomes "1", its output is also in the other OR circuit, so that all the busy states of both latches 3a are reset to "0". As a result, the main memory control device 3 enters an error processing routine due to a main check interrupt or the like. Thus, according to the present invention, it is possible to provide an error recovery control device that can improve the reliability by avoiding a check stop or a hang state.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing one embodiment of the present invention. 1 are denoted by the same reference numerals.
In the figure, 3g is a priority circuit that determines which of the three types of busy signals of the terminal device of the latch 3a is to be output with priority, and 3h is each time the MSU GO signal output from the priority circuit 3g is received. , A reset pipeline for resetting the corresponding address in the latch 3a. The comparison circuit 3d receives the MSU GO signal (including its own and the other party's signal, a kind of busy signal) output from each priority circuit 3g, and detects a match or mismatch between these two signals.

The difference between the principle diagram shown in FIG. 1 and the embodiment of FIG. 2 is that the principle diagram of FIG. The point is that the output busy signals are compared with each other. Since the circuit configuration becomes complicated when the comparison is made for each bit of the latch, the busy signals output for each terminal device are compared. Such a comparison is practically sufficient. The busy signal (MSU GO signal) output from the priority circuit 3g is MSU
It is connected to each main storage device 1 in the form of a crossbar as a request signal. An embodiment of the apparatus configured as described above will be described below.

For example, if a request is generated from CPU0 of MCU0, the request signal enters corresponding local input port 3c. At the same time, it enters the remote input port 3c 'of the other main storage device MSU1. These request states are:
The corresponding address of each corresponding latch 3a is set to a busy state (a state where "1" is set). Assuming that there is another request on the MSU0 side, the priority circuit 3g selects and outputs the highest priority busy signal. This output (MS
UGO) makes the corresponding main storage unit (MSU) busy via the output port 3b. At the same time, priority circuit 3
The output of g is reset to “0” by resetting the contents of the corresponding latch 3a via the reset pipeline 3h. As a result,
Other terminal devices can access the bank. This reset operation is also performed in the other party's main storage device 3.

Here, if a mismatch occurs in a part of the pair of latches 3a, it is treated as system damage, all the latches of all the main memory control devices 3 are reset, and all the remaining requests of the main memory control device 3 are processed. After completion, a machine check interrupt is generated and an error processing routine is entered. Therefore, according to the present invention, if a mismatch occurs in the data of the busy latch 3a, the occurrence of these states can be avoided before the check is stopped or a hang state is reached, and the reliability can be increased.

[Effects of the Invention] As described in detail above, according to the present invention, the contents of the latches provided in the pair of main memory control devices are always configured to be the same data, and the addresses of the corresponding addresses of the two are controlled. It is possible to provide an error recovery control device that can improve the reliability by avoiding a check stop or a hang state by performing a predetermined alarm process by determining that the synchronization is lost when the contents do not match.

[Brief description of the drawings]

 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing a configuration example of a conventional system, and FIG. FIG. In FIG. 1, 1 is a main storage device, 2 is a terminal device, 3 is a main storage control device, 3a is a latch, 3b is an output port, 3c is an input port (local), 3c 'is an input port (remote), and 3d. Is a comparison circuit, and 3e is an OR gate.

Claims (1)

(57) [Claims] 1. A system in which a plurality of main storage devices (1) and a plurality of terminal devices (2) are cross-bar-connected via two main storage control devices (3). (3) a latch (3a) for storing a busy state of a bank corresponding to the total number of banks of the main storage device (1), and a local input port (3c) for receiving a request signal from each terminal device at an input section. A remote input port (3c ') for inputting a request signal from the other party's main memory control device (3); and a comparison circuit (3d) for comparing whether corresponding bits of the pair of latches (3a) match. ), And the busy state due to the request from each terminal device (2) is configured so that the same value is stored in the latch (3a), and a pair of latches are output by the output of the comparison circuit (3d). Corresponding bit of There upon detecting that the sync collapse no longer match occurs, the error recovery control unit configured to reset all the contents of the latch together.