JPH02199562A - Duplicated memory copy system - Google Patents

Abstract

PURPOSE:To attain the coincidence of contents of duplex memories at real time by turning a memory device in a waiting system also to a driving state at the time of outputting a writing instruction to a memory device in an operational system and simultaneously writing the contents of both the memories. CONSTITUTION:A self-system/other system distinguishing code bit for the operating system X is built in a memory address and a connecting device 4 including memory bus connecting circuits 4X, 4Y for the standby system Y and the operating system X is provided with a memory address modifying circuit and an address strobe modifying circuit. When a writing instruction is outputted to an operating system memory device 2X, the information of the self-system display code bit is inputted to a memory 2Y in the waiting system by means of the memory address modifying circuit, fixed modification is applied to an address strobing signal outputted to the operating system X by means of the address strobe modifying circuit and the modified result is written in the memory 2Y of the standby system Y. At the time of writing information in the operating system memory, the same information is written also in the waiting system memory in the same writing cycle and the coincidence of contents of the duplex memories can be attained at real time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention has dual processors and memory devices,
The present invention relates to a duplex memory copy method for matching the storage contents of memory devices of both systems in a data processing system comprising an active system and a standby system.

[Prior Art] A duplex memory copy method is a processing method for matching the contents of a duplex memory, and specific examples of the data processing system that requires this method include a so-called duplex processor device, fault tolerant
Mention may be made of processor devices.

Now, ``Conventionally, as a duplex memory copy method in such a data processing system, Japanese Patent Application Laid-Open No. 60-8664
The technology described in Publication No. 0 was developed.

This technology connects a processor, a data processing circuit for copy processing, a bus arbiter, etc. to a memory bus shared by two memory devices, and then transfers data to one memory device according to a memory copy instruction command output from the processor. This is to copy the written data to the memory device of the other system.

[Problems to be Solved by the Invention] In the duplex memory copy method as described above, when a write d command is issued, writing to one memory device is first completed, and then the further Since data written in one memory device is copied to the other memory device, there is a problem in that the contents of the dual memories sometimes do not match, and this problem has been considered to be a problem to be solved in the future.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a duplex memory copying method that can achieve matching of the contents of duplex memories in real time.

[Means for Solving the Problems] The duplex memory copy method according to the present invention is a data processing system in which a processor and a memory device are duplexed to constitute an active system and a standby system, in which a write command is issued. In this case, the same data is written to the memory devices of both systems in a -write cycle.

Specifically, a code bit for distinguishing between the active system and the other system is incorporated into one of the empty bits of the memory address in advance, and the code bit is inserted during read/write processing. is loaded into each memory device, and the memory device selected by the sign bit is operated.

In addition, the active and standby memory buses are connected to each other via a memory bus communication device, and this memory bus communication device is equipped with a memory address modify circuit and an address strobe modify circuit. put.

The memory address modify circuit is a circuit that operates a standby memory device using the sign bit when a write command is output to the active memory bus.

The address strobe modification circuit modifies the address strobe signal output from the active memory bus communication device to the address strobe modification circuit of the standby memory bus communication device when a write command is output to the active memory bus. This is a circuit that performs certain modifications on the circuit and outputs it to the standby memory bus.

[Operation] The duplex memory copy method according to the present invention incorporates a code bit into the memory address to distinguish between the active system and the other system, and further connects the memory buses of the standby system and the active system to each other. The memory bus communication device includes a memory address modify circuit and an address strobe.
This configuration includes a modify circuit.

When a write command is output to the active memory device, the memory address modify circuit is used to cause the standby memory device to take in the code bit data indicating the own system, and the address strobe・Using a modify circuit, certain modifications are made to the address strobe signal output to the active system, and the output is output to the standby system memory device to perform writing.

Therefore, when the active memory device writes data, the same data can be written to the standby memory device in the same write cycle, achieving matching of the contents of the redundant memory in real time. can do.

[Example] Hereinafter, an example of the present invention will be described based on FIGS. 1 to 5.

The duplex memory copying method of one embodiment is used in a data processing system in which processors and memory devices are duplicated to configure an active system and a standby system. When a write command is issued to one memory device, the standby memory device is also put into operation, and writing is performed in both memory devices at the same time.

In order to perform such processing, in the duplex memory copy method of one embodiment, not only the system configuration is devised, but also the bit allocation in the memory address is devised.

First, the system configuration will be briefly explained.

A data processing system using the duplex memory copy method of one embodiment is a so-called duplex processor device, and is used as a fault-tolerant processor device.

Specifically, as shown in Figure 2, the operational system
and a standby system Y (it is not fixed whether it is an active system or a standby system; if one of them is operating as an active system, the other is a standby system). Become).

Each of the active and standby systems has a processor (cp
u) 1x+ly, memory devices 2x, 2Y, and memory buses 3x, 3Y, with memory bus 3x
, 3Y are connected to each other via a newly installed memory bus communication device 4 for duplex memory copying.

This memory bus communication device 4 includes an active memory bus communication circuit (MXC) 4X and a standby memory bus communication circuit (MXC) 4X.
MXC) 4y, both memory buses 3X
, 3Y, signals are received and passed.

The memory areas of the aforementioned memory devices 2X and 2Y will be explained using FIGS. 3 and 4.

The bit allocation of the memory address has the configuration shown in FIG.

That is, the memory addresses are (n
+1) bits. And among them, A
. - (a+1) bits of A6 (where l<a<n
) is used as an effective bit representing the memory area of one system. Also, A, 4. The bits ~An are so-called empty bits that do not affect the memory capacity or any devices in the system. Then, the most significant bit l−A among these vacant bits A a+ 1 to An
. is used as a code P to distinguish whether the active system X is the own system or the other system.

This sign bit P indicates the own system when it is “0”, and “l”
", it indicates a different system, and the code bit P is sent to each memory device 2x during read/write processing.

It is imported into 2Y and used as a condition for determining whether the self is selected.

As a result, the memory device that has taken in "0" as the sign bit P judges that it has been selected and operates, while the memory device that has taken in 'bi' as the sign bit P operates because it has been selected. It will not work if it is not determined.

Note that the sign bit P is one of the so-called free bits among the bits that make up the memory address, that is, a bit that does not affect the memory capacity and does not affect any device in the system. It is sufficient to incorporate them into one, and it does not need to be the most significant of the empty bits as in the embodiment.

By introducing such a memory address,
The memory map seen from the processor side is as shown in Figure 4.

In this figure, among all the memory areas, numeral 5 indicates the memory area of the own system, and numeral 6 indicates the memory area of the other system.

Also, on this memory map, the symbol M. Using the memory address allocation described above, the address of the location indicated by -M4 is as follows.

Mo; An ~ Ao = ALL “0” M, ; An ~ A, , = A L “0” A, ~ A
o = ALL "l"M2; A, 1 = 1 A,, ~A, = ALL L "O°゛M3; A, 1 =
,I A n-H~A,,,=ALL "O"A, ~Ao
=ALL"1"M,;An~Ao=ALL"1" Next, the above-mentioned memory bus communication device 4 will be explained.

Each memory bus communication circuit 4x, 4Y has a system selection line 9, a code line 10, and an address strobe line 1 as lines through which signals output to the memory bus are passed.
1, a read/write line 12, an other system termination line 13, an own system termination line 14, and a data line (path shown) through which write data and read data flow.

A memory address modify circuit (hereinafter referred to as an address modify circuit) 17 is incorporated in the code line 10, and an address strobe modify circuit (hereinafter referred to as an address modify circuit) is incorporated in the address strobe line 11. (referred to as strobe modify circuit)1
It has a configuration that incorporates 8.

In each of the above-mentioned lines, the system selection line 9 is the active system/
When a signal indicating the standby system (ACT/SBY signal) is input, this circuit passes the signal to each control terminal on the lines 10 to 14 mentioned above to control the flow of signals on each line 10 to 14. .

The processor lx of both systems determines whether it is an active system or a standby system.
, ly, one system is the operational system (AC
T), the other side is always a standby system (100 BY).

Further, each of the memory bus communication circuits 4x+4y receives an ACT/SBY signal from its own processor.

The code line 10 is a circuit for passing the data of the code bit P in the memory address (hereinafter referred to as P data), and includes a signal path 10a for passing the P data without passing through the address modify circuit 17, and an address modify circuit. 17, and a signal path 10b through which P data flows.

The signal path 10a passes P data from the active side to the standby side only when the ACT signal enters the control terminals Oc and 10d on the path from the system selection line 9, and the SBY signal flows to the control terminals 10c and 10d. When entering, do not transmit P data.

The signal path 10b connects to the control terminal 9a of the system selection line 9.
If the signal inverted by
(in the case of a BY signal), the A'CT signal enters the control terminals toe and lof in the path, and the shoulder signal from the active side is passed through the address modify circuit 17 to the standby side as P data. .

The address modify circuit 17 receives the ACT/S'B'Y signal entering the system selection line 9 and the read/write signal.
A read/write signal (hereinafter referred to as an R/W signal) flowing through a line (hereinafter referred to as an R/W line) 12 is monitored.

Furthermore, when a read command is being output to the standby memory device, the P data ``BI'' that has entered the signal path 10b is inverted by the address modify circuit 17 and output as mid data 11011.
Activate the standby memory device on the output side.

Note that when the signal passed through the control terminal 9a indicates SBY, this path 10b does not flow P data.

The address strobe line 11 is a circuit that passes an address strobe signal (hereinafter referred to as an AS signal).
1 without going through the strobe modify circuit 18.
It includes a signal path 11a through which a signal flows, and a signal path 11b through which an AS signal flows through a strobe modify circuit 18.

The signal path 11a allows the AS signal to flow from the active system to the standby system only when the ACT signal is input from the system selection line 9 to the control terminals 11C and 11d on the path, and the SBY signal is input to the control terminal tlG+'lld. When this occurs, the A'S signal will not be sent.

Signal path 1.1. b indicates that when the signal inverted by the control terminal 9a of the system selection line 9 indicates ACT (that is, when the signal input from the own system's processor to the system selection line 9 is the SBY signal), the signal is routed. By entering the control terminals lie and llf in the middle, A is sent to the standby system via the strobe modify circuit 18 from the active system.
Send the S signal.

Here, the strobe modify circuit 18 is
The CT'/SBY signal, R/W signal, and P data are monitored, and only when a write command is received from the active system, or a read command is received from the active system to the standby system memory device. Applies certain modifications to the incoming shoulder signal and outputs it.

Here, certain modification means, for example, when a write command is output to the active memory bus, the AS signal issued to the active system so that the standby memory device also shows that a write command has been output. It means to modify.

Note that when the signal passed through the control terminal 9a indicates SBY, the AS signal does not flow through this path 11'b.

Further, the R/W line 12 is a circuit that sends an R/W signal indicating whether the command output to the memory bus is a read command or a write command.

This R/W line 12 is connected to the R/W line 12 via a control terminal 12a.
It includes a signal path 12b through which a W signal flows, and a signal path 12d through which an R/W signal flows through a control terminal 12C.

The signal path 12b operates when a signal enters the system selection circuit 9 from the processor or is ACT, and sends R from the active system to the standby system.
, /W times the signal.

The signal path 12d is activated when the signal input from the processor to the system selection circuit 9 is SBY, and the signal path 12d is activated to send R from the active system to the standby system.
/W signal is sent.

The other system end line 13 is a circuit for allowing the active system processor to take in the end signal output from the standby system memory device, and when the signal input to the system selection circuit 9 by the control terminal I3a is ACT, This signal is taken into the operational system.

The own system termination line 14 is a circuit for allowing the active system processor to take in the termination signal output from the memory device when it becomes standby. , sends a signal from the standby system to the active system.

MDSACKS is the end signal issued from the standby memory device.
The end signal issued from the active memory device is called a M signal.
It is called the DSA'CK signal.

The circuit configurations are set symmetrically between these memory path communication circuits 4X, 4Y, and these circuits 4
The connections between the x and 4Y lines are as follows.

In the case of lines 10 to 12, lines of the same type are connected to each other, and regarding line 13.14, the other system termination line 13 of one system is connected to the own system termination line of the other system.

The specific operation according to the above embodiment will be explained below.

(4) When the active processor device 1x writes data to its own memory device 2x, it is as follows.

Write commands and write data output to the active memory bus are sent to the standby memory bus via the R/W line I2 of the communication circuits 4x and -4Y and the data line of the illustrated path.

In addition, the P data output to the active memory bus 3x “
0'' passes through the path 10a on the code line 10 of the active communication circuit 4x, and passes through the path 1.0a on the code line 10 of the standby communication circuit 4Y. After passing through Ob, it is output to the standby system as 0''.

Therefore, when the active memory device 2X enters a writable state due to the P data "O" fetched from its own system's Memobus, the standby memory device 2Y also enters a writable state in the same write cycle. become.

Further, the AS signal output to the active memory bus 3x passes through a path 14a in the address strobe line 11 of the active communication circuit 4x, and passes through the standby communication circuit 4.
The signal passes through a path 11b in the address strobe line 11 of Y□, undergoes a certain modification by the strobe modify circuit 18 on the path 11b, and is output to the standby system.

Therefore, when the active memory device 2X writes write data using the AS signal fetched from its own memory bus, the standby memory device 2Y also writes write data to the standby memory bus communication circuit in the same write cycle. The same write data is written using the AS signal output by 4Y.

Therefore, according to this method, it is possible to write the same data to both the active and standby memory devices in the volite cycle, and it is possible to achieve matching of the contents of the duplexed memory in real time. .

Furthermore, even if system switching occurs due to some kind of failure in redundant fault training, land processor equipment, etc. that emphasize real-time, the content that was being operated in the old active system can be immediately continued.

Note that the active processor device 1x is the own memory device 2.
The timing of duplex memory copying when X is commanded to write data is as shown in FIG.

In the figure, 81 is an address signal, S is an R/W signal, S3 is an active system AS signal, S4 is a standby system AS signal, S5 is a write data★, S6 is an MDSACK signal, and S7 is an MDSAC signal.
The KS signal and Sll are response signals sensed by the active processor.

The active processor 1x is the memory device 2x of both systems.

The write operation is ended by receiving end signals s, , S7 from 2Y, respectively.

(2) When the active processor 1x reads data from its own memory device 2x, the process is as follows.

P data "'0" output to the active memory bus 3x
passes through the path 10a in the code line IO of the active communication circuit 4, and passes through the code line I of the standby communication circuit 4Y.
Inverted by passing through the path 10b at O, “
1°" and is output to the standby system.

Further, the A/NO signal output to the active memory bus 3x passes through a path 11a in the address strobe line 11 of the active communication circuit 4x, and passes through the standby communication circuit 4.
Path 1 in address strobe line 11 of Y
1b, but is invalidated by the strobe modify circuit 18 on path 11b.

Therefore, when a read command is issued to the active memory device, the standby system does not operate and data is read only from the active memory device.

(3) The active processor 1x is the standby memory device 2Y
When reading data from , the procedure is as follows.

The P data "1" outputted to the active memory bus 3x passes through the path 10a on the code line IO of the active communication circuit 4x, and is transferred to the code line 10 of the standby communication circuit 4Y.
is reversed by passing through the path 10b at
''' and is output to the standby system.

Further, the A/NO signal output to the active memory bus 3x passes through the path 11a in the address strobe line 11 of the active communication circuit 4x, and passes through the standby communication port 14.
Path 1 in address strobe line 11 of Y
lb, is subjected to a certain modification by the strobe modifying circuit 18 on the path 11b, and is output to the standby system.

Therefore, when a read command is issued from the active processor to the standby memory device, the active memory device does not operate due to the P data "1" output to its own system.
Data is read only from the standby memory device.

That is, in the case of a read operation, the memory devices of both systems are
Can be used alternatively.

[Effects of the Invention] As is clear from the above explanation, the duplex memory copy method according to the present invention incorporates a code bit into the memory address to distinguish between the active system and the other system, and furthermore, A memory bus communication device that interconnects the system and active memory buses is provided with a memory address modify circuit and an address strobe modify circuit.

When a write command is output to the active memory device, the memory address modify circuit is used to cause the standby memory device to take in the code bit data indicating the own system, and the address strobe・Using a modify circuit, certain modifications are made to the address strobe signal output to the active system, and the output is output to the standby system memory device to perform writing.

Therefore, when the active memory device writes data, the same data can be written to the standby memory device in the same write cycle, achieving matching of the contents of the redundant memory in real time. can do.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory bus communication device in an embodiment of the present invention, FIG. 2 is a block diagram of a data processing system to which the present invention is applied, and FIG. 3 is a configuration diagram of a memory address in the embodiment. , FIG. 4 is an explanatory diagram of the memory area on the memory map in the data processing system, and FIG.
The figure is a timing chart of duplex memory copying in one embodiment. 1x, IY... Processor, 2 XH2Y...
...Memory device, 3X, 3Y...Memory bus, 4...Memory bus communication device, 4x, 4y...
...Memory bus communication circuit, 5...Self system memory area, 6...Other system memory area, 9...
・System selection line, 10... Code line, 11・
...Address strobe line, 12...
・R/W line, 13... Other system end line, 14
.... Own system end line, 17.. Memory address modify circuit, 18.. Address strobe modify circuit. nononononononono

Claims (1)

[Claims] In a data processing system in which processors and memory devices are duplicated to constitute an active system and a standby system, in order to distinguish in advance whether the active system is the own system or the other system. The code bit of is incorporated into one of the free bits of the memory address, and the code bit is taken into each memory device during read/write processing, and the memory device selected by the sign bit is operated; The active and standby memory buses are connected to each other via a memory bus communication device, and this memory bus communication device has a function that uses the sign bit when a write command is output to the active memory bus. a memory address modifying circuit that operates a standby memory device using a memory bus, and an address that modifies the address strobe signal output from an active memory bus communication device and causes the standby memory device to operate the address strobe signal. - A redundant memory copy method characterized in that a strobe modify circuit is provided so that the contents written in the active memory device are also written in the standby memory device via the memory bus communication device.