JPH0625987B2 - Complex computer system - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a composite computer system including a shared memory device of a dual configuration shared by a plurality of computers.

[Technical Background of the Invention] As a means for constructing a complex computer system, sharing of main memory is known. For this sharing, a shared memory device is a device provided so that a plurality of computers can access it like its own main memory.

FIG. 2 shows a complex computer system in which the shared memory device 10 is shared by a plurality of computers 20-1 to 20-n. Shared memory device 10
In order to improve reliability, the memory is generally duplicated as shown in the figure, and is composed of two memory units 10a and 10b. The memory units 10a and 10b mainly include the memory 11
a, 11b, shared memory controllers 12a, 12b for controlling the memories 11a, 11b, shared memory buses 13a, 13b, computers 20-1 to 20
-n shared memory bus 13a, 13b (via memory 11a, 11b)
Shared memory ports 14a-1 to 14a-n, 14b-1 for connecting to
14b-n and console panels 15a, 15b for operating the memory units 10a, 10b. The shared memory controllers 12a and 12b are provided with duplication control circuits 16a and 16b. The duplication control circuits 16a and 16b are interconnected by a duplication control bus 17 for performing duplication control.
The duplication control circuits 16a and 16b perform duplication synchronization control via the duplication control bus 17 and copy control for matching the contents of the memories 11a and 11b.

[Problems of Background Art] In each of the memory units 10a and 10b of the shared memory device 10 having the duplex configuration shown in FIG. 2, the online state and the offline state are controlled by disconnection (offline) when an error occurs, or by an operator. It was generally performed by operating the console panels 15a, 15b by. Therefore, be sure to check the console panel 15a even when diagnosing one system unit.
(Or 15b) was required and it was complicated. Also, if a transient error occurs, it is possible to recover (restart) by initializing.
Since it was impossible to control from ~ 20-n, the operator had to intervene to restore the console panel 15a (or 15b) by initialization.

Therefore, instead of operating the console panel, the computer 20-1 ~
It is possible to control the memory units 10a and 10b of the shared memory device 10 independently and directly from 20-n. However, in order to realize this, the shared memory interfaces 24-1 to 24-n in the computers 20-1 to 20-n and the shared memory controller
Dedicated control signal lines for operation control are required between 12a and 12b. For this reason, the shared memory device 10 has many address signal lines, data information signal lines, control information signal lines, and signal lines, which causes mounting problems and is difficult to realize.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object thereof is to provide a composite computer system in which operation control from a computer to a duplicate shared memory device can be performed without preparing a dedicated control signal line. To provide.

[Summary of the Invention] According to the present invention, there is provided a complex computer system including a duplicated shared memory device shared by a plurality of computers. The dual shared memory device is composed of two independent sets of memory units. Each memory unit has a shared memory controller containing a microprocessor.
Both controllers are independent of each other without a duplication control circuit as in the conventional case. That is, in the present invention, the shared memory controller itself does not have the duplication control function. Then, the shared memory controller itself is not provided with a duplication control function, but the shared memory interface of each computer is controlled to control each shared memory controller of the two sets of memory units to perform duplication control. Two
A duplication control circuit is provided. This enables access in units of memory units.

Now, each shared memory controller has a built-in microprocessor as described above. This microprocessor is a C of each computer through a shared memory interface.
Can communicate with PU. Therefore, the CPU in each computer controls the operation of the corresponding memory unit via the shared memory controller by communicating with the microprocessor of each shared memory controller in the two sets of memory units via the shared memory interface. Is configured to.

[Embodiment of the Invention] FIG. 1A shows the configuration of a compound computer system according to an embodiment of the present invention. The system shown in FIG. 1A is composed of a duplicate shared memory device 30 and a plurality of computers 40-1 to 40-n sharing the shared memory device 30.

The shared memory device 30 includes two memory units 30a and 30b. The memory units 30a and 30b mainly include the memory 3
1a, 31b, shared memory controllers 32a, 32b, shared memory buses 33a, 33b connecting the memories 31a, 31b via the shared memory controllers 32a, 32b, and computers 40-1 to 40-n
To the shared memory buses 33a, 33b (via the memories 31a, 31b) via shared memory ports 34a-1 to 34a-n, 34b-1 to
It consists of 34b-n.

The computers 40-1 to 40-n mainly have CPUs 41-1 to 41-n and main memories 42-1 to 4 that are local memories of the CPUs 41-1 to 41-n.
42-n, system buses 43-1 to 43-n, and the same system bus
43-1 to 43-n (CPUs 41-1 to 41-n connected to) and shared memory ports 34a-1, 34b-1 to 34a- of shared memory device 30
n, 34b-n and interface lines 50a-1, 50b-1 to 50a-n,
Shared memory interface 44-1 connecting via 50b-n
It consists of ~ 44-n.

FIG. 1 (b) is a shared memory controller of FIG. 1 (a).
The structure of 32a is shown. The shared memory controller 32a includes a memory controller 61 that controls the memory 31a and a shared memory bus controller 62 that controls the shared memory bus 33a.
have. Further, the shared memory controller 32a is a microprocessor 63 that performs various services required by the controller 32a, and a microcomputer interface that enables the shared memory bus controller 62 to be controlled by connecting the microprocessor 63 to the shared memory bus 33a. Has 64. The microprocessor 63 includes a shared memory bus 33a, shared memory ports 34a-1 to 34a-n, and shared memory interfaces 44-1 to 40-1 to 40-n of the computers 40-1 to 40-n.
It communicates with the computers 40-1 to 40-n via 44-n. The configuration of the shared memory controller 32b is basically the same as the configuration of the shared memory controller 32a in FIG. 1 (b). Therefore, regarding the configuration of the shared memory controller 32b, if necessary, replace a with b in the above description and FIG. 1 (b).

FIG. 1 (c) shows the configuration of the shared memory interface 44-1 of FIG. 1 (a). Shared memory interface 44-1
Are shared memory ports 34a-1, 34b-1 of the shared memory device 30.
Port interfaces 71a and 71b for duplication corresponding to
And a system bus interface 72 corresponding to the system bus 43-1. Port interface 71a, 71
b and system bus interface 72 are internal bus 73
Interconnected by. A duplication control circuit 74 for performing duplication control is connected to the internal bus 73. The shared memory interface 44-1 is a dual control circuit.
A microprocessor 75 for controlling the 74, and a microcomputer interface for connecting the microprocessor 75 to the internal bus 73 to control the duplex control circuit 74.
Has 76. Shared memory interface 44-n
The shared memory interface 44-1 of FIG.
The configuration is basically the same. Therefore, regarding the configuration of the shared memory interface 44-n, if necessary,
Replace -1 with -n in the above description and Figure 1 (c).

As is clear from the above description, in this embodiment, no console panel is provided in the memory units 30a, 30b, and further, a duplicated control bus connecting the shared memory controllers 32a, 32b is provided. Note that it is not. In addition, the shared memory controllers 32a and 32b are provided with the shared memory controllers 12a and 12b shown in FIG.
Circuits corresponding to the duplex control circuits 16a and 16b are not provided. Then, as represented by the shared memory interface 44-1 shown in FIG. 1C, the duplication control circuit 74 is provided in each of the shared memory interfaces 44-1 to 44-n. Please be careful.

Next, the operation of the embodiment of the present invention will be described.

Duplication control Duplication control of the shared memory device 30 is performed by duplication selected (in the shared memory interface) of the shared memory interfaces 44-1 to 44-n of the computers 40-1 to 40-n. Control circuit 74
Controlled by. Now shared memory interface 44-1
It is assumed that the internal duplication control circuit 74 performs duplication control. In this case, the operation of the duplex control circuit 74 is stopped, activated, and controlled by a command from the CPU 41-1.
-1 and via the system bus interface 72.

Now, the duplication control circuit 74 is a duplication shared memory device.
30 (the memory units 30a and 30b thereof) are individually controlled. Therefore, the duplex control circuit 74 uses the internal bus 7
3, port interface 71a, 71b, interface 50a-
1, 50b-1, shared memory ports 34a-1, 34b-1 and shared memory bus 33a, 33b via any shared memory controller 3
Information is sent to 2a and 32b. Shared memory controller 32a,
32b is for the duplication control from the duplication control circuit 74,
The control result information is sent to the shared memory interface 44-1 of the computer 40-1. In this case, if the duplication is controlled synchronously, the shared memory controllers 32a and 32b notify the other shared memory controller to notify the shared memory buses 33a and 33a.
It is necessary to take cycle b. For this purpose, a special control signal must be provided between the controllers 32a and 32b. Therefore, in this embodiment, as described below,
The redundant shared memory device 30 is asynchronous.

First, in this embodiment, in order to make the shared memory device 30 asynchronous, in accessing the shared memory device 30,
Double write and single read control is applied. In accessing the memories 31a and 32b in the shared memory device 30, a memory in which both writing and reading are performed is called a master, and a memory in which only writing is performed is called a slave. With this definition, the master side access frequency (M) and the slave side access frequency (S) are as follows.

Master side access frequency (M) = W + R Slave side access frequency (S) = W However, W: Write frequency R; Read frequency Therefore, (M) 7 ≧ (S). Thus, in this embodiment, the duplex control circuit is
Applying the double write / single read method under the control of 74
By keeping the duplex access frequency (M) ≧ (S), the slave can follow the master even if the duplex control is asynchronous. However, the state of (M) ≦ (S) may temporarily occur due to the interrupt control. Therefore, the duplication control circuit 74 controls the access to the master side port by monitoring the buffer state on the slave side among the input / output buffers (not shown) built in the port interfaces 71a and 71b.

As described above, in this embodiment, by making the duplexing control asynchronous, it is possible to perform an arbitrary access in units of one system. The duplication control circuit 74 is controlled by CP
Shared memory controller as well as commands from U41-1
It is also performed by a command from 32a, 32b via the port interfaces 71a, 71b. As this command, for example, when an abnormality is detected in the shared memory controller 32a,
There is an offline request or the like issued from the microprocessor 63 of the controller 32a.

Operation control from computer -1 Memory unit connection / disconnection When the shared memory device 30 is maintained or when a failure occurs in the shared memory device 30, the memory unit in the shared memory device 30
It is necessary to disconnect the relevant unit from among 30a and 30b, and to perform an operation such as forced connection. In such cases, the calculator
In the case of 40-1 as an example, the command required for the shared memory interface 44-1 from the CPU 41-1 in the computer 40-1 is the system bus.
It is generated via 43-1. This command is transmitted to the microprocessor 75 via the system bus interface 72, the internal bus 73 and the microcomputer interface 76 of the shared memory interface 44-1. Microprocessor 75 is C
When the command from the PU 41-1 is an offline request or an online request, the specified unit of the shared memory device 30, for example, the shared memory controller 32a of the memory unit 30a, the port interface 71a, the interface line 50a-1,
The shared memory sends control information to that effect via the port 34a-1 and the shared memory bus 33a. The control information sent to the shared memory controller 32a is notified to the microprocessor 63 via the interface 64 in the controller 32a. As a result, the microprocessor 63 sends a disconnection or connection request to the shared memory bus controller 62 via the shared memory bus 33a. The shared memory bus controller 62 performs corresponding processing in response to a request from the microprocessor 63. As a result, if the disconnection request is issued, the disconnection of the memory unit 30a (here, the memory 31a
The access to the memory unit 30a is performed, and the self-diagnosis of the memory unit 30a (memory 31a of the memory unit 30a) becomes possible through the following forced connection. If the connection request (this request is issued when the memory unit 30a is determined to be normal as a result of self-diagnosis), the memory unit 30a
Is connected (here, the memory 31a is released from the access prohibited state).

When the memory unit 30a is disconnected (offline) by the above offline request, the CP
The U 41-1 requests the shared memory interface 44-1 to forcibly connect the corresponding unit 30a in order to self-diagnose (the memory 31a of) the memory unit 30a. This request is transmitted to the shared memory controller 32a of the corresponding unit 30a by the microprocessor 75 of the shared memory interface 44-1. This causes the shared memory controller 32a to
The memory unit 30a is forcibly connected only to the shared memory interface 44-1. As a result, the CPU 41-1 can access the memory unit 30a in the offline state, and the self-diagnosis of the unit 30a becomes possible.

As described above, in this embodiment, the connection and disconnection of an arbitrary memory unit, which was conventionally required to be performed by the operator operating the console panel, can be performed by the computers 40-1 to 40-4.
This can be done by notifying the request from the shared memory controller in the target unit of the shared memory device 30 from 40-n.
That is, the operation control of the shared memory device 30 can be performed from the computers 40-1 to 40-n according to the program. Therefore, the disconnection of the memory unit, the forced connection in this disconnected state, the self-diagnosis in this forced connection state, and the connection (return to the online state) according to this self-diagnosis result follow the programs 40-1 to 40-n. It can be done automatically by the command from.

-2 Initialization of memory unit When a failure occurs due to a transient error caused by disturbance or the like, for example, the CPU 41-1 of the computer 40-1 uses the shared memory interface 44 as in the case of the online request and the offline request described above. -1 (the microprocessor 75) to the corresponding unit of the shared memory device 30, for example the memory unit 30a
Issues a request to initialize (initialize). Shared memory interface 44-1 (of which microprocessor 75) is a C
The initialization request from the PU 41-1 is transmitted to the shared memory controller 32a in the corresponding unit 30a of the shared memory device 30. As a result, the microprocessor 63 of the shared memory controller 32a executes the initialization routine, and the memory unit 30a
(Memory 31a of) is initialized. When the shared memory controller 32a completes the initialization, it notifies the shared memory interface 44-1 of the computer 40-1 of the completion of the initialization. This completion notification is sent from the shared memory interface 44-1 to the CPU.
Passed to 41-1.

[Effect of the Invention] As described in detail above, according to the present invention, the operation control from the computer to the dual shared memory device can be performed without preparing a dedicated control signal line. Diagnosis, automatic restart based on this diagnosis result, restart by initialization when a transient error occurs, etc. can be realized.

[Brief description of drawings]

FIG. 1 (a) is a block diagram of a composite computer system according to an embodiment of the present invention, and FIG. 1 (b) is FIG. 1 (a).
A block diagram of the shared memory controller 32a shown in
FIG. 1 (c) is a block diagram of the shared memory interface 44-1 shown in FIG. 1 (a), and FIG. 2 is a block diagram of a conventional complex computer system. 30 ... Shared memory device, 30a, 30b ... Memory unit, 31a, 3
1b ... memory, 32,32b ... shared memory controller, 40-1 ...
40-n ... Computer, 41-1 to 41-n ... CPU, 44-1 to 44-n ... Shared memory interface, 63, 75 ... Microprocessor, 7
4 ... Duplication control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koji Shida 1-18-17 Nishishimbashi, Minato-ku, Tokyo Inside Toshiba Engineering Co., Ltd. (72) Hideji Takemoto 1-18 Nishishinbashi, Minato-ku, Tokyo No. 17 within Toshiba Engineering Co., Ltd. (72) Inventor Akihiko Oyama 1-18-17 Nishishimbashi, Minato-ku, Tokyo Within Toshiba Engineering Co., Ltd. (56) Reference JP-A-53-121429 (JP, A) JP-A-57-17066 (JP, A) JP-A-57-18094 (JP, A)

Claims (1)

[Claims] 1. A dual shared memory device comprising two independent sets of memory units having a shared memory controller with a built-in microprocessor, and a plurality of computers sharing the dual shared memory device. A shared memory interface for controlling each shared memory controller of a set of memory units to control the shared memory and connecting the computer to each of the two sets of memory units, and the shared memory A plurality of computers having a CPU that communicates with the microprocessors of the shared memory controllers in the two sets of memory units via an interface and controls the operation of the corresponding memory units via the shared memory controller; A computer system characterized by.