JPS57101958A - Memory address extension system - Google Patents

Memory address extension system

Info

Publication number
JPS57101958A
JPS57101958A JP55177648A JP17764880A JPS57101958A JP S57101958 A JPS57101958 A JP S57101958A JP 55177648 A JP55177648 A JP 55177648A JP 17764880 A JP17764880 A JP 17764880A JP S57101958 A JPS57101958 A JP S57101958A
Authority
JP
Japan
Prior art keywords
devices
address
mmc0
mmc1
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55177648A
Other languages
Japanese (ja)
Other versions
JPH0122653B2 (en
Inventor
Kazuhiko Goukon
Satoru Kuwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55177648A priority Critical patent/JPS57101958A/en
Publication of JPS57101958A publication Critical patent/JPS57101958A/en
Publication of JPH0122653B2 publication Critical patent/JPH0122653B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To extend an address, by providing an address extension indicating FF, setting this FF to an address extension indicating state, forming working and stand-by main storage devices to a double system, writing the same contents simultaneously by the common address, and making each storage device independent as necessary. CONSTITUTION:Storage control devices MMC0, MMC1 are connected to plural main storage devices MM0, MM1, and control devices CC0, CC1 are connected to the devices MMC0, MMC1 through a bus B, so that the same contents can be written by a common address in one working device MM0 and the other stand- by device MM1. To the respective exclusive OR gates EOR0, EOR1 connected to terminals AM of these devices CC0, CC1, address extension FFs MF0, MF1 are connected, and the devices MMC0, MMC1 are controlled by outputs of the gates EOR0, EOR1. In this state, the same contents are written in the devices MM0, MM1 by the same address as a double system, and also are written in each device MM0, MM1 independently by the FFs MF0, MM1 as necessary.
JP55177648A 1980-12-16 1980-12-16 Memory address extension system Granted JPS57101958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55177648A JPS57101958A (en) 1980-12-16 1980-12-16 Memory address extension system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55177648A JPS57101958A (en) 1980-12-16 1980-12-16 Memory address extension system

Publications (2)

Publication Number Publication Date
JPS57101958A true JPS57101958A (en) 1982-06-24
JPH0122653B2 JPH0122653B2 (en) 1989-04-27

Family

ID=16034660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55177648A Granted JPS57101958A (en) 1980-12-16 1980-12-16 Memory address extension system

Country Status (1)

Country Link
JP (1) JPS57101958A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61243548A (en) * 1985-04-22 1986-10-29 Nec Corp Data memory device
JPS62128094A (en) * 1985-11-28 1987-06-10 Nec Ic Microcomput Syst Ltd Microcomputer
JPS62237557A (en) * 1986-04-09 1987-10-17 Hitachi Ltd Duplex bus connection system
JPS643769A (en) * 1987-06-26 1989-01-09 Nippon Telegraph & Telephone Memory access system
JPH02108497A (en) * 1988-10-14 1990-04-20 Mitsubishi Metal Corp Uniform packing device for powder molding
JPH02199562A (en) * 1989-01-30 1990-08-07 Oki Electric Ind Co Ltd Duplicated memory copy system
JP2009175879A (en) * 2008-01-22 2009-08-06 Nec Corp Duplex system and memory copy method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61243548A (en) * 1985-04-22 1986-10-29 Nec Corp Data memory device
JPS62128094A (en) * 1985-11-28 1987-06-10 Nec Ic Microcomput Syst Ltd Microcomputer
JPS62237557A (en) * 1986-04-09 1987-10-17 Hitachi Ltd Duplex bus connection system
JPS643769A (en) * 1987-06-26 1989-01-09 Nippon Telegraph & Telephone Memory access system
JPH02108497A (en) * 1988-10-14 1990-04-20 Mitsubishi Metal Corp Uniform packing device for powder molding
JPH02199562A (en) * 1989-01-30 1990-08-07 Oki Electric Ind Co Ltd Duplicated memory copy system
JP2009175879A (en) * 2008-01-22 2009-08-06 Nec Corp Duplex system and memory copy method

Also Published As

Publication number Publication date
JPH0122653B2 (en) 1989-04-27

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