JP2009175879A - Duplex system and memory copy method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a duplex system for matching the contents of a main storage device under simple configuration and control and its memory copy method. <P>SOLUTION: This duplex system is characterized by providing write destination changing parts 113, 120 and 230 for performing write to a preliminary system main memory 240 without performing write to a current system main memory 140 in a write through operation. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a duplex system, and more particularly to a memory copy method for enabling processing to be continued when switching between an active system and a standby system.

  A communication device used for a communication service is required to have high reliability and cannot be stopped even for a moment. Therefore, a redundant configuration is adopted in this type of communication apparatus.

  In a redundant system employing a redundant configuration, in order to continue the process before and after switching from the active data processing module to the standby data processing module, the contents of the main storage device and cache memory of the active system module The contents of the main memory and the cache memory of the standby module must match.

  As a method of making the contents of the main storage device and the cache memory coincide with each other, there is a method of writing the same data to the main storage device of the standby module each time data is written to the main storage device of the active module ( For example, see Patent Document 1 or 2.)

JP-A 64-19438 JP 2001-92682 A

  The method of writing the same data to the main storage device of the standby module every time data is written to the main storage device of the active module has a problem that it takes time. Although the method for solving this problem is also described in Patent Document 1, there is another problem that a FIFO must be provided and the configuration and control become complicated.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a duplex system and a memory copy method thereof that can match the contents of a main storage device with a simple configuration and control.

  According to one aspect of the present invention, in the duplex system, the write destination changing means for writing to the standby main storage device without writing to the active main storage device during the write-through operation. A duplex system characterized in that is provided.

  According to another aspect of the present invention, in a memory copy method of a duplex system, a write-through operation can be performed on a standby main storage device without writing to the active main storage device. A memory copy method characterized in that writing is performed can be obtained.

  According to the present invention, the address conversion unit is provided, and in the write-through operation, writing is performed to the standby main storage device instead of the active main storage device. The contents of the active and standby main storage devices can be matched in a short time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, the principle of the present invention will be described.

  Generally, in a computer system, a cache memory that compensates for the difference in operating speed is provided between a processing unit and a main memory (main storage device). Data is written to the data cache memory, and simultaneously or later, the data written to the data cache memory is written to the main memory. A method of writing data to the main memory at the same time as writing data to the data cache memory is called write-through.

  In the redundant system, the same configuration is adopted in each of the active and standby modules. For each module, the data cache memory in the CPU is used when the processing unit writes and reads data to and from the main memory.

  Usually, data cache memory write-back or write-through for maintaining coherence between the data cache memory and the main memory is performed by writing data in the data cache memory to a corresponding address in the main memory.

  In contrast, in the present invention, only in the case of write-through, the data written in the active data cache memory is not written to the corresponding address of the active main memory, and the main memory of the standby (standby) module is not written. Write to the corresponding address. Coherence between the active data cache memory and the main memory is realized by writing back the data cache memory. As a result, the stored contents can be matched without performing the operation of copying the contents of the active main memory to the standby main memory.

  In order to realize such an operation, the duplex system of the present invention has a write destination changing unit that sends write-through data to the external bus side such as PCI and passes the data to the spare module side. The write destination changing unit, when detecting a write-through, an address changing unit that changes an address value output from the CPU to the outside to an address value indicating the external bus side such as PCI, and a PCI that restores the changed address to the original. An external bus interface connected to an external bus such as a bus, and an address decoder that distributes address signals according to address values are included.

  As described above, in the duplex system of the present invention, by using the write-through operation, the same result as the copy operation can be obtained, and the copy-dedicated operation becomes unnecessary.

  The present invention is applied to a redundant data processing module in a communication system that is a redundant data processing module and requires switching without interruption and switching process continuity.

  Next, a duplex system according to an embodiment of the present invention will be described.

  The duplex system of FIG. 1 has a pair of identically configured modules 100 and 200, and has a redundant configuration in which one is used as an active system (in operation) and the other is used as a standby system (standby).

  The module 100 includes a CPU device 110, an address decoder 120 that decodes an address signal output from the CPU device 110, a main memory 140 specified by the address decoder 120, and a PCI interface 130.

  The CPU device 110 also includes a processing unit 111, a data cache memory 112, and an address conversion unit 113 that converts an address signal output from the data cache memory 112. The address conversion unit 113 performs address conversion only at the time of write-through, and does not perform address conversion at other times.

  Similarly, the module 200 includes a CPU device 210, an address decoder 220 that decodes an address output from the CPU device 210, a main memory 240 specified by the address decoder 220, and a PCI interface 230.

  The CPU device 210 includes a processing unit 211, a data cache memory 212, and an address conversion unit 213 that converts an address signal output from the data cache memory 212. The address conversion unit 213 performs address conversion only at the time of write-through, and does not perform address conversion at other times.

  The module 100 and the module 200 are connected by a PCI bus via the PCI interfaces 130 and 230, and can transfer data to each other.

  Next, the operation of the duplex system in FIG. 1 will be described in detail with reference to FIGS. In the following, in order to simplify the description, it is assumed that the data cache memories 112 and 212 each have an area that can store two sets of addresses and data. In addition, specific numerical values of addresses and data are merely for convenience.

  First, in the state of FIG. 1, the module 100 is in operation and the module 200 is on standby. In this state, it is assumed that the processing unit 111 of the CPU device 110 issues a request to write the data “5482” at the address “03500”.

  As shown in FIG. 1, the data cache memory 112 searches the inside upon receiving a request from the processing unit 111, finds that the address “03500” exists, and determines that it is a cache hit. Then, the data cache memory 112 writes the data “5482” at the address “03500”. At the same time, the data cache memory 112 passes a request to write the data “5482” to the address “03500” to the address conversion unit 113 as a write-through operation.

  The address conversion unit 113 performs an address conversion operation at the time of write-through, and does not perform an address conversion operation at other times. That is, the address conversion unit 113 operates as an address conversion unit only during write-through. The address conversion operation is performed so that, for example, when the addresses of the main memories 140 and 240 are 0 to 9999, the converted address becomes a value outside the range. Here, it is assumed that +40000 processing is performed on the input address. As a result, as a write-through operation, the address conversion unit 113 that has received a request to write data “5482” to the address “03500” issues a request to write data “5482” to the address “43500”. Output to.

  The address decoder 120 accesses the main memory 140 or passes the request to the PCI interface 130 according to the input address. That is, the address decoder 120 functions as a distribution unit. Here, when the input address is 0 to 9999, the main memory 140 is accessed, and when the address is 40000 to 49999, the access request is delivered to the PCI interface 130.

  The PCI interface 130 sends the input access request to the PCI interface 230 of the module 200 via the PCI bus.

  The PCI interface 230 converts an address included in the access request from the module 100 into an internal address. That is, the PCI interface 230 functions as an address reverse conversion unit. Here, a process of -40000 is performed on the input address. Then, the PCI interface 230 outputs the result to the address decoder 220. As a result, an access request for writing “5482” data to the address “03500” issued by the module 100 is input to the address decoder 220 of the module 200.

  The address decoder 220 determines that the address “03500” is an address for the main memory 240 and passes this access request to the main memory 240. In this way, data “5482” is written to address “03500” in the main memory 240.

  As described above, the address conversion unit 113, the address decoder 120, and the PCI interface 230 function as a write destination changing unit.

  Next, it is assumed that the processing unit 111 of the CPU device 110 issues a request to write data “1357” at address “03200”.

  As shown in FIG. 2, the data cache memory 112 receives the request from the processing unit 111, searches the inside, finds that the address “03200” exists, and determines that it is a cache hit. Then, the data cache memory 112 writes the data “1357” at the address “03200”. At the same time, the data cache memory 112 passes a request to write the data “1357” to the address “03200” to the address conversion unit 113 as a write-through operation.

  The address conversion unit 113 performs a process of +40000 on the input address and outputs a request for writing the data “1357” to the address “43200” to the address decoder 120.

  Since the input address is “43200”, the address decoder 120 delivers the access request to the PCI interface 130.

  The PCI interface 130 sends the input access request to the PCI interface 230 of the module 200 via the PCI bus.

  The PCI interface 230 performs a process of −40000 on the address input from the module 100 and outputs the result to the address decoder 220. As a result, an access request to write “1357” data to the address “03200” issued by the module 100 is input to the address decoder 220 of the module 200.

  The address decoder 220 determines that the address “03200” is an address for the main memory 240 and passes this access request to the main memory 240. Thus, the data “1357” is written to the address “03200” in the main memory 240.

  When the operation of FIG. 2 is completed, the data cache memory 112 has used up two storage areas. In this state, it is assumed that the processing unit 111 of the CPU device 110 issues a request to write data “1642” at address “03800”.

  As shown in FIG. 3, the data cache memory 112 searches the inside for the address “03800” but cannot find it, but determines that there is a cache miss and no cache is available. Then, the data cache memory 112 writes back one of the data in the two storage areas to the corresponding address in the main memory 140 to make a space in the storage area. At this time, the processing unit 111 and the data cache memory 112 function as cache write-back means.

  Unlike the case of the write-through operation, the address conversion unit 113 does not perform the address conversion operation during the write-back operation. That is, an access request for writing “5482” to the address “03500” is passed from the CPU device 110 to the address decoder.

  The address decoder 120 determines that the address “03500” is an address for the main memory 140 and passes this access request to the main memory 140. As a result, data “5482” is written to address “03500” in the main memory 140. Thus, one free area is created in the data cache memory 112. Further, the data at addresses “03500” in the main memories 140 and 240 match.

  Subsequently, the processing of the request to write the data “1642” to the address “03800” previously output from the processing unit 111 of the CPU device 110 is resumed.

  As shown in FIG. 4, the address “03800” and the data “1642” are written in the free area of the cache memory 112 in response to a request to write the data “1642” to the address “03800”. At the same time, an access request is passed to the address conversion unit 113 by a write-through operation.

  The address conversion unit 113 performs +40000 processing on the address. As a result, an access request for writing “1642” to the address “43800” is passed from the CPU device 110 to the address decoder 120.

  The address decoder 120 determines that the address “43800” is an address for the PCI bus, and passes this access request to the PCI interface 130 without passing it to the main memory 140.

  The PCI interface 130 passes this access request to the PCI interface 230 of the waiting module 200 via the PCI bus.

  The PCI interface 230 performs a process of −40000 on the address input for internal address conversion, and passes it to the address decoder 220 as an access request for writing data “1642” at address “03800”.

  The address decoder 220 determines that the address “03800” is an address for the main memory 240 and passes this access request to the main memory 240. Thus, the data “1642” is written to the address “03800” of the main memory 240.

  Next, it is assumed that a read request at address “03200” is issued from the processing unit 111 of the CPU device 110. In this case, as shown in FIG. 5, the data cache memory 112 searches the inside, determines that there is a cache hit, and reads data “1357” from address “03200” of the data cache memory 112. In this access, the main memory 140 is not accessed, and the data cache memory 112 is read. Therefore, the processing unit 111 does not require any special processing time.

  Next, the operation when switching between the active system and the standby system between the modules 100 and 200 will be described.

  First, as shown in FIG. 6, the operating module 100 is switched to the standby state.

  More specifically, the processing unit 111 outputs a cache full write-back instruction for writing back all the stored contents of the data cache memory 112 to the main memory 140.

  The data cache memory 112 performs a process of writing back all data in the storage area to the main memory 140 in response to the cache full write back instruction. At this time, the processing unit 111 and the data cache memory 112 function as write-back means.

  The address conversion unit 113 does not perform address conversion because it is a write-back operation, and the address in the data cache memory 112 is passed from the CPU device 112 to the address decoder 120 as it is.

  The address decoder 120 passes the access request to the main memory 140 because the input address indicates the main memory 140. The main memory 140 writes the write-back data to the corresponding address in response to the access request.

  When the entire contents of the data cache memory 112 are written back to the main memory 140, the stored contents of the main memory 140 and the main memory 240 are completely identical. In addition, since the data cache memories 112 and 212 have a very small capacity compared to the main memories 140 and 240, the time for rewriting all the data in the data cache memories 112 and 212 is not particularly problematic.

  It should be noted that correct data is stored in the main memory 240 of the module 200 even before the cache 100 is completely written back. Therefore, the module 200 can be shifted to an operation operation at any time. However, if the module 200 is in operation, the writing to the main memory 140 by the write-through operation in the module 200 in the module 200 and the cache full write-back operation of the module 100 conflict. Therefore, the module 200 does not perform the operation operation until the cache full write-back operation of the data cache memory of the module 100 is completed.

  It is assumed that the module 200 is changed during operation after the cache full write-back operation of the module 100 is completed. After that, it is assumed that a request to write “3366” data to “03250” is output from the processing unit 211 of the CPU device 210.

  As shown in FIG. 7, the data cache memory 212 searches for the address “03250” and recognizes that there is an empty space in the cache although it is not a cache hit. Then, the data cache memory 212 writes the address “03250” and the data “3366” in association with each other in the free space. At the same time, the data cache memory 212 passes an access request to the address conversion unit 213 by a write-through operation.

  The address conversion unit 213 performs +40000 processing on the input address. As a result, an access request for writing “3366” to the address “43250” is passed from the CPU device 210 to the address decoder 220.

  The address decoder 220 determines that the address “43250” is an address for PCI, and passes this access request to the PCI interface 230 without passing it to the main memory 240.

  The PCI interface 230 passes this access request to the PCI interface 130 of the waiting module 100.

  The PCI interface 130 performs a process of −40000 on the address input for the internal address conversion. Then, the PCI interface 130 passes the address decoder 120 as an access for writing “3366” to the address “03250”.

  The address decoder 120 determines that the address “03250” is an address for the main memory 140 and passes this access to the main memory 140. The main memory 140 writes data “3366” at address “03250”.

  Next, it is assumed that a read request at address “03200” is issued from the processing unit 211 of the CPU device 210.

  As shown in FIG. 8, the data cache memory 212 searches the inside and determines that there is a cache miss because the address “03200” does not exist. Then, the data cache memory 212 passes a read request to the address conversion unit 213 to access the main memory 240.

  Since this read request is not a write-through operation, the address conversion unit 213 does not perform address conversion. As a result, a read access request at address “03200” is passed from the CPU device 210 to the address decoder 220.

  The address decoder 220 determines that the address “03200” is an address for the main memory 240 and passes this access request to the main memory 240. The main memory 240 returns the data “1357” stored at the address “03200” as read data.

  The read data “1357” is transferred to the processing unit 211 and written to the data cache memory 212 at the same time.

  As described above, in the duplex system according to the present embodiment, the write data of the operating module is copied to the waiting module in real time by converting the address of the write data only during the write-through operation of the data cache memory. The As a result, after the module is switched, the module that is in operation immediately becomes ready for operation. In addition, the data copy operation during data write of the operating module does not affect the processing capability. In other words, in this redundant system, in the write operation of the CPU, the cache operation is possible even though the write data is copied to another module for each write, so the memory access time is not sacrificed. A copy operation can be performed.

  In addition, the duplex system according to the present embodiment can be realized only by adding an address conversion unit to the related duplex system, and since this address conversion unit can be included in the CPU device, the cost is not increased. Can be produced.

  Furthermore, since access is controlled by address conversion, if the address conversion unit is provided in the CPU device, it can be realized without adding a new terminal to the CPU device, so there is almost no increase in the cost of the CPU device.

  Although the present invention has been described in detail according to one embodiment, the present invention is not limited to the above embodiment.

  For example, in the above embodiment, two modules are connected by a PCI bus and a PCI interface, but other buses and / or interfaces, such as RIO (rapid IO) or a CPU bus can also be used.

  Further, in the address decoder, the data copy destination may be divided according to the address by finely decoding the address.

  Further, the PCI interface and the address decoder may be taken into the CPU device, and the PCI interface terminal and the main memory terminal may be output from the CPU device.

  Furthermore, when a data write operation is performed in a waiting module, the waiting CPU device prohibits the data cache memory so that data is not written from the waiting module to the operating module through the PCI bus. It may be in a state. Alternatively, the data cache memory mode may be set to write-through prohibition.

It is a block diagram for demonstrating a structure and operation | movement of the duplex system which concerns on one embodiment of this invention. It is a block diagram for demonstrating operation | movement of the duplex system of FIG. It is a block diagram for demonstrating operation | movement of the duplex system of FIG. It is a block diagram for demonstrating operation | movement of the duplex system of FIG. It is a block diagram for demonstrating operation | movement of the duplex system of FIG. It is a block diagram for demonstrating operation | movement of the duplex system of FIG. It is a block diagram for demonstrating operation | movement of the duplex system of FIG. It is a block diagram for demonstrating operation | movement of the duplex system of FIG.

Explanation of symbols

100, 200 Module 110, 210 CPU device 111, 211 Processing unit 112, 212 Data cache memory 113, 213 Address conversion unit 120, 220 Address decoder 130, 230 PCI interface 140, 240 Main memory

Claims (10)

  In a duplex system, there is a duplex feature characterized by providing write destination change means for writing to the standby main storage device without writing to the active main storage device during the write-through operation. system. The duplex system according to claim 1,
The write destination changing means is
Address conversion means for performing a predetermined conversion on the write destination address only during the write-through operation and outputting a converted address, and otherwise outputting an untranslated address;
Distribution means for outputting the converted address to an external bus connecting the active system and the standby system, and outputting the untranslated address to the main memory device of the active system;
Address reverse conversion means for reversely converting the translated address from the external bus;
A duplex system characterized by including: The duplex system according to claim 2,
The duplex system, wherein the address conversion means is an address conversion unit provided in a CPU device. The duplex system according to claim 1,
A duplex system comprising write-back means for performing cache write-back when a cache miss occurs. The duplex system according to claim 1,
A duplex system comprising a write-back means for performing cache write-back when switching between the active system and the standby system.   In a memory copy method of a duplex system, a memory is characterized in that, during a write-through operation, a write is made to a standby main storage device without writing to the active main storage device. Copy method. The memory copy method according to claim 6,
Performing a predetermined conversion on the write destination address only during the write-through operation and outputting the converted address; otherwise, outputting the unconverted address;
Outputting the translated address to an external bus connecting the active system and the standby system, and outputting the untranslated address to the main memory device of the active system;
Reverse-converting the translated address from the external bus;
A memory copy method comprising: The memory copy method according to claim 7,
A memory copy method, wherein a predetermined conversion is performed on the write destination address in a CPU device. The memory copy method according to claim 6,
A memory copy method comprising a step of performing cache write-back upon a cache miss. The memory copy method according to claim 6,
A memory copy method comprising a step of performing cache write-back when switching between an active system and a standby system.

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