JP2000181738A - Duplex system and memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To match the content of the cache memory of an act system with the contents of main memories in two systems and to easily switch systems in the duplex system of a zero system and a one system, containing processors having the cache memories and in a memory control method. SOLUTION: In the duplex system of a zero system and a one system containing processors 1 and 11 having cache memories 2 and 12, cache memory control circuits 9 and 19 reading the contents of cache memories 2 and 12 issuing coherent read cycles for reading the contents of he cache memories 2 and 12 and reading them in main memories 4 and 14 with periodical starting or starting by an urgent control signal by a power cut and the detection of processor runaway are connected to local buses 7 and 17. Bus control circuits 5 and 15 preferentially give the use permission of local buses 7 and 17 with the urgent control signals, the contents of the cache memories are written into the main memories, and they are written into the main memories of a mate system through a cross bus 10. Then, the contents of the main memories 4 and 14 of the two systems are matched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a dual system in which a system including a processor having a cache memory is duplicated, and a memory control method. One of the duplicated systems is used as the act system and the other as the standby system, so that the contents of the main memory of both systems are controlled so that they match, and in the event of a failure in the act system, the system is switched to the standby system to continue processing. the system,
Data transmission systems are also employed in various systems such as switching systems. It is known that a cache memory is provided in such a duplex system to speed up processing. There is a demand for further improving the reliability of the duplex system provided with the cache memory.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory view of a conventional example, and shows a main part of a duplex system of a system 0 and a system 1;
41 and 51 are processors (MPU), 42 and 52 are cache memories (CM), 43 and 53 are memory control circuits (MMC), 44 and 54 are main memories (MM),
5 and 55 are bus control circuits (BA), 46 and 56 are input / output control devices (IOC), 47 and 57 are local buses, 60
Indicates an intersection bus.

The system 0 and the system 1 have the same configuration, and if one is an act system, the other is a standby system. Processor (MPU) 41,
51 are connected to memory control circuits (MMC) 43 and 53 via local buses 47 and 57, respectively.
Main memories (MM) 44 and 54 are connected to 3 and 53, respectively. The bus control circuits (BA) 45 and 55 have a configuration in which the right of use is given by contention control of the use request of the local buses 47 and 57. Also 0 system and 1
The memory control circuits 43 and 53 with the system are connected by a cross bus 60.

In a redundant system, when processing is switched from an act system to a standby system,
It is necessary that the contents of the main memories 44 and 54 match. Therefore, for example, when writing data to the main memory 33 by a processor or DMA (direct memory access) to the 0-system main memory 44, the local bus 47 is occupied by the control of the bus control circuit 45. The write address and the write data are transferred to the memory control circuit 43, the data is written from the memory control circuit 43 to the main memory 44, and the write address and the write data are crossed from the memory control circuit 43. The data is transferred to the memory control circuit 53 via the bus 60 and the memory control circuit 5
3 is to write data to the main memory 54.

As shown in the figure, the cache memory (C
M; Cache Memories) 42 and 52 are provided, and the processors 41 and 51 generally access the cache memories 42 and 52 to increase the processing speed. Various control methods for the cache memories 42 and 52 and the main memories 44 and 54 have already been proposed, and for example, a write-through method and a copy-back method are known.

In either system, when data is read from the main memories 44, 54, if the cache memory 42, 52 is hit, the data is read without accessing the main memories 44, 54, thereby obtaining the main memory. 4
It can be faster than accessing 4,54. When writing data, the write-through method uses the cache memory 4
The data is also written to the main memories 44 and 54 together with the main memories 44 and 54. In this case, the data is also written to the main memories of the other systems, so that the main memories 44 and 54 of both the systems are written. Content can be matched.

In the copy-back method, data is written only in the cache memories 42 and 52.
Since the local buses 47 and 57 are not used, the processing speed can be increased as compared with the write-through system. When writing the data in the cache memories 42 and 52 to the main memories 44 and 54, the data in the main memories 44 and 54 of both systems are also made to coincide with each other.

In a duplex system, a first-in first-out memory (FIFO) is provided in a system 0 and a system 1 together with a cache memory, and data to be written in the cache memory is stored in the F-system.
Write to the FIFO at the same time or via the cache memory, write data from this FIFO to the main memory,
There is known a method in which the drawback of the write-through method is improved (for example, see Japanese Patent Application Laid-Open No. Sho 64-19438).

In a multiprocessor system in which each processor has a cache memory, there is also known a configuration in which, when a processor issues a specific instruction, a coherency maintaining operation is performed on a shared data block (for example, a configuration is known). And JP-A-9-62580).

[0010]

In a redundant system provided with a cache memory, by matching the contents of the main memory between the act system and the standby system, the processing can be taken over from the act system to the standby system. . However, when the write-through method is applied, since data is written to the cache memory as well as to the main memory, local bus contention processing, access processing to the main memory, data transfer to another system, etc. It is not easy to increase the speed as compared with the copy-back method.

Therefore, it is conceivable to apply a copy back method. In this case, in real time, the contents of the act-based cache memory and the contents of the standby-based main memory do not match. Therefore, when the processing is switched from the act-based to the standby-based system, the act-based cache memory is controlled by the program control. The contents of the main memory of both systems are matched by sweeping out the contents of the cache memory of the system and writing to the main memory of the local system, and also writing to the memory of the standby system. Will switch.

However, if a failure occurs in which the contents of the cache memory cannot be flushed due to a power-off of the act system or a runaway of the processor of the act system, the contents of the main memories of both systems match. But,
This means that the contents of the cache memory of the act system cannot be taken over to the standby system. Therefore, there is a problem that normal processing cannot be continued.

Further, in the conventional duplicated system provided with the cache memory and the FIFO, the configuration is equivalent to a configuration in which the cache memory is duplicated, so that the cost is increased and the power supply is cut off as described above. For runaway, data cannot be transferred from the act FIFO to the standby main memory, so that there is a problem that normal processing cannot be continued. An object of the present invention is to make the contents of the act-based cache memory and the contents of the standby-based memory coincide with each other based on a copy-back method as a basic method.

[0014]

The dual system according to the present invention comprises: (1) processors (MPU) 1, 11 having cache memories (CM) 2, 12;
Bus control circuits (BA) 5 and 15 for performing contention control of the local buses 7 and 17 to which the local buses 11 are connected;
7 including memory control circuits (MMC) 3, 13 connected to the main memory 7 and main memories (MM) 4, 14 for writing and reading data by the memory control circuits 3, 13.
A redundant system having a system system and a system 1 system, in which memory control circuits 3 and 13 are connected by a cross bus 10, and connected to local buses 7 and 17 to periodically store the contents of cache memories 2 and 12. , And a cache memory control circuit (CMC) 9, 19 for issuing a coherent read cycle for writing data into the main memories 4, 14.

(2) Cache memory control circuits 9 and 1
Reference numeral 9 denotes an emergency control signal based on detection of power cutoff or processor runaway by the emergency processing circuits (EMAs) 8 and 18,
A configuration is provided in which a request to use the local buses 7 and 17 is sent to the bus control circuits 5 and 15, and a data request for the cache memories 2 and 12 is made to the processors 1 and 11.

(3) Cache memory control circuits 9 and 1
No. 9 can have a configuration in which, when a coherent read cycle is issued, a memory area related to both the act system and the standby system is set, and data is transferred for the set memory area.

(4) The bus control circuits 5 and 15 may have a configuration for giving permission to use the local buses 7 and 17 preferentially based on the emergency control signals from the emergency processing circuits 8 and 18.

Further, the memory control method of the present invention comprises: (5) processors 1, 11 having cache memories 2, 12;
Local buses 7, 1 connected to the processors 1, 11
Bus control circuits 5 and 15 for competing control of the memory 7, memory control circuits 3 and 13 connected to the local buses 7 and 17, and main memories 4 and 14 for writing and reading data by the memory control circuits 3 and 13. A memory control method in a redundant system in which the memory control circuits 3 and 13 of the 0-system and the 1-system including
, A coherent read cycle for periodically writing the contents of the cache memories 2 and 12 to the main memories 4 and 14 is issued, and the contents of the main memories 4 and 14 of the system 0 and the system 1 are matched. .

(6) The local buses 7 and 17 are preferentially used by the emergency control signals from the emergency processing circuits 8 and 18 to execute a coherent read cycle, and the main memory of the system 0 and the system 1 4 and 14 are matched.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of an embodiment of the present invention.
Is a cache memory (CM), 3, 13 are memory control circuits (MMC), 4, 14 are main memories (MM), 5,
15 is a bus control circuit (BA), 6 and 16 are input / output control devices (IOC), 7 and 17 are local buses, 10 is an intersection bus, 8 and 18 are emergency processing circuits (EMA), and 9 and 19 are cache memories. 1 shows a control circuit (CMC).

The 0-system and the 1-system have the same configuration. The local buses 7 and 17 have processors 1 and 11 having cache memories 2 and 12, respectively.
Memory control circuits 3, 1 for controlling main memories 4, 14
3, various input / output control devices 6 and 16, cache memory control circuits 9 and 19, and bus control circuits 5 and 15 are connected. The bus control circuits 5 and 15 perform contention control for the bus use request and give exclusive use of the bus. Also, an intersection bus 10 is provided between the memory control circuits 3 and 13.
To transfer data between the 0 system and the 1 system, and to make the contents of the main memories 4 and 14 of both systems coincide.

The emergency processing circuits 8 and 18 are connected to the bus control circuits 8 and 18 and the cache memory control circuits 9 and 1 by detecting failures such as power-off detection and runaway detection of the processors 1 and 11, respectively.
9 to add an emergency control signal. Although not shown, the system switching process is started by adding an emergency control signal to the mate system by detecting a failure.

The processors 1 and 11 read and write data to and from the cache memories 2 and 12 by a copy-back method. The cache memory control circuits 9 and 19 are provided with a periodic or emergency processing circuit 8. , 18
The emergency control signal from the cache memories 2 and 12
And a function of sending a control signal for writing data from the cache memories 2 and 12 to the main memories 4 and 14 to the memory control circuits 3 and 13. That is, it has a function of issuing a coherent read cycle. Therefore, when the contents of the cache memories 2 and 12 are updated, after a certain period, the main memories 4 and 12 are updated.
14 are written to the contents of the cache memory of the act system and the main memories 4 and 14 of both systems.
Is matched. Further, the bus control circuits 5 and 15 have a function of giving priority to the local buses 7 and 17 for data transfer from the cache memories 2 and 12 by an emergency control signal from the emergency processing circuits 9 and 19. I have.

FIG. 2 is an explanatory view of a main part of a cache memory control circuit according to an embodiment of the present invention. Reference numeral 21 denotes a bus interface control unit, 22 denotes an address counter, 23 denotes a target address control register, and 24 denotes a timer. The cache memory control circuits (CMC) 9, 19 are connected to local buses 7, 17, as shown in FIG.

The timer 24 is set so as to output a start-up signal every period that does not adversely affect the usage status of the local buses 7 and 17. A coherent read cycle is issued by a dynamic start signal or an emergency control signal from the emergency processing circuits (EMAs) 8 and 18. The address counter 22 stores the cache memory 2,
Generate 12 addresses.

The target address control register 23 is a register for setting an address range at the time of a coherent cycle.
The area in which the contents of,,,,,, 常 に, 常 に,, 常 に, 常 に, 常 に, 常 に, 常 に, 常 に, 常 に, 常 に, 常 に, 常 に, で は, で は, で は, に わ た る, で は, デ ー タ, デ ー タ, デ ー タ, デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ デ ー タ 処理 デ ー タ デ ー タ デ ー タ 領域 デ ー タ 処理 デ ー タ 処理, 例 え ば 領域 プ ロ グ ラ ム デ ー タ デ ー タ サ イ ク ル 処理 サ イ ク ル.

FIG. 3 is an explanatory diagram of a data request sequence according to the embodiment of the present invention, in which BA, CMC, MPU, MM
C and MM are bus control circuits (BA) 5, 1 in FIG.
5, cache memory control circuits (CMC) 9, 19, processors (MPU) 1, 11, memory control circuit (MM
C) 3, 13 and main memories (MM) 4, 14;
The case of hit and the case of non-hit for the Kish memory will be described.

The cache memory control circuit (CMC) 9,
Reference numeral 19 sends a bus request to the bus control circuit BA by a periodic start signal from the timer 24 or an emergency control signal from the emergency processing circuits (EMAs) 8 and 18 based on detection of power-off.

The bus control circuit BA preferentially gives permission to use the local bus in response to a bus request from the cache memory control circuit CMC. By permitting use of the local buses 7, 17, the cache memory control circuit CMC issues a coherent read cycle CR to an address defined as a memory space. Processor MP
U outputs a memory inhibit signal MMINH when an address in the coherent read cycle CR hits the cache memories (CM) 2 and 12;
The data in the cache memories 2 and 12 are transferred to the local bus 7 and
17 on.

The memory control circuit MMC prohibits access to the main memory MM by the memory inhibit signal MMINH, writes data from the cache memories 2 and 12 on the local buses 7 and 17 into the main memory MM, and writes the data at that time. Of the write address and the write data, and a cross bus 10
To transfer through. Mate memory control circuit MMC
Writes the data transferred via the cross bus 10 into the main memory MM, whereby the contents of the cache memories 2 and 12 are stored in the main memory (MM) of both systems.
4, 14 will be written. Memory control circuit M
When the data writing to the main memory MM is completed, the MC sends an end signal to the bus control circuit BA, and ends the coherent read cycle.

The above operation is shown as a cache hit, and the coherent read cycle CR
Of the cache memory (CM) 2,
When the cache memory 12 does not hit, the processor MPU does not read data from the cache memory CM because the content of the main memory MM is updated according to the content of the cache memory, as shown as a non-cache hit. The memory control circuit MMC is a bus control circuit B
A is sent to A to end the coherent read cycle.

Therefore, the contents of the main memory MM are periodically updated in accordance with the contents of the cache memory CM, and the contents of the main memories MM of both systems are controlled so as to be identical. Can be. Also, in the case of emergency control such as power-off, the contents of the cache memory can be written to the main memory MM and the mate main memory MM by preferential use of the local bus. Switching can be easily performed.

The 0-system and the 1-system can also have a multiprocessor configuration. In this case, a cache memory CM is provided for the multiprocessor MPU, and a cache memory control is provided for each cache memory CM. A circuit CMC is provided and connected to a local bus, and coherent read cycles are issued at different timings to the same local bus, respectively.
By writing the updated data to the main memory MM, the contents of the main memories MM of both systems can be matched even in a redundant system with a multiprocessor configuration, and the system can be easily switched even when a failure occurs. Can be done.

[0034]

As described above, the present invention relates to a processor (MP) having cache memories (CMs) 2 and 12.
U) The present invention relates to a redundant system composed of a system 0 and a system 1 including systems 1 and 11, and a memory control method therefor. The contents of the cache memories 2 and 12 are periodically read out and stored in the main memories (MM) 4 and 14. Cache memory control circuits (CMCs) 9 and 19 for issuing a coherent read cycle to be written are connected to local buses 7 and 17 and cache memories 2 and 1 in a copy-back system.
2 and the contents of the main memories 4 and 14 so as to match each other at regular intervals, and an emergency processing circuit (EMA).
When a power-down or a runaway of the processor is detected by 8 or 18, a coherent read cycle is executed by preferentially using the local buses 7 and 17, and the contents of the cache memory are taken over from the act system to the standby system. Can be written to the main memories 4 and 14.

The memory area in that case is stored in the target address control register 2 of the cache memory control circuits 9 and 19.
3 (see FIG. 2) and the like, it is possible to transfer only the data necessary for system switching, and it is also possible to omit unnecessary processing.

Therefore, even in the copy-back method, after updating the contents of the act-based cache memory, the updated contents can be written to the main memory at least after a certain period of time. Even if the system goes down, the standby system can resume processing using the contents of the main memory, and has the advantage of greatly improving the reliability of the system.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a cache memory control circuit according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a data request sequence according to the embodiment of this invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1,11 Processor (MPU) 2,12 Cache memory (CM) 3,13 Memory control circuit (MMC) 4,14 Main memory (MM) 5,15 Bus control circuit (BA) 6,16 I / O controller (IOC) ) 7,17 Local bus 8,18 Emergency processing circuit (EMA) 9,19 Cache memory control circuit (CMC) 10 Cross bus

Claims (6)

[Claims] 1. A processor having a cache memory, a bus control circuit for controlling competition of a local bus connected to the processor, a memory control circuit connected to the local bus, and writing and reading of data by the memory control circuit In a redundant system having a 0-system and a 1-system including a main memory for performing the following operations, the memory control circuits are connected to each other by a cross bus. A redundant system comprising a cache memory control circuit for issuing a coherent read cycle for reading out contents and writing the read out contents to the main memory. 2. The cache memory control circuit sends a local bus use request to the bus control circuit in response to an emergency control signal based on detection of a power failure by an emergency processing circuit or a runaway of a processor, and sends the request to the processor. 2. The duplex system according to claim 1, further comprising a configuration for requesting data from a cache memory. 3. The cache memory control circuit sets a memory area related to both an act system and a standby system when the coherent read cycle is issued, and transfers data for the set memory area. The duplex system according to claim 1, further comprising a configuration. 4. The bus control circuit according to claim 1, wherein said bus control circuit is configured to give priority to use of a local bus based on an emergency control signal from said emergency processing circuit.
The duplex system according to any one of claims 1 to 3. 5. A processor having a cache memory, a bus control circuit for controlling competition of a local bus connected to the processor, a memory control circuit connected to the local bus, and writing and reading of data by the memory control circuit. A memory control method in a duplicated system in which the memory control circuits of the 0-system and the 1-system including a main memory for performing A memory control method, comprising: issuing a coherent read cycle for writing the contents of a memory to the main memory, and matching the contents of the main memories of the 0-system and the 1-system. 6. The coherent read cycle is executed by preferentially using the local bus in response to an emergency control signal from the emergency processing circuit, and the contents of the main memory of the 0-system and the 1-system are stored. 6. The method according to claim 5, further comprising the step of matching.