JPH0816475A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity of a cache memory, to lower the price of the system, and to speed up the operation by making a request snoop on a common bus by using cache tag information that a bus bridge has. CONSTITUTION:A CPU 101 sends a common read(CR) request having the address of a local memory 105 to a cache memory 103 and if a cache mishit is made, a CR request is sent from the cache memory 103 to a local common bus 106. The bus bridge 107 retrieves bus tag information 113 corresponding to the CPU 102 by a tag snooping means 111 and outputs a snoop request signal 117 for a connection with the CPU 102 and a memory inhibition signal 118 for a connection with the local memory 105 according to the retrieval result, thereby holding consistency. Consequently, tag duplication on the cache memory side can be eliminated, the hardware quantity of the cache memory is reduced, and the hardware is simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system that uses a shared bus to maintain data consistency.

[0002]

2. Description of the Related Art Multiprocessor systems that ensure data consistency by bus snooping are well known. In a system using such a method, the cache memory connected to the bus at the time when a request is issued to the bus inspects each tag information, and if it has the latest data for the request, the memory Assert the memory inhibit signal to inhibit the reading of data from. This guarantees that the latest data is always returned. Examples of buses that use such technology include the SPARC MBus. SPARC MBus
For details of the document SPARC MBus Interface Specific
ation, SPARC International.

FIG. 6 shows an example of the configuration of a distributed shared memory multiprocessor system using this. When the cache memory issues a coherent read (CR) request to the local shared bus, the cache memory searches the duplicated tag information to see if it has the latest data for the request. As a result, if it has the latest data, the memory inhibit signal (MIH) is asserted, the operation of the memory is suppressed, and the latest data is supplied to maintain consistency.

If this search is faster than the data read from the memory, there is no problem, but if it is slow, it is necessary to wait for the read from the memory, which causes a drop in performance. Has a duplicated tag for snoops from
Therefore, there has been a problem that the amount of hardware and complexity increase.

On the other hand, the cache memory invalidation processing method in a hierarchical bus system such as a multiprocessor system has the following technical background. In computer systems, modules such as processors, memory, and I / O devices are connected by a bus. To exchange data between these modules, a module becomes the bus master and issues bus commands such as read / write to the bus.
(Called slave module) outputs a response signal.

For example, if the processor module is a memory
When reading data from the module, the processor issues a read instruction on the bus. The memory module informs the processor that the data is ready by reading the data of interest from the memory and outputting it to the bus and outputting a response signal. The processor sees this signal and knows that data is output to the bus, and takes in the data on the bus.

In a system such as a multiprocessor system having multiple modules with cache memory for storing temporary copies of memory, when multiple modules share the same data, one of the modules may share this data. When rewriting the existing data, the invalidation command is issued to the bus to invalidate the data in the cache memory of another module. At this time, it is assumed that the invalidation processing is accepted when another module that performs the invalidation processing by the invalidation instruction becomes ready to receive the next bus instruction. Therefore, the response signal is invalid for all modules. It is output when the processing of the conversion instruction is completed.

One of the reasons is prevention of simultaneous update. Memory is often updated based on the previous value, but in a multiprocessor system, if two or more processors fetch one value, update each, and write them one after another, the data will be written later. The result of performing is not based on the previously written value, which causes inconvenience. For example, test-and-set instruction or swap
Read and write commands, etc. with one command,
In the meantime, with spin lock, which uses the property that reading / writing of other processors does not enter, those instructions should end only after the invalidation processing accompanying writing has been completed in all processors. Otherwise, two or more processors acquire the unlocked state copied on the cache, and exclusive control cannot be realized. The cache that has completed the invalidation process newly obtains the updated value, and therefore performs the process based on the immediately preceding value to correctly implement the exclusive control.

Another reason is that the cache is managed in units of cache lines larger than the access unit of the processor (an integral multiple of the access unit). When access to update another access unit of the same cache line is executed simultaneously by two or more processors, the invalidation process is not performed completely because both cache lines hold the values before update. Then, there is a problem in that the content that was previously acquired by acquiring the bus is overwritten by subsequent access, resulting in a phenomenon as if it were evaporated.

For this reason, writing is generally designed to be completed after the invalidation processing is completed in all caches, but the invalidation processing requires a relatively long time, There was a problem that the performance of the entire system was unavoidable.

The method of outputting the invalidation response signal is as follows: 1. The maximum time for invalidation processing is determined in advance, and one module outputs the response signal as a representative. 2. Each module accepts the invalidation request. Method to output each invalidation response signal at each point, 3. Until each module receives invalidation request op
There is a method to keep asserting the signal of en drain and to know that the entire invalidation is completed according to the principle of wired OR.

The completion time of the invalidation process is significantly increased when using a hierarchical bus system. A hierarchical bus system is a system in which multiple modules are connected to one bus described above (hereinafter referred to as a local bus) and connected by a bus called a global bus.
(Figure 7). Each local bus is connected to the global bus via a module called a bus bridge.

The operation in the conventional method when an invalidating instruction is executed in such a hierarchical bus system is described in the cache memory (3) and the cache memory (6).
The operation when the processor (7) rewrites the address data while the address data is stored will be described.

1. First, the processor (7) is a local bus
Issue an invalidation command for address 1000 in (1). 2. The processor (8) and the bus bridge (8) see the invalidation instruction and assert the invalidation processing in-progress signal (15).

3. Processor (8) is in cache memory
After confirming that there is no data at address 1000, the assertion of the invalidation processing in progress signal (15) is stopped. However, the bus bridge (11) keeps asserting.

4. The bus bridge (11) issues a request to use the global bus (13). 5. When the bus bridge (11) gets the right to use the global bus (13), it issues an invalidation instruction to the global bus (13) while keeping the invalidation processing in progress signal (15) asserted. To do. The bus bridge (11) acquired the right to use the global bus (13) before the bus bridge (11) acquired the right to use the global bus (13), and the bus instruction for the data at the same address was issued. Case, Bus Bridge (11)
Returns a re-execution response to the invalidation instruction issued by the processor (7), completes the invalidation instruction on the local bus (1) once, and then from the global bus to the local bus (1). Issue the received bus command. The processor (7) that received the re-execution response to the invalidation instruction
After processing the bus instruction issued in (1), if the received instruction is an instruction that requires invalidation, invalidate re
If the ad command received is any other command, the invalidation command as before is issued.

6. In response to the invalidation instruction issued to the global bus (13), the bus bridge (12) issues an invalidation instruction for the address 1000 to the local bus (2). 7. The processor (9) and the bus bridge (10) see the invalidation instruction and assert the invalidation processing in-progress signal (16).

8. The processor (10) is in the cache memory
After confirming that there is no data at address 1000, cancel the invalidation processing in progress signal (16). On the other hand, the processor (9)
6) Start invalidation processing of data at address 1000 while asserting.

9. The processor stops asserting the invalidation processing in progress signal (16) after the invalidation processing is completed. 10. Processors (9) and (10) have signals (1
The bus bridge (1
2) returns a completion response to the invalidation instruction of the global bus, and completes the invalidation instruction on the global bus.

11. Upon receiving this response, the bus bridge (11) stops asserting the invalidation processing in-progress signal (15). 12. The processor (7) that issued the invalidation instruction sees that both the processor (9) and the bus bridge (11) de-assert the invalidation-in-progress signal and that the invalidation instruction has completed. Know and start processing the next instruction. Like this
The conventional technique involves a bus delay of 2N-1 stages in order to perform invalidation processing across N layers of buses.

[0021]

In a multiprocessor system in which a shared bus disclosed in Japanese Patent Application No. 05-199772 is coupled to other parts of the system through a bus bridge in a consistent manner, The bus bridge has tag information of the cache memory connected to the shared bus in order to snoop requests from other parts of the system. In such a system, the tag duplication on the cache memory side becomes unnecessary by snooping the request on the shared bus in the bus bridge.

The first invention of the present invention has been made in view of this point, and in a system in which a shared bus is coupled with other parts of the system by a bus bridge in a consistent manner, Tag duplication on the cache memory side can be eliminated by using the cache tag information of the bridge to perform snooping of requests on the shared bus, reducing the hardware amount of the cache memory and enabling simplification. The purpose is to provide a cheaper and faster system.

On the other hand, in the conventional hierarchical bus system, when an invalidation instruction is issued, after the invalidation instruction is completed on all local buses other than the local bus to which the module that issued the invalidation instruction is connected. The invalidation instruction is completed on the global bus, and further, the invalidation instruction on the local bus that issued the invalidation instruction is completed after the invalidation instruction is completed on the global bus. Therefore, until the invalidation instruction is completed, the global bus and the local bus to which the module that issued the invalidation instruction is connected cannot be used. Further, the module that issued the invalidation instruction cannot start the next processing until the invalidation instruction is completed.

The second invention of the present invention has been made in view of this point, and in the hierarchical bus system, the efficiency of use of the bus when the invalidation instruction is issued is increased, and the invalidation instruction is further issued. It is an object of the present invention to provide a system in which the created module can move to the next processing at an early stage.

[0025]

The first invention of the present invention is as follows:
A multiprocessor system for maintaining data consistency among a plurality of nodes connected by a first bus, the node comprising a processor having a cache memory, a memory device, the processor and the memory device. A cache bus coupled to the second bus, and a bus bridge device coupling the processor and the memory device with the first bus. Means for simulating the tag information, means for outputting a memory inhibition signal indicating that the memory operation is inhibited to the memory device based on the tag information obtained by the means, and the cache based on the tag information. And a means for outputting a snoop request signal indicating that it is necessary to perform a snoop operation on the memory. And characterized in that.

A second invention of the present invention is a multiprocessor system for maintaining data consistency among a plurality of nodes connected by a first bus, the nodes comprising:
A bus-bridge device for connecting the second bus and the first bus; a second bus for connecting the processor; and a bus-bridge device for coupling the second bus and the first bus. Means for issuing to the second bus a bus instruction that has acquired the right to use the first bus, prior to another bus instruction that arrives at the same time as this bus instruction and is for the same memory address, When issuing the invalidation instruction for the cache memory from the second bus to the first bus, the invalidation request is completed when the right to use the first bus is acquired. Means for outputting the indicated signal to the second bus.

[0027]

According to the first aspect of the present invention, when a request is issued from a certain cache memory to the shared bus (second bus), the bus bridge retrieves the current tag information, and if the shared bus is used, When any of the cache memories connected to the (second bus) has the latest data, the memory inhibit signal and the snoop request signal for the cache memory are asserted to maintain the consistency. .

Further, when a request is issued from the bus bridge to the shared bus (second bus) by a request from another part of the system (transmitted via the first bus), the bus bridge issues the request. The tag information is previously searched in parallel, and if any cache memory connected to the shared bus (second bus) has the latest data, a memory inhibit signal and a snoop request signal for the cache memory. Acts to maintain consistency by asserting.

In any case, the bus bridge acts so as to update the tag information by the tag information simulation means as needed in accordance with the processing of the request. According to the second aspect of the present invention, when a module issues an invalidation instruction in a hierarchical bus system, a bus bridge connected to the same local bus (second bus) as the module is provided. Global bus (first bus)
By returning a response when the right to use is acquired, the invalidation instruction on the local bus is completed, the next bus instruction can be issued, and the module that issued the invalidation instruction is invalid. It becomes possible to start the next processing by the conversion instruction.

When the bus bridge receives an invalidation instruction from another bus bridge connected to the global bus in response to the invalidation instruction issued to the global bus, each bus The global bus may be used for the next bus instruction to complete an invalidate instruction on the global bus without waiting for the invalidate instruction on the local bus to which the bridge is attached to complete. It will be possible.

[0031]

【Example】

(Embodiment 1) A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration diagram of a multiprocessor system according to an embodiment of the present invention. 100 is a node 1, 200 is a node 2, and the system shared bus 3
Are bound by 00. CPU on node 1
101 and CPU 102 are cache memory 10 respectively
3, the cache memory 104 is connected, and the cache memory 103, the cache memory 104, and the local memory 105 are connected by the local shared bus 106. The bus bridge 107 connects them to the system shared bus 3
Connect with 00.

The cache memory 103 has CPU tag information 1
08, the cache memory 104 has the CPU tag information 109, and holds whether or not the cache data hits the request from the CPU 101 and the local shared bus 106, the state of the cache data, and the like.

The bus bridge 107 is connected to the simulated bus tag information 112 corresponding to the cache memory 103 and the simulated bus tag information 113 corresponding to the tag memory 104 by the tag information simulation means 110 and the tag snoop means 111. There is.
The bus bridge 107 further snoops requests from the local shared bus 106 and the system shared bus 300, and as a result, determines whether or not it is necessary to intervene in the cache memory 103 and the cache memory 104, respectively. The unit 114 and the local memory 105 have a memory inhibition determination unit 115 for determining whether or not to inhibit the memory operation, and the snoop request determination unit includes the snoop request signal 116 and the snoop request signal 1
17 connects the cache memory 103 and the cache memory 104, and the memory inhibition determination unit is connected to the local memory 105 by the memory inhibition signal 118.

The node 2 has the same structure as the node 1, and a detailed description thereof will be omitted. The thus configured multiprocessor system operates as follows. Here, the cache memory is M (exclusive dirty) O (shared dirty) E (exclusive clean) S (shared clean) I (invalid)
It is assumed that the write-in-validate type copyback protocol that takes the following five states is adopted. The operation of the cache memory and the state transition of the tag are not directly related to the present invention and will not be described.

For details, refer to Document A Class of Compatible Cache
Consistency Protocols and their Support by The IEE
E Futurebus, 13th ISCA, June 1986. (Paul Sweazey, Al
anJay Smith). Further, in this embodiment, the above-mentioned SPARC is added to the local shared bus and the system shared bus.
Here is an example of using MBus.

CR having the address of the local memory 105 from the CPU 101 to the cache memory 103
(Shared Read) When a request is issued, the cache memory 103 operates based on the protocol. In the present invention, a case where a cache hit occurs is not important, so a case where a cache miss occurs will be considered. When a cache miss occurs, a CR request is issued from the cache memory 103 to the local shared bus 106. The bus bridge 107 is a tag snoop means 111.
Then, the bus tag information 113 corresponding to the CPU 102 is searched, and a snoop request signal 117 connected to the CPU 102 and a memory inhibit signal 118 connected to the local memory 105 are output according to the result.

The correspondence between bus tag information and output signals is shown in FIG. If the CPU 102 issues a CR request having the address of the local memory 105 to the cache memory 104 and similarly a cache miss occurs in the cache memory 104, a CR request is similarly issued to the local shared bus 106. .

The bus bridge 107 is a tag snoop means 1
The bus tag information 112 corresponding to the CPU 101 is searched by 11 and a snoop request signal 116 connected to the CPU 101 and a memory inhibit signal 118 connected to the local memory 105 are output according to the result. Correspondence between the bus tag information and the output signal is as shown in FIG.

Up to now, the case where the CR request is issued from the cache memory to the local shared bus has been described. In another case, the case where the CR request is issued from the system shared bus to the local shared bus through the bus bridge. I will describe. CP is one example
If the U 201 issues a CR request having the address of the local memory 105 to the cache memory 203 and a cache miss occurs in the cache memory 203, the CR request is first issued to the local shared bus 206. The bus bridge searches the bus tag information 213 for the cache memory 204 by the tag snoop means 111.

If there is no valid data in its own node, a CR request to the shared bus 300 is issued. The detailed description of the case in which the CR request is issued to the shared bus is omitted because it is not related to the essence of the present invention. The details are described in Japanese Patent Application No. 05-199772 mentioned above. In the other bus bridge 106, the tag snoop means 111 causes the bus tag information 112 corresponding to the CPU 101 and the bus tag information 1 corresponding to the CPU 102.
13 is searched, and the snoop request signal 11 is searched according to the result.
6, 117 and the memory inhibit signal 118 are output. The relationship between the tag information and the output signal is shown in FIG.

The same operation is performed when a CRI (exclusive read) request is issued instead of the CR request. In this case, the tag transition after the request is completed is different.
The CI (invalidation request) request, the CWI request, the RD request, and the WR (write-back) request are not related to the present invention, so the description thereof will be omitted.

In either case, when the request is executed, the tag information simulation means of the bus bridge updates the bus tag information as needed. The tag information simulation means can simulate the CPU tag information in the cache memory by monitoring the request type on the local shared bus and the response to it on the bus. In this embodiment, a SPARC MBus is used for the local shared bus.
The transition of the bus tag information when using is shown in FIGS. 4 and 5. FIG. 4 is a transition of bus tag information regarding the processor that issued the request. FIG. 5 is a transition of bus tag information regarding a processor that has not issued a request.

In the case of this example, when a write hit from the CPU to the cache memory occurs, it cannot be known on the local shared bus, so the bus tag information of the bus bridge and the CPU tag information of the cache memory do not match temporarily. There are cases. This is a case where the CPU tag information of the cache memory is changed to M by the write hit when the bus tag information of the bus bridge shows E. Therefore, when the bus tag information of the bus bridge shows E, the snoop request signal is output. It is necessary to retrieve the CPU tag information in the cache memory by asserting the memory inhibit signal. However, if a signal for detecting a write hit is separately provided, the tag information in the bus bridge can be matched with the tag information in the cache memory, so that unnecessary snoop does not occur.

In this embodiment, two nodes are connected by the system shared bus, but the effectiveness of the present invention does not change even if the number of nodes is larger than that. In this embodiment, two CPUs are connected to the local shared bus through their respective caches, but the number of CPU and cache pairs is arbitrary, and tag information can be connected to the bus bridge according to the number. Well, the effectiveness of the invention does not change.

In this embodiment, the system has two hierarchies of the system shared bus and the local shared bus. However, if a bus bridge is similarly configured between the hierarchies, it is possible to take more hierarchies and its modification. Can be considered variously, but the effectiveness of the present invention does not change in any modification.

In this embodiment, the SPARC MBus is used for the local shared bus and the system shared bus.
The present invention is not limited to this, and can be applied to various bus protocols, and its effectiveness remains unchanged.

Although the snoop request signal and the memory inhibit signal are independent signals in this embodiment, the present invention is not limited to this, and it is possible to connect them as one signal. The effectiveness remains the same. (Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings. FIG. 7 shows the overall configuration of a multiprocessor system according to an embodiment of the present invention. 2 sets of local
Cache memory (3, 4, 5, 6) on bus (1, 2)
Two sets of processor modules (7,8,9,10)
And bus bridges (11, 12) are connected, and these local buses are connected to the global bus via the bus bridge. In addition to the two bus bridges, a memory module (14) is connected to the global bus. On the local bus, there are open drain invalidating signals (15, 16), which are connected to the processor module and the bus bridge, respectively. When an invalidate instruction is issued on the local bus, the processor module and the bus bridge continue to assert this signal until they are ready to accept the next bus instruction. Modules connected to the local bus cannot issue the next bus instruction while this signal is asserted.

FIG. 8 shows a schematic structure of the bus bridges (11, 12) in FIG. Bus bridge is local
A local bus instruction reception unit that receives bus instructions issued by a bus module connected to the bus
A global bus request generation unit for requesting a right to use the global bus according to the bus command received by the bus command reception unit is provided. On the global bus (13), a global bus that arbitrates so that only one bus module uses the global bus at the same time in response to bus use requests from multiple bus modules connected to the global bus. There is a bus arbitration section.

The bus bridge also has a global
After obtaining the right to use the global bus by the bus arbitration unit,
A global bus instruction issuing unit that issues the bus instruction received by the local bus instruction receiving unit to the global bus, and a global bus instruction receiving unit that receives the bus instruction issued by the bus module connected to the global bus A local bus request generation unit for requesting the right to use the local bus according to the bus command received by the global bus command reception unit. Local bus (1,2)
Above, there is a local bus arbitration unit that arbitrates for a bus use request from a bus module connected to a plurality of local buses so that another bus module uses the local bus at the same time. .

The bus bridge further issues a local bus instruction issued to the local bus by the local bus arbitration unit and then issues the bus instruction accepted by the global bus instruction acceptance unit to the local bus. When a bus instruction for the same cache line is received by the local section, the local bus instruction receiving section, and the global bus instruction receiving section, the bus instruction of the local bus is suspended and the re-execution is prompted. When the global bus arbitration unit can acquire the right to use the global bus to issue the invalidation instruction received by the re-execution notification unit and the local bus instruction reception unit to the global bus, the local bus is notified to the local bus. And a preceding response unit that returns a completion response.

With this configuration, when a bus instruction is issued simultaneously on two local buses, the request generation unit of the bus bridge connected to each local bus requests the right to use the global bus. At this time, the priority determining unit on the global bus selects one of these requests and gives the right to use the global bus.

In response to the bus command of the local bus of the bus bridge that has acquired the right to use, the preceding response unit returns a completion response at that time. For other bus commands, the re-execution notification unit returns a re-execution response instructing re-execution.

Then, the instruction that came from the global bus is
It is issued by the priority instruction issuing unit to the local bus that could not acquire the global bus. For the local bus that could not be acquired by the global bus, the bus instruction canceled by the bus instruction reissue unit is reissued after the completion of this bus instruction, and the processing continues. At this time, the state of the cache may have been changed by an instruction issued from the global bus first, so that a bus instruction different from the previous one may be issued or may not be reissued.

Therefore, when the invalidation instruction is issued to the bus bridge and the right to use the global bus is acquired, the invalidation instruction is issued to another local bus.
As it is guaranteed to complete, the invalidation instruction on the local bus is completed by returning a response to the local bus without waiting for the invalidation instruction on the local bus to complete. Further, when the invalidation instruction is accepted by all the bus bridges connected to the global bus, the invalidation on the global bus to which each bus bridge is connected is completed.

The operation when the processor (7) rewrites the data at the addresses 1000 in the cache memory (3) and the cache memory (6) will be described below.

1. First, the processor (7) is a local bus
Issue an invalidation command for address 1000 in (1). 2. The processor (8) and the bus bridge (11) see the invalidation instruction and assert the invalidation processing in-progress signal (15).

3. The processor (8) uses the cache memory
After confirming that there is no data at address 1000, the assertion of the invalidation processing in progress signal (15) is stopped. However, the bus bridge (11) keeps asserting.

4. The bus bridge (11) issues a request to use the global bus (13). 5. The bus bridge (11) issues an invalidation instruction to the global bus (13) when it is granted the right to use the global bus (13), and asserts the invalidation processing in progress signal (15). Stop doing. The bus bridge (12) gets the right to use the global bus (13) before the bus bridge (11) gets the right to use the global bus (13), and a bus instruction for the data at the same address is issued. If the bus
The bridge (11) returns a re-execution response to the invalidation instruction issued by the processor (7), completes the invalidation instruction on the local bus (1) once, and then returns to the local bus (1). Issues a bus instruction received from the global bus. The processor (7) that received the re-execution response to the invalidation instruction processed the bus instruction issued to the local bus (1), and then the received instruction was an instruction that requires invalidation. In this case, the invalidation read instruction is issued, and if the received instruction is any other instruction, the previous invalidation instruction is issued.

6. Here, since there is no module that asserts the invalidation processing in-progress signal (15), the processor (7) starts the next processing assuming that the invalidation processing is completed. The local bus (3) is ready to issue the next bus instruction.

7. In response to the invalidation instruction issued to the global bus, the bus bridge (12) switches to the local bus.
Issue an invalidation command for address 1000. 8. The processor (9) and the bus bridge (10) see the invalidation instruction and assert the invalidation processing in-progress signal (16).

9. The processor (10) uses the cache memory
After confirming that there is no data at address 1000, the assertion of the invalidation processing in progress signal (16) is stopped. On the other hand, the processor (9) starts the invalidation processing of the data at address 1000 while asserting the invalidation processing in-progress signal (16).

10. The processor stops asserting the invalidation processing in-progress signal (16) after the invalidation processing is completed. At this point, the invalidation processing of the entire system is completed. Further, in the present embodiment, the modules connected to the global bus are only the two bus bridges and the memory that does not need to perform the invalidation processing, so that the completion of the invalidation processing can be notified by a normal bus response. Since the global bus is not provided with the invalidation execution signal because it is possible, it is possible to provide the invalidation execution signal like the local bus when there are three or more bus bridges.

[0063]

As described above, according to the first aspect of the present invention, in the distributed shared multiprocessor system using the shared bus, the cache memory connected to the shared bus needs the tag duplication for the bus snoop. Therefore, the amount of hardware can be reduced. Moreover, since the hardware can be simplified, a great effect that a higher-speed system can be provided at low cost is achieved.

According to the second aspect of the present invention, the bus use efficiency of the invalidation instruction in the hierarchical bus system is improved, and the module that issued the invalidation instruction waits until the invalidation instruction is completed. The next processing can be started early because of shortening.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a multiprocessor system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a correspondence table of tag information and output signals when a request is issued from a processor to a local shared bus.

FIG. 3 is a diagram showing a correspondence table of tag information and output signals when a request is issued from the system shared bus to the local shared bus.

FIG. 4 is a diagram showing a transition table of tag information regarding a processor that issued a request.

FIG. 5 is a diagram showing a transition table of tag information for a processor that has not issued a request.

FIG. 6 is a schematic configuration diagram showing a conventional technique.

FIG. 7 is a schematic configuration diagram of a multiprocessor system according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a bus bridge in the present embodiment.

[Explanation of symbols]

100, 200 ... Node 300 ... System shared bus 101, 102, 201, 202 ... Processor 103, 104, 203, 204 ... Cache memory 105, 205 ... Local memory 106, 206 ... Local shared bus 107, 207 ... Bus bridge 108, 109, 208, 209 ... CPU tag information 108 ', 109', 208 ', 209' ... Duplicate CPU tag information 110, 210 ... Tag information simulation means 111, 211 ... Tag snoop means 112, 113, 212, 213 ... Bus tag information 114, 214 ... Snoop request determination means 115, 215 ... Memory inhibition determination means 116, 117, 216, 217 ... Snoop request signal 118, 219 ... Memory inhibition signal 119, 219 ... Memory inhibit signal (MIH) 1, 2 ... B Cull bus 3, 4, 5, 6 ... Cache memory 7, 8, 9, 10 ... Processor 11, 12 ... Bus bridge 13 ... Global bus 14 ... Memory module 15, 16 ... Invalidation process execution signal 17 , 18… pull-up resistance

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Osamu Wakamori 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (2)

[Claims] 1. A multiprocessor system for maintaining data consistency among a plurality of nodes connected by a first bus, the node comprising a processor having a cache memory, a memory device, and the processor. And a bus bridge device for connecting the processor and the memory device to the first bus, the bus bridge device being connected to the second bus. Means for simulating tag information of a cache memory that is stored, means for outputting a memory inhibition signal indicating that the memory operation is inhibited to the memory device based on the tag information obtained by the means, and the tag Output a snoop request signal indicating that it is necessary to perform a snoop operation to the cache memory based on the information. And a multiprocessor system. 2. A multiprocessor system for maintaining data consistency among a plurality of nodes connected by a first bus, the node connecting a processor having a cache memory and the processor. A second bus, and a bus bridge device for coupling the second bus and the first bus, the bus bridge device acquiring the right to use the first bus. Command
Means for issuing to the second bus prior to other bus instructions that arrive at the same time as this bus instruction and are for the same memory address; and an invalidating instruction for the cache memory from the second bus. When issuing to the first bus, the first
Means for outputting to the second bus a signal indicating that the invalidation request has been completed when the right to use the bus has been acquired.