CN110781107A - Low-delay fusion IO control method and device based on DRAM interface - Google Patents
Low-delay fusion IO control method and device based on DRAM interface Download PDFInfo
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- G06F13/14—Handling requests for interconnection or transfer
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Abstract
The embodiment of the invention discloses a low-delay fusion IO control method and a low-delay fusion IO control device based on a DRAM (dynamic random access memory) interface, wherein the method comprises the following steps: constructing a converged address space accessed by a central processing unit based on the physical capacity of the solid state disk; the fusion address space is divided into a DRAM physical space and an expansion address space, and common system data are stored in the DRAM physical space; when the central processing unit accesses the fused address space through a DRAM interface of a preset fused I/O controller, acquiring a target address space identifier corresponding to data to be accessed; and searching the target address space accessed by the central processing unit according to a preset address space identifier, a mapping table of the address space and the target address space identifier. By adopting the low-delay fusion IO control method based on the DRAM interface, a double-address space mode can be adopted, the data transmission efficiency is improved, and the data access delay in a server is effectively reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of server design, in particular to a low-delay fusion IO control method and device based on a DRAM (dynamic random access memory) interface, and further relates to electronic equipment and a computer readable storage medium.
Background
In recent years, with the rapid development of network technology, the data access speed of a server system cannot adapt to the development requirements of current cloud computing, big data and AI computing, resulting in higher and higher operation cost. Therefore, how to improve the data access efficiency of the server system becomes a technical problem to be solved urgently in the field.
The data Latency (Latency) is the time from the request to the first data is obtained. The access speed of data is an important factor influencing the performance of a computer, and the access of high-speed data is mainly realized by a local storage mode and a network mode. The hard disk space is a main choice for local storage, the data delay time caused by mechanical rotation is 10 milliseconds, and the Access time difference with the Memory space is 6 orders of magnitude, so that an operating system must separate the Access process of the hard disk space from the Access of the Memory space and perform Direct Memory Access (DMA). The latency of network access to data includes the fundamental latency (physical layer and link layer) and administrative latency of the interface protocol, each of which is on the order of approximately 100 nanoseconds, since the fundamental latency includes parallel to serial conversion of transmit and receive, and the complex logic of splicing and parsing of data packets.
The external storage of the network and hard disk space and the access of the computer system usually adopt a Direct Memory Access (DMA) mode, the uncertainty of data delay is better solved, and the DMA needs to occupy a part of the bandwidth of a DRAM interface. In the case of a CPU having two 64-bit channels, the maximum memory bandwidth is typically 51.2 GB/s. The maximum bandwidth of a PCIe (Gen3 x4) hard disk space is as high as 32GB/s, and the maximum bandwidth of a 100Gbe network card exceeds 12 GB/s. Although the DMA space rarely occupies the processing time of the central processing unit, the DMA with high-speed IO can occupy considerable memory access bandwidth of the central processing unit, and is an important factor that restricts the efficiency of the server system in the case of multi-core (more than 8). Therefore, it is desirable to provide a new low-latency fusion IO control scheme based on a DRAM interface.
Disclosure of Invention
Therefore, the embodiment of the invention provides a low-delay fusion IO control method based on a DRAM (dynamic random access memory) interface, so as to solve the problem of high data access delay in a server in the prior art.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
in a first aspect, an embodiment of the present invention provides a low-latency fusion IO control method based on a DRAM interface, including: constructing a converged address space accessed by a central processing unit based on the physical capacity of the solid state disk; the fusion address space is divided into a DRAM physical space and an expansion address space, and common system data are stored in the DRAM physical space; wherein the DRAM physical space is a direct mapping of a portion of the physical capacity of the solid state disk; when the central processing unit accesses the fused address space through a DRAM interface of a preset fused I/O controller, acquiring a target address space identifier corresponding to data to be accessed; searching a target address space accessed by the central processing unit according to a preset address space identifier, a mapping table of the address space and the target address space identifier; wherein the target address space comprises at least one of a DRAM physical space or an extended address space.
Further, the low-latency fusion IO control method based on the DRAM interface further includes: introducing an I2C bus-based interrupt mechanism into the converged I/O controller; the interrupt mechanism is specifically a memory storage module of an added I2C bus master controller patrol controlled controller, and generates an interrupt signal when detecting that the memory storage module is abnormal.
Furthermore, the extended address space is an address space of the solid state disk accessed by the central processing unit through the DRAM interface, and the address space is a direct memory access space.
Further, the DRAM physical space is the memory space of the actual DRAM.
Further, the fusion I/O controller is a controller that integrates the memory space of the dynamic random access memory and the access path of the high-speed I/O; wherein, the high-speed I/O refers to an I/O bus interface of the solid state disk and the Ethernet controller.
In a second aspect, an embodiment of the present invention further provides a low-latency fusion IO control apparatus based on a DRAM interface, including: the integrated address space unit is used for constructing an integrated address space accessed by the central processing unit based on the physical capacity of the solid state disk; the address space dividing unit is used for dividing the fused address space into a DRAM physical space and an extended address space and storing the commonly used system data into the DRAM physical space; wherein the DRAM physical space is a direct mapping of a portion of the physical capacity of the solid state disk; the target address space searching unit is used for obtaining a target address space identifier corresponding to the data to be accessed when the central processing unit accesses the fused address space through a preset DRAM interface of the fused I/O controller; searching a target address space accessed by the central processing unit according to a preset address space identifier, a mapping table of the address space and the target address space identifier; wherein the target address space comprises at least one of a DRAM physical space or an extended address space.
Further, the low-latency fusion IO control device based on the DRAM interface further includes: an interrupt mechanism unit, which is used for introducing an interrupt mechanism based on an I2C bus in the fusion I/O controller; the interrupt mechanism is specifically a memory storage module of an added I2C bus master controller patrol controlled controller, and generates an interrupt signal when detecting that the memory storage module is abnormal.
Furthermore, the extended address space is an address space of the solid state disk accessed by the central processing unit through the DRAM interface, and the address space is a direct memory access space.
Further, the DRAM physical space is the memory space of the actual DRAM.
Further, the fusion I/O controller is a controller that integrates the memory space of the dynamic random access memory and the access path of the high-speed I/O; wherein, the high-speed I/O refers to an I/O bus interface of the solid state disk and the Ethernet controller.
In a third aspect, an embodiment of the present invention further provides an electronic device, including: a processor and a memory; the memory is used for storing a program of the low-delay fusion IO control method based on the DRAM interface, and after the electronic device is powered on and runs the program of the low-delay fusion IO control method based on the DRAM interface through the processor, the electronic device executes any one of the above-mentioned low-delay fusion IO control methods based on the DRAM interface.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium contains one or more program instructions, where the one or more program instructions are used for a server to execute any one of the above methods for low-latency fusion IO control based on a DRAM interface.
By adopting the low-delay fusion IO control method based on the DRAM interface, a double-address space mode can be adopted, the data transmission efficiency is improved, and the data access delay in a server is effectively reduced.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
Fig. 1 is a flowchart of a low-latency fusion IO control method based on a DRAM interface according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a low-latency fusion IO control apparatus based on a DRAM interface according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an electronic device according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a conventional IO system access delay path provided in the prior art;
fig. 5 is a schematic diagram of an access delay path of a converged IO system according to an embodiment of the present invention.
Detailed Description
The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, a computer program generally runs in a Memory space, and the Memory includes two parts, namely a storage medium and an Access interface, wherein the storage medium main body may be a Dynamic Memory (DRAM) or the like, and an operating system may Access the Dynamic Memory through the DRAM interface. Since the dynamic memory is closest to the central processor and is a parallel interface, there is no overhead such as serial-to-parallel conversion, and therefore there is a low latency (i.e., the time from the beginning of the access to the time the first data is obtained) of 10 nanoseconds.
The operating system is usually stored on a solid state disk or a mechanical disk and needs to be called into a memory space to run, so that the speed of a DRAM interface has a great influence on the data access performance of the operating system. Since the DRAM interface usually has a certain access time and no interrupt mechanism, when the solid state disk and the network data need to be transferred to the memory space, the DRAM interface may need to wait, and a corresponding control mechanism needs to be provided to reduce the delay of data access. Therefore, the invention provides a low-delay fusion IO control method based on a DRAM interface.
The following describes an embodiment of the low-latency fusion IO control method based on the DRAM interface according to the present invention in detail. As shown in fig. 1, which is a flowchart of a low-latency fusion IO control method based on a DRAM interface according to an embodiment of the present invention, a specific implementation process includes the following steps:
step S101: and constructing a converged address space accessed by the central processing unit based on the physical capacity of the solid state disk.
In the embodiment of the present invention, the Solid State disk is a Solid State Drive (SSD) in a server. A solid state disk is a hard disk made of an array of solid state electronic memory chips, and is generally composed of a control unit and a memory unit (FLASH chip, DRAM chip).
The Central Processing Unit (CPU) is a processing unit for data processing and program operation, and is used as an operation and control core of the computer system; which may be used as a core component for reading instructions, interpreting computer instructions and processing data in computer software, decoding instructions and executing instructions. The central processing unit mainly comprises a controller and an arithmetic unit, and data relation can be established between the central processing unit and the fusion address space through a fusion IO bus.
Step S102: the fusion address space is divided into a DRAM physical space and an expansion address space, and common system data are stored in the DRAM physical space; wherein the DRAM physical space is a direct mapping of a portion of the physical capacity of the solid state disk.
After the fused address space accessed by the central processing unit is constructed in the above step S101, the fused address space is further divided into a DRAM physical space and an extended address space in this step.
In the embodiment of the invention, the fused address space is divided into double address spaces (DRAM physical space and extended address space), so that the common system data can be stored in the DRAM physical space, and a waiting mechanism is not needed when the DRAM physical space is accessed. The extended address space may merge solid state drives and high speed networks (100Gbe, InfiniBand, etc.), which, by being physically independent of the DRAM space, does not affect access to the DRAM physical space when accessing the extended address space.
The extended address space is the address space of the solid state disk accessed by the central processing unit through the DRAM interface, and the address space is the direct memory access space. The physical space of the DRAM is the memory space of the actual dynamic random access memory.
For example, the size of the converged address space accessed by the central processing unit is equal to the physical capacity (such as 1TB) of the solid state disk. The fused address space may be divided into two parts, a DRAM physical space (e.g., 32GB) and an extended address space (here 1TB-32 GB). The DRAM physical space (here, 32GB) is a direct mapping of the physical capacity (i.e., 32GB capacity) of a portion of the solid state disk, which is the same as normal access to DRAM (without waiting) since it is the dynamic memory space actually used by the central processor for access. The extended address space is a solid state disk address space accessed through a DRAM interface and is a DMA space, and the solid state disk and the high-speed network can access the extended address space by adopting a direct memory access mode.
Step S103: when the central processing unit accesses the fused address space through a DRAM interface of a preset fused I/O controller, acquiring a target address space identifier corresponding to data to be accessed, and searching the target address space accessed by the central processing unit according to the preset address space identifier, a mapping table of the address space and the target address space identifier; wherein the target address space comprises at least one of a DRAM physical space or an extended address space.
After the fused address space is divided into a DRAM physical space and an extended address space in step S102, a target address space identifier corresponding to data to be accessed is obtained in this step, and a target address space accessed by the central processing unit is searched according to a preset address space identifier, a mapping table of address spaces, and the target address space identifier.
In the embodiment of the invention, an I2C bus-based interrupt mechanism is introduced into the fusion I/O controller; the interrupt mechanism is specifically a memory storage module of an added I2C bus master controller patrol controlled controller, and generates an interrupt signal when detecting that the memory storage module is abnormal.
The fusion I/O controller is a controller for integrating the memory space of the dynamic random access memory and the access path of the high-speed I/O. Wherein, the high-speed I/O refers to an I/O bus interface of the solid state disk and the Ethernet controller.
The converged IO bus refers to an access path of high-speed IO integrating a memory space (DRAM), a solid state disk, and a high-speed network, and accesses through a DRAM interface. The high-speed network may be 100Gbe, or ib (infiniband), etc.
As shown in fig. 4 and 5, a schematic diagram of a conventional IO system access delay path in the prior art and a schematic diagram of a converged IO system access delay path provided in an embodiment of the present invention are respectively shown.
Wherein, BWc _ max represents the maximum bandwidth available to the central processing unit core (CPU core); BWd _ max is the maximum bandwidth of the DRAM interface; BWe _ max is the maximum bandwidth of 100Gbe interface; BWs _ max is the maximum bandwidth of the solid state disk interface; PCIE RT is a root node of PCIe; tp is the PCIe Physical (PHY) and Link Layer (LINK) base latency; tnet is 100Gbe Physical (PHY) and LINK Layer (LINK) base latency; ts is the basic delay of the solid state disk interface; tm is the basic delay of a central processor accessing a DRAM interface (DIMM interface); tmd is the basic delay for the converged IO controller (converged IO controller) to access the DRAM interface.
When the conventional IO system employing PCIe as shown in fig. 4, T1(cable-DRAM) is a delay time from the cable connector to the DRAM interface; t1(NAND-DRAM) is the latency from SSD-NAND to DRAM interface; t1(cable-NAND) is the delay time from the cable connector to the SSD-NAND.
When the converged IO controller disclosed by the present invention is adopted as shown in fig. 5, T2(cable-DRAM) is the delay time from the cable connector to the DIMM interface, T2(NAND-DRAM) is the delay time from the SSD-NAND to the DIMM interface, and T2(cable-NAND) is the delay time from the cable connector to the SSD-NAND. It can be seen from fig. 5 that the delay time of the fusion IO is reduced by about 100 ns.
Under the full load of a network and SSD DMA in the conventional PCIe IO controller as shown in FIG. 4 (bandwidth 256Gb/s), the bandwidth that can be obtained by the central processor core is only 44Gb/s, while the converged IO controller of the present application can still obtain nearly 400Gb/s under the condition of the full load of the DMA because of the independent path.
By adopting the low-delay fusion IO control method based on the DRAM interface, the efficiency of data transmission can be improved by adopting a double-address space mode, and the access delay of a system is effectively reduced.
Corresponding to the low-delay fusion IO control method based on the DRAM interface, the invention also provides a low-delay fusion IO control device based on the DRAM interface. Since the embodiment of the apparatus is similar to the above method embodiment, the description is relatively simple, and please refer to the description in the above method embodiment section for the relevant point, and the following description is only illustrative of an embodiment of the low-latency fusion IO control apparatus based on a DRAM interface. Fig. 2 is a schematic diagram of a low latency fusion IO control device based on a DRAM interface according to an embodiment of the present invention.
The low-delay fusion IO control device based on the DRAM interface comprises the following parts:
and the fused address space unit 201 is used for constructing a fused address space accessed by the central processing unit based on the physical capacity of the solid state disk.
In the embodiment of the present invention, the Solid State disk is a Solid State Drive (SSD) in a server. A solid state disk is a hard disk made of an array of solid state electronic memory chips, and is generally composed of a control unit and a memory unit (FLASH chip, DRAM chip). The Central Processing Unit (CPU) is a processing unit for data processing and program operation, and is used as an operation and control core of the computer system; which may be used as a core component for reading instructions, interpreting computer instructions and processing data in computer software, decoding instructions and executing instructions. The central processing unit mainly comprises a controller and an arithmetic unit, and data relation can be established between the central processing unit and the fusion address space through a fusion IO bus.
An address space dividing unit 202, configured to divide the merged address space into a DRAM physical space and an extended address space, and store common system data in the DRAM physical space; wherein the DRAM physical space is a direct mapping of a portion of the physical capacity of the solid state disk.
After the fused address space accessed by the central processing unit is constructed in the above-described fused address space unit 201, the fused address space is further divided into a DRAM physical space and an extended address space in the address space dividing unit 202.
In the embodiment of the invention, the fused address space is divided into double address spaces (DRAM physical space and extended address space), so that the common system data can be stored in the DRAM physical space, and a waiting mechanism is not needed when the DRAM physical space is accessed. The extended address space may merge solid state drives and high speed networks (100Gbe, InfiniBand, etc.), which, by being physically independent of the DRAM space, does not affect access to the DRAM physical space when accessing the extended address space.
The extended address space is the address space of the solid state disk accessed by the central processing unit through the DRAM interface, and the address space is the direct memory access space. The physical space of the DRAM is the memory space of the actual dynamic random access memory.
For example, the size of the converged address space accessed by the central processing unit is equal to the physical capacity (such as 1TB) of the solid state disk. The fused address space may be divided into two parts, a DRAM physical space (e.g., 32GB) and an extended address space (here 1TB-32 GB). The DRAM physical space (here, 32GB) is a direct mapping of the physical capacity (i.e., 32GB capacity) of a portion of the solid state disk, which is the same as normal access to DRAM (without waiting) since it is the dynamic memory space actually used by the central processor for access. The extended address space is a solid state disk address space accessed through a DRAM interface and is a DMA space, and the solid state disk and the high-speed network can access the extended address space by adopting a direct memory access mode.
A target address space searching unit 203, configured to obtain a target address space identifier corresponding to data to be accessed when the central processing unit accesses a converged address space through a preset DRAM interface of a converged I/O controller, and search for a target address space accessed by the central processing unit according to a preset address space identifier, a mapping table of address spaces, and the target address space identifier; wherein the target address space comprises at least one of a DRAM physical space or an extended address space.
After the merged address space is divided into a DRAM physical space and an extended address space in the merged address space unit 201, a target address space identifier corresponding to data to be accessed is obtained in this step, and a target address space accessed by the central processing unit is searched according to a preset address space identifier, a mapping table of address spaces, and the target address space identifier.
In the embodiment of the invention, an I2C bus-based interrupt mechanism is introduced into the fusion I/O controller; the interrupt mechanism is specifically a memory storage module of an added I2C bus master controller patrol controlled controller, and generates an interrupt signal when detecting that the memory storage module is abnormal.
The fusion I/O controller is a controller for integrating the memory space of the dynamic random access memory and the access path of the high-speed I/O. Wherein, the high-speed I/O refers to an I/O bus interface of the solid state disk and the Ethernet controller.
The converged IO bus refers to an access path of high-speed IO integrating a memory space (DRAM), a solid state disk, and a high-speed network, and accesses through a DRAM interface. The high-speed network may be 100Gbe, or ib (infiniband), etc.
By adopting the low-delay fusion IO control device based on the DRAM interface, the efficiency of data transmission can be improved by adopting a double-address space mode, and the access delay of a system is effectively reduced.
Corresponding to the low-delay fusion IO control method based on the DRAM interface, the invention further provides electronic equipment. Since the embodiment of the electronic device is similar to the above method embodiment, the description is relatively simple, and please refer to the description of the above method embodiment, and the electronic device described below is only schematic. Fig. 3 is a schematic view of an electronic device according to an embodiment of the present invention.
The electronic device specifically includes: a processor 301 and a memory 302; the memory 302 is configured to run one or more program instructions, and is configured to store a program of the low-latency fusion IO control method based on the DRAM interface, and after the server is powered on and runs the program of the low-latency fusion IO control method based on the DRAM interface through the processor 301, the low-latency fusion IO control method based on the DRAM interface is executed. The electronic device of the present invention may be a server.
Corresponding to the low-delay fusion IO control method based on the DRAM interface, the invention also provides a computer storage medium. Since the embodiment of the computer storage medium is similar to the above method embodiment, the description is simple, and please refer to the description of the above method embodiment, and the computer storage medium described below is only schematic.
The computer storage medium contains one or more program instructions, and the one or more program instructions are used for the server to execute the low-latency fusion IO control method based on the DRAM interface.
In an embodiment of the invention, the processor or processor module may be an integrated circuit chip having signal processing capabilities. The Processor may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component.
The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The processor reads the information in the storage medium and completes the steps of the method in combination with the hardware.
The storage medium may be a memory, for example, which may be volatile memory or nonvolatile memory, or which may include both volatile and nonvolatile memory.
The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory.
The volatile Memory may be a Random Access Memory (RAM) which serves as an external cache. By way of example and not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (ddr Data Rate SDRAM), Enhanced SDRAM (ESDRAM), synclink DRAM (SLDRAM), and Direct memory bus RAM (DRRAM).
The storage media described in connection with the embodiments of the invention are intended to comprise, without being limited to, these and any other suitable types of memory.
Those skilled in the art will appreciate that the functionality described in the present invention may be implemented in a combination of hardware and software in one or more of the examples described above. When software is applied, the corresponding functionality may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present invention should be included in the scope of the present invention.
Claims (10)
1. A low-delay fusion IO control method based on a DRAM interface is characterized by comprising the following steps:
constructing a converged address space accessed by a central processing unit based on the physical capacity of the solid state disk;
the fusion address space is divided into a DRAM physical space and an expansion address space, and common system data are stored in the DRAM physical space; wherein the DRAM physical space is a direct mapping of a portion of the physical capacity of the solid state disk;
when the central processing unit accesses the fused address space through a DRAM interface of a preset fused I/O controller, acquiring a target address space identifier corresponding to data to be accessed; searching a target address space accessed by the central processing unit according to a preset address space identifier, a mapping table of the address space and the target address space identifier; wherein the target address space comprises at least one of a DRAM physical space or an extended address space.
2. The low-latency fusion IO control method based on DRAM interface of claim 1, further comprising: introducing an I2C bus-based interrupt mechanism into the converged I/O controller; the interrupt mechanism is specifically a memory storage module of an added I2C bus master controller patrol controlled controller, and generates an interrupt signal when detecting that the memory storage module is abnormal.
3. The low-latency fusion IO control method based on the DRAM interface of claim 1, wherein the extended address space is an address space of a solid state disk accessed by the central processing unit through the DRAM interface, and the address space is a direct memory access space.
4. The method of claim 1, wherein the DRAM physical space is a memory space of a physical DRAM.
5. The low-latency fusion IO control method based on the DRAM interface of claim 4, wherein the fusion I/O controller is a controller that integrates an access path of a memory space and a high-speed I/O of the DRAM; wherein, the high-speed I/O refers to an I/O bus interface of the solid state disk and the Ethernet controller.
6. A low-delay fusion IO control device based on DRAM interface is characterized by comprising:
the integrated address space unit is used for constructing an integrated address space accessed by the central processing unit based on the physical capacity of the solid state disk;
the address space dividing unit is used for dividing the fused address space into a DRAM physical space and an extended address space and storing the commonly used system data into the DRAM physical space; wherein the DRAM physical space is a direct mapping of a portion of the physical capacity of the solid state disk;
the target address space searching unit is used for obtaining a target address space identifier corresponding to the data to be accessed when the central processing unit accesses the fused address space through a preset DRAM interface of the fused I/O controller; searching a target address space accessed by the central processing unit according to a preset address space identifier, a mapping table of the address space and the target address space identifier; wherein the target address space comprises at least one of a DRAM physical space or an extended address space.
7. The low-latency fusion IO control device based on DRAM interface of claim 6, further comprising: an interrupt mechanism unit, which is used for introducing an interrupt mechanism based on an I2C bus in the fusion I/O controller; the interrupt mechanism is specifically a memory storage module of an added I2C bus master controller patrol controlled controller, and generates an interrupt signal when detecting that the memory storage module is abnormal.
8. The low-latency fusion IO control device based on the DRAM interface of claim 6, wherein the extended address space is an address space of a solid state disk accessed by the CPU through the DRAM interface, and the address space is a direct memory access space.
9. An electronic device, comprising:
a processor; and
the memory is used for storing a program of the low-latency fusion IO control method based on the DRAM interface, and after the electronic device is powered on and runs the program of the low-latency fusion IO control method based on the DRAM interface through the processor, the low-latency fusion IO control method based on the DRAM interface as claimed in any one of claims 1 to 5 is executed.
10. A computer-readable storage medium containing one or more program instructions for execution by a server of the DRAM interface-based low-latency fusion IO control method of any one of claims 1-5.
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