CN103810113A - Fusion memory system of nonvolatile memory and dynamic random access memory - Google Patents
Fusion memory system of nonvolatile memory and dynamic random access memory Download PDFInfo
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Abstract
The invention discloses a fusion memory system of a nonvolatile memory and a dynamic random access memory. The nonvolatile memory and the dynamic random access memory are fused together and are jointly used as a memory of a computer system for unified management, the dynamic random access memory can carry out unified addressing together with the nonvolatile memory, part capacity of the dynamic random access memory can be used as a high-speed cache of the nonvolatile memory, the capacity of cache space adapts to data load characteristics by itself and is dynamically matched, so that the access speed of the nonvolatile memory is improved, access frequency of a disk by an I/O can be lowered, and the overall performance of the computer system is improved.
Description
Technical field
The invention belongs to Computer Storage field, be specifically related to the fusion memory system of a kind of nonvolatile memory and dynamic RAM.
Background technology
The appearance of novel nonvolatile memory (Non-Volatile Memory, NVM) for expansion calculator memory provides new approach, has promoted the change of computing machine in system architecture simultaneously.Existing NVM has PCM(Phase Change Memory, phase transition storage), STT-RAM(Spin Transfer Torque Random Access Memory, spin-transfer torque random access memory), MRAM(Magnetic Random Access Memory, magnetic RAM device), FeRAM(Ferroelectric Random Access Memory, ferroelectric random storer) etc.The Ultrahigh of novel nonvolatile memory is no longer traditional flow of charge storage data that electronics forms utilized, but utilize magnetoresistance, resistive effect should, the such mechanism of cholesteric-nematic transition etc. realizes the storage of data, such characteristic makes them have the advantage that many legacy memory can not have, if phase transition storage is a kind of novel nonvolatile memory being made up of chalcogenide material, it utilizes the reversible phase transformation of material to carry out storage information, phase-change memory material can occur from non-crystal state to crystal state under certain condition, return to again the variation of non-crystal state, non-crystal state in this process and crystal state present different resistance characteristics and optical characteristics, therefore, can utilize amorphous state and crystalline state to represent that respectively " 0 " and " 1 " store data, it provides non-volatile, low energy consumption, the features such as random read-write speed is fast.Samsung and company of Micron Technology have released the PCM chip of 90nm and 45nm processing procedure successively at present.
Current novel nonvolatile memory is in the research in computer memory system field, main direction has two: the one, use as external equipment, the 2nd, adopt nonvolatile memory and DRAM as mixing internal memory (Hybrid Memory), DRAM is the cache of nonvolatile memory.
For DRAM, nonvolatile memory has non-volatile, can retain for a long time data, has high density characteristic simultaneously, and this provides support to further developing of memory techniques; But meanwhile nonvolatile memory has relatively large delay, and writing speed and DRAM also have gap, the life-span of part nonvolatile memory is also relatively limited, if think, it can substitute DRAM, just must overcome the problems such as himself, energy consumption and delay in life-span, but existing research is mostly all only for some the carrying out in these problems, do not consider and overcome many-sided restriction, therefore nonvolatile memory does separately internal memory and also has a lot of challenges and predicament, also cannot accomplish in a short time the complete replacer of DRAM.Generally only use at present the ROM part of nonvolatile memory replacement computer original system, or research is used DRAM and nonvolatile memory to build mixing internal memory, make the intermediate storage layer of computer memory system of nonvolatile memory, as: data storage is successively by disk, nonvolatile memory, dynamic RAM, Cache, CPU, data access level is too many, IO path is long, does not give full play of the feature of nonvolatile memory.
Summary of the invention
Given this, the object of the present invention is to provide the fusion memory system of a kind of nonvolatile memory and dynamic RAM, solution active computer internal memory power failure data is lost, starting up is slow, the low inferior series of problems of IO performance of Energy Intensity Reduction difficulty, frequent and disk swapping, simultaneously can be by dynamically adjusting the capacity that merges space, core buffer, the request of self-adaptation application load, improves internal memory service efficiency.
A kind of nonvolatile memory that the present invention proposes and the fusion memory system of dynamic RAM, comprising:
The nonvolatile memory (NVM) of unified addressing, unified management and dynamic RAM (DRAM), wherein DRAM comprises the DRAM cache part of the cache that serves as nonvolatile memory, its spatial content capable of dynamic is adjusted;
Protocol conversion module, for the protocol memory that the protocol conversion of nonvolatile memory phy chip package interface is adopted for memory interface;
Merge Memory Controller Hub, for according to the work schedule of nonvolatile memory and DRAM phy chip, upper strata call instruction and pin level signal condition, worker state machine is set to complete corresponding operation, and the software interface that drives memory chip is provided;
Merge memory management module, for carrying out unified management to merging internal memory, comprise that dram space capacity dynamically adjusts submodule, wherein, described dram space capacity is dynamically adjusted submodule for periodically monitoring the hit rate H of DRAM cache part, and detects read-write requests ratio R:
R=read request number ÷ write request number (1)
In the time of hit rate H < K and read-write requests ratio R<T, increase DRAM cache capacity, wherein, K, T are predetermined threshold, its value can be according to user's request and self-defined configuration, 0<K<1,0<T<1;
In the time of hit rate H >=K and read-write requests ratio R >=T, reduce DRAM cache capacity.
Compared with prior art, the present invention has following beneficial effect: the advantage of having given play to greatest extent nonvolatile memory and DRAM, by merging memory architecture, solve that existing memory system power failure data is lost, starting up is slow, the low inferior series of problems of IO performance of Energy Intensity Reduction difficulty, frequent and disk swapping.
Accompanying drawing explanation
Fig. 1 is the fusion memory system Organization Chart of the embodiment of the present invention;
Fig. 2 is the fusion memory system hardware platform architecture figure of the embodiment of the present invention;
Fig. 3 is the non-volatile fusion internal memory hardware structure figure of the embodiment of the present invention;
Fig. 4 is the fusion memory management module figure of the embodiment of the present invention;
Fig. 5 is that parallel framework merges memory modules figure;
Fig. 6 is that vertical framework merges memory modules figure.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing and exemplary embodiment, the present invention is further elaborated.Should be appreciated that exemplary embodiment described herein is only in order to explain the present invention, the scope of application being not intended to limit the present invention.
The fusion memory system of the embodiment of the present invention is described below: merge memory system overall architecture, merge memory system hardware platform and merge memory management module from three aspects.
One, merge memory system overall architecture
As shown in Figure 1, in the fusion memory system of the embodiment of the present invention, adopt nonvolatile memory (NVM) and dynamic RAM (DRAM) to build internal memory, CPU visits fusion memory system by merging Memory Controller Hub, so-called fusion, the reflection in system level is addressing and the allocation manager scheme of the memory system that is made up of nonvolatile memory and dynamic RAM.
According to DRAM device residing position in this framework, DRAM device is divided into two parts:
The status of part DRAM and nonvolatile memory is equal, and they carry out unified addressing, unified management, and both form traditional internal memory jointly.According to the feature of CPU access memory data, can directly deposit data be arrived to the dynamic RAM part of internal memory or the nonvolatile memory part of internal memory;
Another part DRAM serves as the cache of nonvolatile memory, for covering and alleviating the nonvolatile memory delay performance poor with respect to DRAM, is called DRAM cache.The amount of capacity of this part dram space dynamically can be joined, and can, according to the information such as characteristic and access frequency of upper layer data load, dynamically adjust adaptively amount of capacity.
For whole fusion memory system, it is to DRAM and nonvolatile memory unified addressing, unified management, and the scope of its address is 0～n, can regard as a whole internal memory as to upper strata, and concrete device type is invisible.Wherein, the part that the address of nonvolatile memory part is unified addressing, this part address immobilizes; The address of DRAM is another part of unified addressing, can dynamic change.Notice that the address realm A of cache DRAM is 0～X herein, the maximum address that X is DRAM, address realm A dynamically adjusts according to the characteristic of upper strata request.For example, if request is to read to write few type more, A will diminish, and directly allows read request occur on nonvolatile memory; On the contrary, if request is to read to write less many types, A can become greatly, also utilizes more DRAM to serve as the cache of nonvolatile memory, to cover its writing rate, and improves the life-span.
Two, merge memory system hardware platform
Employing includes but not limited to the embedded-development environment of the processor such as ARM, FPGA, merge memory system in these platform deploy, make processor identify and access fusion internal memory in the mode of internal memory, realize the fusion memory system based on nonvolatile memory and DRAM.
(1) hardware platform overall architecture
As shown in Figure 2, hardware platform overall architecture comprises with next several parts:
Processor module, includes but not limited to the processor such as ARM, FPGA;
Multiple internal memory physical interfaces, for providing the signaling protocol that meets memory techniques standard.Above-mentioned memory interface technical standard can be existing memory interface technical standard, as DDR2, and DDR3 etc.In these internal memory physical interfaces, reserve the memory interface that design system must be used, the I/O mouths that used as the corresponding internal memory of processor control etc., also will reserve and merge nonvolatile memory and the needed memory interface of DRAM device in memory system.
SD card interface module, is configured and is started processor system by SD card;
Universal serial port turns usb interface module, and debugging serial port function is provided;
PCIe interface module, according to user's request and self-defined, supports PCIe series (comprising a PCIe generation, multiple passage configuration under two generations) physical layer protocol, and this hardware platform is communicated with host interface with the PCIe interface (PCIe2.0X8) of definition;
Power supply adaptor module, supporting with ATX power interface, multiple adaptive I/O mouth level can be provided, as 1.2V, 1.5V, 1.8V, 2.5V, 3.3V etc. are provided;
Clock management module, for generation of the needed clock of corresponding module.
(2) nonvolatile memory merges internal memory hardware
Nonvolatile memory merges the concrete framework of internal memory hardware as shown in Figure 3, its mentality of designing is as follows: take certain serial nonvolatile memory chip as basis, design and make nonvolatile memory and merge internal memory, this internal memory hardware interface type is followed the memory standard signaling protocol that mainboard internal memory physical interface adopts, corresponding standard physical interface is provided, can be connected in memory interface with set form, support the DRAM internal memory hardware of same standard agreement simultaneously, by the work of merging memory management and merging Memory Controller Hub, make processor to access nonvolatile memory storer and DRAM storer according to the access mode of internal memory, realize the fusion memory system based on nonvolatile memory and dynamic randon access.
Wherein, because the interface protocol of internal storage access is standard agreement, and current nonvolatile memory phy chip on the market has not all adopted the communication protocol consistent with memory standard.Therefore,, in order to realize memorymodel access nonvolatile memory, need between the protocol memory that memory interface module adopts in nonvolatile memory chip package interface protocol and hardware plan overall architecture, change, or complete compatibility.For this reason, this fusion internal memory hardware comprises a protocol conversion module, for the protocol memory that the protocol conversion of nonvolatile memory phy chip package interface is adopted for memory interface.
Meanwhile, level between distinct interface agreement need to be isolated and be changed (if the support level of the LPDDR2 of Micron Technology Series PC M chip is 1.2V, P8P series is 3.3V, and the level of DDR3 agreement support is 1.5V, the level of DDR2 agreement support is 1.8V), therefore, preferably, this fusion internal memory hardware also comprises a level switch module, completes level isolation and conversion between distinct interface agreement.
The concrete form of non-volatile memory hardware can be memory bar, selected nonvolatile memory chip according to demand, composition storage array; Also can be the form of inserting subcard in master card, on each subcard, can adopt multi-disc, formed certain capacity solid-state storage space, in subcard, each nonvolatile memory chip is an independent passage, and the operation such as the read-write between multiple subcards can complete parallel.
(3) merge Memory Controller Hub
As traditional Memory Controller Hub, merge Memory Controller Hub according to the work schedule of nonvolatile memory and DRAM phy chip, upper strata call instruction and pin level signal condition, worker state machine is set to complete corresponding operation, and the software interface that drives memory chip is provided.The hardware aspect of Memory Controller Hub, according to merging the state machine of memory chip work and the order that call on current upper strata, completes corresponding operating; The software aspect of Memory Controller Hub, provides the function interface to merging each orders such as memory system read-write.In Memory Controller Hub, the specific design of state machine is the state of the art, does not repeat them here.
Three, merge memory management module
For nonvolatile memory and the different internal memory of DRAM two classes, merge memory management module and need to consider layout and the migration of data, according to the relative merits of two class storeies, rationally place data, make the internal storage data of depositing in nonvolatile memory and DRAM have certain difference, very fast to embody DRAM access rate, the feature that PCM is non-volatile, to crucial data consistent metadata information reliably as high in needs, start and need configuration information fast, read-only system information is directly placed in nonvolatile memory.Rationally utilize both storage spaces simultaneously, internal memory Cache using part DRAM as nonvolatile memory, often the data placement of access is in DRAM, nonvolatile memory is as the rear end storage of DRAM, utilize the fast feature of DRAM access speed, cover the long shortcoming of write delay of nonvolatile memory, and reduced the number of times of writing of nonvolatile memory, be beneficial to non-volatile storage life and the restriction of writing energy consumption.Also given play to the non-volatile characteristic of nonvolatile memory power down, data consistency is good, persistence internal storage data simultaneously.
As shown in Figure 4, in the embodiment of the present invention, merge memory management module and carry out unified management to merging internal memory, comprise cold and hot data identification submodule, Data Migration submodule, initialization submodule, read-write requests scheduling sublayer module, address mapping submodule, wear leveling submodule etc.
Cold and hot data identification submodule: the cold and hot property that judges visit data according to access frequency and access time.Wherein, consider the temperature of data itself, the many factors such as the principle of locality while considering routine access again, for nonvolatile memory used, dispose cold and hot data identification mechanism;
Data Migration submodule: according to the recognition result of cold and hot data, the data of cold data will be identified as in DRAM, move in DRAM cache or NVM and (specifically decide according to the characteristic of selected NVM the Data Migration direction that is identified as cold data by DRAM), by be identified as the data of dsc data in DRAM cache, move in DRAM.Such advantage is, make full use of the fast advantage of read-write speed of DRAM, reduce the time of Data Migration operation and postpone expense, simultaneously in the time that data are moved in succession between the two, do not have real being written in nonvolatile memory, reduce writing of redundancy in nonvolatile memory device or unnecessary data, be conducive to the life-span of nonvolatile memory;
Initialization submodule: when system initialization for the first time, predetermined critical data (as system starts required information, needs high consistent metadata information reliably) is imported in nonvolatile memory.In the time of follow-up operation, critical data also leaves in nonvolatile memory, is like this started and carried out fast the next time that makes system, and no longer need again to import log-on message.
Read-write requests scheduling sublayer module: after upper strata request is assigned, determine the address that issues of request according to request characteristic, then request command is issued to fusion Memory Controller Hub, finally arrive the corresponding internal memory that merges.Described request characteristic comprises read-write type ratio, request load characteristic etc.
Address mapping submodule: maintain unified address mapping table for merging memory system.This table leaves in nonvolatile memory, and the logical address and the physical address that merge internal memory are separated, and is convenient to carry out abrasion equilibrium and the read-write requests scheduling of nonvolatile memory device.
Abrasion equilibrium submodule: the read-write number of times of monitoring nonvolatile memory, divides timing to utilize Address Mapping to realize the abrasion equilibrium of nonvolatile memory carrying out upper strata request.Preferably, can also take into account in nonvolatile memory region Mobile state abrasion equilibrium, as periodically read and write the exchange of thermal region address.Be specially: what the each region of statistics nonvolatile memory occurred reads number of times and write number of times, between the frequent read operation region that I/O occurs and write operation region, carry out data, address displacement.
Preferably, merge memory management module and also comprise performance optimization submodule: carry out optimisation strategy according to the characteristic of nonvolatile memory, comprise reduction write delay, write time-out and write cancellation etc.Wherein, because nonvolatile memory is larger with respect to the write delay of DRAM, and the life-span of nonvolatile memory is limited, therefore to merging the performance optimization mechanism of memory system mainly for write performance optimization, the energy optimization etc. of nonvolatile memory device, and solving to greatest extent the restriction of nonvolatile memory at aspects such as life-span, write operation delay and energy consumptions, Integral lifting merges the performance of memory system.
Further, merge memory management module and also comprise that dram space capacity dynamically adjusts submodule: periodically monitor the hit rate H of DRAM cache part, and detect read-write requests ratio R:
R=read request number ÷ write request number (1)
When hit rate H < K(K is a predetermined threshold, its value can be according to user's request and self-defined configuration, 0<K<1) and (T is a predetermined threshold when read-write requests ratio R<T, its value can be according to user's request and self-defined configuration, 0<T<1), increase DRAM cache capacity.Concrete operations are that the DRAM of unified addressing is rejected to space, subregion, and be addressed in DRAM cache, the amount of capacity increasing is that doubly (γ is the volume change factor for the γ of former DRAM cache capacity, 0< γ <1, this value can also be configured by User Defined);
In the time of hit rate H >=K and read-write requests ratio R >=T, reduce DRAM cache capacity.Concrete operations are that the segment space in DRAM cache is addressed in the unified addressing that merges internal memory, the amount of capacity reducing is that doubly (θ is the volume change factor for the θ of former DRAM cache capacity, 0< θ <1, this value can also be configured by User Defined).
As can be seen here, this memory system is emphasized the fusion of nonvolatile memory and DRAM, the status and the effect that are both are no longer the memory architecture that simple mixed architecture or individual course exist, but " fusion architecture ", be that nonvolatile memory and DRAM form unified internal memory jointly, wherein DRAM will unify space addressing with nonvolatile memory, meanwhile in DRAM, mark off segment space and be the buffer memory cache of nonvolatile memory; According to the difference of the factors such as data payload feature, the capacity that serves as the cache segment space of nonvolatile memory in DRAM is dynamically configurable; Load characteristic is had to perception, flexible configuration DRAM cache amount of capacity, to improve the hit rate of DRAM cache, improves the performance that merges memory system.
It is pointed out that the adjustment of DRAM capacity likely become two extreme: 1. parallel construction: all DRAM all with nonvolatile memory unified addressing, no longer serve as the cache of nonvolatile memory, as shown in Figure 5; 2. vertical stratification: all DRAM have served as the cache of nonvolatile memory, nonvolatile memory is as the rear end exented memory of DRAM, as shown in Figure 6.
Finally it may be noted that the nonvolatile memory that merges memory system in the embodiment of the present invention can be the storer based on phase transition storage, can be also that storer based on NAND FLASH or other can be as the nonvolatile memorys of internal memory.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a fusion memory system for nonvolatile memory and dynamic RAM, comprising:
The nonvolatile memory (NVM) of unified addressing, unified management and dynamic RAM (DRAM), wherein DRAM comprises the DRAM cache part of the cache that serves as nonvolatile memory, its spatial content capable of dynamic is adjusted;
Protocol conversion module, for the protocol memory that the protocol conversion of nonvolatile memory phy chip package interface is adopted for memory interface;
Merge Memory Controller Hub, for according to the work schedule of nonvolatile memory and DRAM phy chip, upper strata call instruction and pin level signal condition, worker state machine is set to complete corresponding operation, and the software interface that drives memory chip is provided;
Merge memory management module, for carrying out unified management to merging internal memory, comprise that dram space capacity dynamically adjusts submodule, wherein, described dram space capacity is dynamically adjusted submodule for periodically monitoring the hit rate H of DRAM cache part, and detects read-write requests ratio R:
R=read request number ÷ write request number (1)
In the time of hit rate H < K and read-write requests ratio R<T, increase DRAM cache capacity, wherein, K, T are predetermined threshold, its value can be according to user's request and self-defined configuration, 0<K<1,0<T<1;
In the time of hit rate H >=K and read-write requests ratio R >=T, reduce DRAM cache capacity.
2. fusion memory system according to claim 1, also comprises level switch module, for completing level isolation and the conversion between distinct interface agreement.
3. fusion memory system according to claim 1, wherein, described fusion memory management module also comprises cold and hot data identification submodule and Data Migration submodule, and described cold and hot data identification submodule is for judging the cold and hot property of visit data according to access frequency and access time; Described Data Migration submodule, for according to the recognition result of cold and hot data, will be identified as the data of cold data in DRAM, moves in DRAM cache or NVM, by be identified as the data of dsc data in DRAM cache, moves in DRAM.
4. fusion memory system according to claim 1, wherein, described fusion memory management module also comprises initialization submodule, for predetermined critical data (as system starts required information, needs high consistent metadata information reliably) being imported to nonvolatile memory when the system initialization for the first time.
5. fusion memory system according to claim 1, wherein, described fusion memory management module also comprises read-write requests scheduling sublayer module: after upper strata request is assigned, determine the address that issues of request according to request characteristic, then request command is issued to fusion Memory Controller Hub, finally arrives the corresponding internal memory that merges.
6. fusion memory system according to claim 1, wherein, described fusion memory management module also comprises address mapping submodule, is used to fusion memory system to maintain unified address mapping table.
7. fusion memory system according to claim 1, wherein, described fusion memory management module also comprises abrasion equilibrium submodule, for monitoring the read-write number of times of nonvolatile memory, divides timing to utilize Address Mapping to realize the abrasion equilibrium of nonvolatile memory carrying out upper strata request.
8. fusion memory system according to claim 7, wherein, described abrasion equilibrium submodule is also for adding up the each region of nonvolatile memory occurs read number of times and write number of times, between the frequent read operation region that I/O occurs and write operation region, carries out data, address displacement.
9. fusion memory system according to claim 1, wherein, described fusion memory management module also comprises performance optimization submodule, for carrying out optimisation strategy according to the characteristic of nonvolatile memory, comprises reduction write delay, writes time-out and write cancellation.
10. fusion memory system according to claim 1, wherein, described nonvolatile memory is that the storer based on phase transition storage (PCM), the storer based on NAND FLASH or other can be as the nonvolatile memorys of internal memory.
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