CN114253461A

CN114253461A - Mixed channel memory device

Info

Publication number: CN114253461A
Application number: CN202011017708.XA
Authority: CN
Inventors: 孙明浩
Original assignee: Chengdu Starblaze Technology Co ltd
Current assignee: Chengdu Starblaze Technology Co ltd
Priority date: 2020-09-24
Filing date: 2020-09-24
Publication date: 2022-03-29

Abstract

A mixed channel memory device is provided. The provided mixed channel memory device includes a control unit and an NVM chip. A control component comprising a media interface controller for coupling a plurality of NVM chips; the media interface controller is coupled to the plurality of NVM chips via a plurality of channels; a first channel of the plurality of channels is coupled to a plurality of NVM chips; a first NVM chip of the plurality of NVM chips is of a first type and a second NVM chip of the plurality of NVM chips is of a second type; wherein the first type is different from the second type; the medium interface controller comprises a micro-instruction storage unit, a micro-instruction execution unit and a signal driver; the microinstruction execution unit executes a sequence of microinstructions to operate the signal driver to provide signals to the plurality of channels.

Description

Mixed channel memory device

Technical Field

The present application relates to a memory device technology, and more particularly, to a memory device having a hybrid channel, a controller thereof, and a method of providing a hybrid channel.

Background

FIG. 1 illustrates a block diagram of a storage device. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high speed Peripheral Component Interconnect), NVMe (NVM Express, high speed nonvolatile storage), ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), XPoint Memory, and the like are common NVM.

The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

Control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to an interface protocol of NVM chip 105 to operate NVM chip 105 and receive command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc. Chinese patent application No. 201510253428.1 entitled "microinstruction sequence execution method and apparatus thereof" provides an example of a media interface controller that applies storage media access commands to NVM chips by executing microinstructions. Chinese patent application No. 2020106080147 entitled "adaptive NVM read method and apparatus thereof", chinese patent application No. 202010615178.2 ", chinese patent application No. 202010207004.2", chinese patent application No. media interface controller and storage controller for read command fusion, chinese patent application No. 201810380329.3, chinese patent application No. method and apparatus for executing NVM commands out of order ", chinese patent application No. 201610836531.3, chinese patent application No. method and apparatus for generating NVM chip interface commands".

An NVM chip includes one or more Logical Units (LUNs). One or more dies (Die) may be included within the NVM chip package. Typically, a logic cell corresponds to a single die. The logical unit may include a plurality of planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within an NVM chip may execute commands and report status independently of each other. The meaning for target, logical Unit, Plane (Plane) is provided in "Open NAND Flash Interface Specification (Revision 3.0)" available from http:// www.micron.com// media/Documents/Products/Other% 20Documents/ONFI3_0gold. ashx, which is part of the prior art. In this application, the use of Target (Target) and Logical Unit (LUN) is interchangeable unless otherwise indicated.

NVM chips typically store and read data on a page basis. And data is erased in blocks. A block (also referred to as a physical block) contains a plurality of pages (also referred to as physical pages). The physical page has a fixed size, e.g., 17664 bytes. Physical pages may also have other sizes.

In the storage device, mapping information from logical addresses to physical addresses is maintained by using a Flash Translation Layer (FTL). The logical addresses constitute storage space of the storage device as perceived by upper level software, such as an operating system. The physical address is an address for accessing a physical memory location of the memory device. Address mapping may also be implemented using an intermediate address modality in the related art. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address.

A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in storage devices. Usually, the data entry of the FTL table records the address mapping relationship in the unit of data page in the storage device.

The FTL of some memory devices is provided by a host to which the memory device is coupled, the FTL table is stored by a memory of the host, and the FTL is provided by software executed by a processor of the host. Still other storage management devices disposed between hosts and storage devices provide FTLs.

Fig. 2 shows a detailed block diagram of the control part of the storage device.

Hosts access storage devices with IO commands that follow a storage protocol. The control component generates one or more storage commands according to the IO commands from the host and provides the storage commands to the media interface controller. The media interface controller generates storage media access commands (e.g., program commands, read commands, erase commands) in accordance with the interface protocol of the NVM chip in accordance with the storage commands. The control unit also tracks that all storage commands generated from one IO command are executed and indicates the processing result of the IO command to the host.

Referring to fig. 2, the control means includes, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface acquires the IO command provided by the host, generates a storage command and provides the storage command to the storage command processing unit. The storage command accesses, for example, a storage space of the same size, for example, 4 KB. A data unit recorded in the NVM chip corresponding to data accessed by one storage command is referred to as a data frame. A physical page records one or more frames of data. For example, a physical page is 17664 bytes in size, and a data frame is 4KB in size, then one physical page can store 4 data frames.

The storage medium management unit maintains a logical to physical address translation for each storage command. For example, the storage medium management unit includes an FTL table. For a read command, the storage medium management unit outputs a physical address corresponding to a logical address accessed by the storage command, for a write command, the storage medium management unit allocates an available physical address to the storage medium management unit, and records a mapping relation between the accessed logical address and the allocated physical address. The storage medium management unit also maintains functions such as garbage collection, wear leveling, etc. required to manage the NVM chips.

The storage command processing unit operates the media interface controller to send a storage media access command to the NVM chip according to the physical address provided by the storage media management unit. For clarity, commands sent by the storage command processing unit to the media interface controller are referred to as media interface commands, while commands sent by the media interface controller to the NVM chip are referred to as storage media access commands. The storage medium access commands follow the interface protocol of the NVM chip.

Fig. 3 illustrates a media interface controller.

The medium interface controller comprises a micro instruction memory, a micro instruction execution unit and a signal driver. The media interface controller is also coupled to the NVM chip. The media interface controller provides the storage media access command to the NVM chip and obtains a processing result of the storage media access command. The micro instruction memory stores micro instruction sequences.

The media interface controller receives the media interface command (shown as CMD in fig. 3) provided by the storage command process. The micro instruction sequence corresponds to the medium interface command, and the medium interface controller obtains the corresponding micro instruction sequence according to the received medium interface command and provides the micro instruction sequence to the micro instruction execution unit. The micro-instruction execution unit executes the micro-instruction sequence, drives the signal driver according to the signals indicated by the micro-instruction sequence, and generates specified signals on the leads coupled with the NVM chip by the medium interface. And generating a signal sequence conforming to an interface protocol of the NVM chip by executing the micro instruction sequence. The signal driver also collects signals from the leads, e.g., data read from the NVM chip from the DQ leads.

There are various types of NVM chips. Various types of NVM chips are, for example, from different vendors, conform to different NVM chip interface protocols (e.g., "Toggle," "ONFI," etc.), provide different characteristics for different application scenarios (e.g., low latency, large capacity, high endurance, etc.).

The media interface controller is coupled to the NVM chip through a channel (channel). To increase storage density and balance the pin count of the controller chip, it is common to couple, for example, 2 or more NVM chips in a single lane (or to a lane in LUNs or Target units). Multiple Target shared buses (including a control bus and a data bus) coupled to the same channel to reduce the number of pins used to couple the NVM chip to the media interface controller. A lane provides each Target coupled to the lane with its own dedicated Chip Enable (CE) signal to avoid transmitting signals to more than one Target at any time.

The NVM chips coupled to the same channel are typically of the same type so that the media interface controller operates all NVM chips in the same manner.

Disclosure of Invention

Some application systems require the use of different types of NVM chips to meet varying performance requirements. For example, a CDN (content delivery network) needs better read performance, while an enterprise-level application needs higher data reliability. Inside memory devices, the need for a variety of NVM chip types is also growing. For example, for critical metadata of a storage device, access (read and/or write) that can be low latency is required; for storage devices with the ability to distinguish between cold/hot data, it is desirable that the storage medium for cold data has better retention (retention) and the storage medium for hot data has better Endurance (Endurance) and/or access latency. Thus, a need has arisen for coupling different types of NVM chips on the same control unit within a memory device. Further, it is desirable to couple different types of NVM chips on the same channel. However, when NVM chips on the same channel share a bus, and the types of the NVM chips are different, it is likely that driving one NVM chip will not drive another NVM chip effectively, which presents challenges to the media interface controller.

Coupling different types of NVM chips on the same control unit also presents challenges for storage media management. There is a need to distinguish between the memory space provided by different NVM chips and it is also desirable to keep the technical complexity low for the introduction of new functionality.

According to a first aspect of the present application, there is provided a first control means according to the first aspect of the present application, comprising a media interface controller for coupling a plurality of NVM chips; the media interface controller is coupled to the plurality of NVM chips via a plurality of channels; a first channel of the plurality of channels is coupled to a plurality of NVM chips; a first NVM chip of the plurality of NVM chips is of a first type and a second NVM chip of the plurality of NVM chips is of a second type; wherein the first type is different from the second type.

According to a first control means of the first aspect of the present application, there is provided a second control means according to the first aspect of the present application, wherein the first type is an SLC type and the second type is a TLC type.

The third control means according to the first aspect of the present application is provided according to the first or second control means of the first aspect of the present application, wherein a second channel of the plurality of channels is coupled to a second plurality of NVM chips; a third NVM chip of the second plurality of NVM chips is of a third type and a fourth NVM chip of the second plurality of NVM chips is of a fourth type; wherein the third type is different from the fourth type.

According to a first control component of the first aspect of the present application, there is provided the fourth control component of the first aspect of the present application, wherein the media interface controller includes a signal driver through which signals are supplied to the plurality of channels.

According to one of the first to fourth controlling means of the first aspect of the present application, there is provided the fifth controlling means of the first aspect of the present application, wherein the media interface controller further comprises a plurality of NVM configuration register sets, each including a plurality of registers storing characteristics of the NVM chip.

According to a fifth controlling means of the first aspect of the present application, there is provided the sixth controlling means of the first aspect of the present application, wherein the set of NVM configuration registers comprises a time constraint configuration register, an address format configuration register, a data length configuration register and/or a command format configuration register.

According to a fifth or sixth controlling means of the first aspect of the present application, there is provided the seventh controlling means according to the first aspect of the present application, wherein the characteristic of the type of the NVM chip to be accessed is obtained from the corresponding NVM configuration register set according to the type of the NVM chip to be accessed; the signal driver provides signals to the NVM chip to be accessed through a channel according to the obtained characteristics.

According to a seventh control component of the first aspect of the present application, there is provided the eighth control component of the first aspect of the present application, wherein the media interface controller further comprises a plurality of cache units; data read from the first NVM chip is stored in a first cache cell of the plurality of cache cells; data to be written to the second NVM chip is also stored in the first cache unit.

According to an eighth controlling means of the first aspect of the present application, there is provided the ninth controlling means of the first aspect of the present application, wherein the first NVM chip acts as a cache for the second NVM chip.

According to one of the first to ninth control means of the first aspect of the present application, there is provided the tenth control means according to the first aspect of the present application, wherein the medium interface controller includes a microinstruction storage unit, a microinstruction execution unit, and a signal driver; the microinstruction execution unit executes a sequence of microinstructions to operate the signal driver to provide signals to the plurality of channels.

According to a tenth control unit of the first aspect of the present application, there is provided the eleventh control unit of the first aspect of the present application, wherein the microinstruction memory stores a plurality of microinstruction sequences; the plurality of micro instruction sequences comprise a micro instruction sequence used for processing a medium interface command and a plurality of micro instruction sequences used for providing a storage medium access command for the NVM chip; and executing the micro instruction sequence for processing the medium interface command, and calling the micro instruction sequence corresponding to the medium interface command and used for providing a storage medium access command for the NVM chip.

According to an eleventh controlling means of the first aspect of the present application, there is provided the twelfth controlling means of the first aspect of the present application, wherein the plurality of microinstruction sequences for providing storage medium access commands to NVM chips comprises microinstruction sequences for providing program commands to NVM chips of the first type and microinstruction sequences for providing program commands to NVM chips of the second type.

According to an eleventh or twelfth controlling means of the first aspect of the present application, there is provided the thirteenth controlling means of the first aspect of the present application, wherein the microinstruction execution unit further comprises a plurality of NVM configuration register sets, each including a plurality of registers storing characteristics of the NVM chip; executing the micro instruction sequence for processing the media interface command also sets a type flag; the microinstruction execution unit accesses one of the plurality of NVM configuration register sets according to the type tag and operates the signal driver to provide signals to the plurality of channels using the characteristic of the NVM chip obtained by accessing the one of the plurality of NVM configuration register sets.

According to a thirteenth control unit of the first aspect of the present application, there is provided the fourteenth control unit of the first aspect of the present application, wherein the microinstruction execution unit further comprises a microinstruction decoder and a plurality of signal generation units; the micro-instruction decoder provides the micro-instruction to one of the plurality of signal generating units according to the meaning of the micro-instruction; the microinstruction decoder further selects a plurality of registers of one of the plurality of NVM configuration register sets to provide to one or more of the plurality of signal generation units based on the type tag; the signal generating unit operates the signal driver to provide a signal to one of the plurality of channels according to the microinstructions provided by the microinstruction decoder and the characteristics retrieved from the one of the plurality of NVM configuration register sets.

According to a fourteenth control section of the first aspect of the present application, there is provided the fifteenth control section of the first aspect of the present application, wherein the plurality of signal generating units includes a command signal generating unit, an address signal generating unit, and/or a data transmission signal generating unit; the command signal generating unit generates a command header of a storage medium access command according to the microinstruction, and also acquires time constraint information from a time constraint configuration register of the NVM configuration register set to generate an ALE signal and/or a CLE signal on the channel.

According to a fourteenth or fifteenth controlling means of the first aspect of the present application, there is provided the sixteenth controlling means according to the first aspect of the present application, wherein the address signal generating unit generates the address part of the storage medium access command according to the microinstruction, and further acquires the address format from the address format configuration register of the NVM configuration register set to generate the DQ signal over the channel for a plurality of cycles.

According to one of the fourteenth to sixteenth control units according to the first aspect of the present application, there is provided the seventeenth control unit according to the first aspect of the present application, wherein the data transfer signal generation unit generates the data portion of the storage medium access command according to the microinstruction, and further acquires the data length from the data length configuration register of the NVM configuration register set to generate the DQ signal for the specified number of cycles on the channel.

According to one of the tenth to seventeenth controlling means of the first aspect of the present application, there is provided the eighteenth controlling means of the first aspect of the present application, wherein the medium interface controller includes one or more buffer units for buffering data read out from or to be written to one of the plurality of NVM chips; the microinstruction execution unit executes a microinstruction sequence used for copying operation to provide a read command to the first NVM chip, record the read data in a first cache unit, and provide a programming command to the second NVM chip to write the data of the first cache unit into the second NVM chip.

According to an eighteenth control component of the first aspect of the present application, there is provided the nineteenth control component of the first aspect of the present application, wherein the media interface controller calls a microinstruction sequence for the copy operation in response to recognizing the media interface command indicating the move operation.

According to an eighteenth or nineteenth controlling means of the first aspect of the present application, there is provided the twentieth controlling means according to the first aspect of the present application, wherein the first NVM chip acts as a cache for the second NVM chip; the media interface controller also includes a block mapping table whose entries record, in association, the blocks of the second NVM chip and one or more blocks of the first NVM chip.

According to a twentieth controlling means of the first aspect of the present application, there is provided the twenty-first controlling means of the first aspect of the present application, wherein in response to receiving a first media interface command indicating to write data to a first block of the second NVM chip, accessing the block mapping table for a second block of the first NVM chip associated with the first block; writing write data indicated by the first media interface command to the second block by a sequence of microinstructions for providing a program command to the first type of NVM chip.

According to a twenty-first controlling means of the first aspect of the present application, there is provided the twenty-second controlling means of the first aspect of the present application, wherein in response to receiving a first media interface command indicating to write data to the first block of the second NVM chip, recording in the block mapping table that the first block is associated with the second block of the first NVM chip.

According to a twenty-first or twenty-second controlling means of the first aspect of the present application, there is provided the twenty-third controlling means of the first aspect of the present application, wherein the write data size indicated by the first media interface command is a physical page size of the first block; and when a micro instruction sequence used for providing a programming command for the NVM chip of the first type is executed, acquiring a conversion mode of a physical page address of the second NVM chip and a physical page address of the first NVM chip through an address format configuration register of an NVM configuration register group corresponding to the same type mark, and generating the physical page address of the second block.

According to one of the twenty-first to twenty-third control sections of the first aspect of the present application, there is provided the twenty-fourth control section of the first aspect of the present application, wherein data of the second block is copied to the first block by executing a micro instruction sequence for a copy operation according to an association relationship of the first block and the second block recorded by a block mapping table; and clearing the association relation between the first block and the second block in a block mapping table.

According to one of the twenty-first to twenty-fourth controlling means of the first aspect of the present application, there is provided the twenty-fifth controlling means of the first aspect of the present application, wherein in response to receiving a second media interface command indicating to write data to a third block of the second NVM chip, accessing the block mapping table results in the third block not having a record in the block mapping table; writing write data indicated by the second media interface command to the third block by a sequence of micro-instructions for providing a program command to the NVM chip of the second type.

According to one of the tenth to twenty-fifth control elements of the first aspect of the present application, there is provided the twenty-sixth control element of the first aspect of the present application, wherein the media interface controller comprises a scheduler for scheduling a plurality of threads to be executed by the microinstruction execution unit, wherein a sequence of microinstructions being executed, together with their state, is referred to as a thread; a first plurality of threads of the plurality of threads correspond one-to-one with the LUNs of the plurality of NVM chips, each of the first plurality of threads corresponding to a microinstruction sequence for providing storage medium access commands to the NVM chips.

According to a twenty-sixth controlling means of the first aspect of the present application, there is provided the twenty-seventh controlling means of the first aspect of the present application, wherein a second thread of the plurality of threads corresponds to a LUN of the first NVM chip to which data is to be copied and a LUN of the second NVM chip, the second thread being a sequence of microinstructions applied to the copy operation.

According to a twenty-sixth control component of the first aspect of the present application, there is provided the twenty-eighth control component of the first aspect of the present application, wherein the media interface controller schedules the first thread and the second thread, both of which are assigned the first cache unit, in response to recognizing the media interface command indicating the move operation; the first thread reads data from the first NVM chip according to a micro-instruction sequence for providing a read command to the NVM chip and records the data in a first cache unit; the second thread writes the data of the first cache unit to the second NVM chip according to a micro instruction sequence for providing a program command to the NVM chips.

According to a twenty-eighth controlling means of the first aspect of the present application, there is provided the twenty-ninth controlling means of the first aspect of the present application, wherein the second thread yields in response to data to be written to the second NVM chip not having been recorded in the first buffer unit; and/or scheduling the second thread in response to data to be written to the second NVM chip being recorded in the first cache location.

According to a second aspect of the present application, there is provided a memory device according to the second aspect of the present application, comprising a control section and a plurality of NVM chips; wherein the control means is one of the first to twenty-ninth control means according to the first aspect of the present application.

According to a third aspect of the present application, there is provided a first media interface command processing method according to the third aspect of the present application, including: acquiring a medium interface command, and identifying the type of an NVM chip to be accessed by a medium interface; obtaining the characteristics of the NVM chip to be accessed according to the identified type; and generating a storage medium access command for accessing the NVM chip according to the acquired characteristics.

According to a first media interface command processing method of a third aspect of the present application, there is provided a second media interface command processing method of the third aspect of the present application, wherein in response to the type being a first type, a first microinstruction sequence corresponding to the first type is executed; and the first micro instruction sequence acquires the characteristics in the execution process and generates a storage medium access command for accessing the NVM chip according to the acquired characteristics.

According to a first media interface command processing method of the third aspect of the present application, there is provided a third media interface command processing method of the third aspect of the present application, wherein in response to the media interface command indicating a first operation, a first microinstruction sequence corresponding to the first operation is executed; and the first micro instruction sequence acquires the characteristics in the execution process and generates a storage medium access command for accessing the NVM chip according to the acquired characteristics.

According to the second or third media interface command processing method of the third aspect of the present application, there is provided the fourth media interface command processing method of the third aspect of the present application, wherein according to the identified type, a characteristic of a type of the NVM chip to be accessed is obtained from an NVM configuration register set corresponding to the type; wherein the set of NVM configuration registers includes a time constraint configuration register, an address format configuration register, a data length configuration register, and/or a command format configuration register that store characteristics of the NVM chip.

According to one of the second to fourth media interface command processing methods of the third aspect of the present application, there is provided a fifth media interface command processing method according to the third aspect of the present application, wherein executing a microinstruction sequence for processing a media interface command analyzes the media interface command, and invokes the first microinstruction sequence; wherein executing the sequence of microinstructions for processing the media interface command further identifies a type of the NVM chip to be accessed by the media interface; and executing the first micro-instruction sequence to acquire the characteristics of the type of the accessed NVM chip from the NVM configuration register group corresponding to the type.

According to one of the second to fifth media interface command processing methods of the third aspect of the present application, there is provided the sixth media interface command processing method of the third aspect of the present application, wherein the first microinstruction sequence includes a microinstruction that generates a command header of a storage media access command, a microinstruction that generates an address of the storage media access command, and/or a microinstruction that generates data of the storage media access command.

According to a sixth media interface command processing method of the third aspect of the present application, there is provided the seventh media interface command processing method of the third aspect of the present application, wherein the microinstruction that generates the command header of the storage media access command is executed, the command header of the storage media access command is generated, and the time constraint information is further obtained from the time constraint configuration register of the NVM configuration register set to generate the command header ALE signal and/or CLE signal for the storage media access command on the channel.

According to a sixth or seventh media interface command processing method of the third aspect of the present application, there is provided the eighth media interface command processing method of the third aspect of the present application, wherein the microinstruction that generates the address of the storage media access command is executed, and the address format is obtained from the address format configuration register of the NVM configuration register set to generate a plurality of cycles of DQ signals for the address of the storage media access command on the channel.

According to one of the sixth to eighth media interface command processing methods of the third aspect of the present application, there is provided the ninth media interface command processing method of the third aspect of the present application, wherein the microinstruction that generates data of the storage medium access command is executed, and the data length is obtained from the data length configuration register of the NVM configuration register set to generate the DQ signal for the specified number of cycles on the channel.

According to one of the first to ninth media interface command processing methods of the third aspect of the present application, there is provided the tenth media interface command processing method of the third aspect of the present application, wherein in response to acquiring a media interface command instructing to move data from the NVM chip of the first type to the NVM chip of the second type, a microinstruction sequence for a copy operation is executed to provide a read command to the first NVM chip, record the read data in the first cache unit, and provide a program command to the second NVM chip to write the data of the first cache unit to the second NVM chip.

According to a tenth media interface command processing method of the third aspect of the present application, there is provided the eleventh media interface command processing method of the third aspect of the present application, wherein the first NVM chip serves as a cache of the second NVM chip; and recording the block of the second NVM chip in association with one or more blocks of the first NVM chip in an entry of a block mapping table.

According to an eleventh media interface command processing method of the third aspect of the present application, there is provided the twelfth media interface command processing method of the third aspect of the present application, wherein in response to receiving a first media interface command instructing to write data to a first block of the second NVM chip, accessing the block mapping table to obtain a second block of the first NVM chip associated with the first block; writing write data indicated by the first media interface command to the second block by a sequence of microinstructions for providing a program command to the first type of NVM chip.

According to a twelfth media interface command processing method of the third aspect of the present application, there is provided the thirteenth media interface command processing method of the third aspect of the present application, wherein in response to receiving a first media interface command instructing to write data to the first block of the second NVM chip, recording that the first block is associated with the second block of the first NVM chip in the block mapping table.

According to a twelfth or thirteenth media interface command processing method of the third aspect of the present application, there is provided the fourteenth media interface command processing method of the third aspect of the present application, wherein the write data size indicated by the first media interface command is a physical page size of the first block; and when a micro instruction sequence used for providing a programming command for the NVM chip of the first type is executed, acquiring a conversion mode of a physical page address of the second NVM chip and a physical page address of the first NVM chip through an address format configuration register of an NVM configuration register group corresponding to the same type mark, and generating the physical page address of the second block.

According to one of the twelfth to fourteenth media interface command processing methods of the third aspect of the present application, there is provided the fifteenth media interface command processing method of the third aspect of the present application, wherein data of the second block is copied to the first block by executing a microinstruction sequence for a copy operation according to an association relationship between the first block and the second block recorded by a block mapping table; and clearing the association relation between the first block and the second block in a block mapping table.

According to one of the twelfth to fifteenth media interface command processing methods of the third aspect of the present application, there is provided the sixteenth media interface command processing method of the third aspect of the present application, wherein in response to receiving a second media interface command instructing to write data to a third block of the second NVM chip, accessing the block mapping table results in the third block having no record in the block mapping table; writing write data indicated by the second media interface command to the third block by a sequence of micro-instructions for providing a program command to the NVM chip of the second type.

According to one of the first to sixteenth media interface command processing methods of the third aspect of the present application, there is provided a seventeenth media interface command processing method according to the third aspect of the present application, further comprising: scheduling a plurality of threads, wherein the sequence of microinstructions executed along with their state are referred to as threads; the first plurality of threads in the plurality of threads correspond to the LUNs of the NVM chip one-to-one, and each of the first plurality of threads corresponds to a microinstruction sequence for providing a storage medium access command to the NVM chip.

According to one of the seventeenth media interface command processing method of the third aspect of the present application, there is provided the eighteenth media interface command processing method of the third aspect of the present application, wherein a second thread of the plurality of threads corresponds to a LUN of the first NVM chip to which the data is to be copied and a LUN of the second NVM chip, and the second thread is for a microinstruction sequence to be applied to the copy operation.

According to one of seventeenth media interface command processing methods according to the third aspect of the present application, there is provided a nineteenth media interface command processing method according to the third aspect of the present application, wherein in response to recognition of a media interface command instructing a move operation, a first thread and a second thread are scheduled, both the first thread and the second thread being assigned a first cache unit; the first thread reads data from the first NVM chip according to a micro-instruction sequence for providing a read command to the NVM chip and records the data in a first cache unit; the second thread writes the data of the first cache unit to the second NVM chip according to a micro instruction sequence for providing a program command to the NVM chips.

According to one of the nineteenth media interface command processing methods of the third aspect of the present application, there is provided the twentieth media interface command processing method of the third aspect of the present application, wherein the second thread yields in response to data to be written to the second NVM chip not having been recorded in the first cache unit; and/or scheduling the second thread in response to data to be written to the second NVM chip being recorded in the first cache location.

According to a fourth aspect of the present application, there is provided an information processing apparatus according to the fourth aspect of the present application, comprising a processor and a memory, wherein the processor stores a program that realizes one of the first to twentieth media interface command processing methods according to the third aspect of the present application when executed by the processor.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 illustrates a block diagram of a prior art storage device;

FIG. 2 illustrates a detailed block diagram of a control component of the storage device;

FIG. 3 illustrates a media interface controller;

FIG. 4A illustrates a mixed channel media interface controller according to the present application;

FIG. 4B illustrates yet another hybrid channel media interface controller according to the present application;

FIG. 5 illustrates a schematic diagram of a mixed channel media interface controller implementing a programming operation in accordance with the present application;

FIG. 6A is a diagram illustrating a microinstruction according to yet another embodiment of the present application;

FIG. 6B illustrates a set of NVM configuration registers according to yet another embodiment of the present application;

FIG. 7 shows a block diagram of a microinstruction execution unit according to yet another embodiment of the present application;

FIG. 8 illustrates a block diagram of a media interface controller according to yet another embodiment of the present application;

FIG. 9A illustrates a block diagram of a media interface controller according to yet another embodiment of the present application;

FIG. 9B illustrates a block diagram of a media interface controller according to yet another embodiment of the present application; and

FIG. 10 illustrates a block diagram of a media interface controller according to another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

FIG. 4A illustrates a mixed channel media interface controller according to the present application.

The signal drivers of the media interface controller couple one or more channels (shown in fig. 4A as channel 420 and channel 425). Each channel is coupled to one or more NVM chips. These NVM chips are of the same or different types. By way of example, in FIG. 4A, 2 NVM chips coupled to channel 420 have type 1 and type 2, respectively, and 2 NVM chips coupled to channel 425 have type 3 and type 4, respectively. Still by way of example, type 1 is a low-latency NVM operating, for example, according to the Toggle standard, type 2 is a TLCNVM operating according to the Toggle standard, type 3 is a TLCNVM operating according to the ONFI standard, and type 4 is a TLCNVM operating according to the ONFI standard but operating in SLC mode.

FIG. 4B illustrates yet another hybrid channel media interface controller according to the present application.

In contrast to the hybrid channel media interface controller of FIG. 4A, the micro instruction memory of the hybrid channel media interface controller of FIG. 4B stores a plurality of micro instruction sequences including, for example, a micro instruction sequence for media interface command processing, a micro instruction sequence 410 for issuing a program command to an NVM chip having a type 1, a micro instruction sequence 412 for issuing a program command to an NVM chip having a type 2, a micro instruction sequence 414 for issuing a read command to an NVM chip having a type 3, and a micro instruction sequence 416 for issuing an erase command to an NVM chip having a type 4. The micro instructions of the micro instruction sequence (410, 412, 414, and 416) each indicate the parameters needed to satisfy the type of NVM chip to be operated on. It will be appreciated that the micro instruction memory also stores micro instruction sequences for other operations.

In response to the storage command processing unit (see also fig. 2) providing the media interface command, the microinstruction execution unit executes the microinstruction sequence for media interface command processing to identify the NVM chip type and operation type indicated by the media interface command, and invokes the corresponding microinstruction sequence to drive the signal driver to generate the storage media access command to the Target of the specified NVM chip. By providing corresponding micro instruction sequences for different types of NVM chips, a storage medium access command corresponding to the type of NVM chip is generated on the channel when the micro instruction sequences are executed.

For example, the media interface command indicates to the NVM chip of type 1 of the programming channel 420 that the microinstruction sequence 410 for issuing a program command to the NVM chip having type 1 is invoked by the microinstruction sequence for performing media interface command processing. As another example, the media interface command instructs the type 4 NVM chip of the erase channel 425 to invoke the microinstruction sequence 416 for issuing an erase command to the NVM chip having type 4 through the microinstruction sequence for performing the media interface command processing.

As yet another example, the media interface command indicates a variety of information, including the type of operation (e.g., read, program, erase, etc.), the address accessed (e.g., which NVM chip, which LUN, block number, page number, etc.), and optionally a type flag. The type flag indicates, for example, TLC operation, MLC operation or SLC operation. Alternatively or additionally, the type flag indicates that the ONFI protocol is used or the Toggle protocol is used. By executing the micro instruction sequence for media interface command processing, the micro instruction sequence corresponding to the media interface command is identified. For example, if the type flag of the media interface command indicates SLC operation, then the microinstruction sequence 410 is invoked to generate a storage media access command from the media interface command; if the type flag of the media interface command indicates TLC operation, then the micro instruction sequence 412 is invoked to generate a storage media access command from the media interface command.

FIG. 5 illustrates a schematic diagram of a mixed channel media interface controller implementing programming operations in accordance with the present application.

By way of example, the microinstruction memory stores a microinstruction sequence 510 for media interface command processing, a microinstruction sequence 512 for issuing program commands to NVM chips having SLC type, and a microinstruction sequence 514 for issuing program commands to NVM chips having TLC type.

The micro instruction sequence 510 for media interface command processing is executed in response to the storage command processing unit providing the media interface command to the media interface controller. The micro instruction sequence 510 obtains a media interface command (520), identifies the type and operation type of the NVM chip indicated by the media interface command according to the content of the media interface command, and calls the corresponding micro instruction sequence (512 or 514) to drive the signal driver to generate a storage media access command to the Target of the specified NVM chip.

Optionally, when the microinstruction sequence 510 is executed, the corresponding parameter is generated and the called microinstruction sequence is configured according to the NVM chip type and the operation type indicated by the media interface command. For example, for a program command of an SLC type NVM chip, the amount of data it needs to transfer is 4KB, while for a program operation of a TLC type NVM chip the amount of data it needs to transfer is 16KB, 32KB or 48 KB. The size of the amount of data to be transferred is indicated in the parameters generated when the sequence of micro instructions 510 is executed. Still by way of example, the program commands for an SLC type NVM chip have a different command format and/or command encoding than the program commands for a TLC type NVM chip, and the command format and/or command encoding to be used is indicated in the parameters generated when the microinstruction sequence 510 is executed. As yet another example, the program commands for the SLC type NVM chip and the TLC type NVM chip have different timing or constraints, such as having respective signal setup and/or hold times, which are indicated to be used in parameters generated when the microinstruction sequence 510 is executed.

Still optionally, the microinstruction sequence 510 is executed to check or adjust the physical address indicated by the media interface command to access the NVM chip. For example, the programming order of the physical pages of a block of the NVM chip does not coincide with their physical page numbers (e.g., programming cannot be performed in an increasing or decreasing order of physical page numbers, but rather the physical pages are programmed in a specified order, e.g., in the order of physical page numbers 1-10-11-2-20). Accordingly, the micro instruction sequence 510, when executed, generates a physical page number to be programmed from the physical address indicated by the media interface command. As yet another example, multiple types of NVM chips have different numbers of physical pages within their respective blocks. To manage the convenience of the storage medium, the storage command processing unit manages the storage medium in terms of a virtual NVM, the media interface command indicating the page address of the virtual NVM, the pages of the virtual NVM may be composed of two or more real physical pages, and the translation between the page address of the virtual NVM and the real physical page number is performed by the microinstruction sequence 510.

By way of example, if the micro instruction sequence 510 is executed to recognize that the retrieved media interface command indicates to perform a programming operation on an SLC type NVM chip, the micro instruction sequence 512 is invoked and optionally provided with the required parameters to perform the programming of the SLC type NVM chip. In response, the microinstruction execution unit (see also FIG. 4) executes the microinstruction sequence 512.

By way of example, for a program operation of an SLC type NVM chip, the amount of data written is 4 KB. The micro instruction sequence 512, when executed, retrieves the 4KB of data to be written (the storage location of which is provided by the media interface command) and stores it in the program data cache. Optionally, the micro instruction sequence 512 only confirms that the 4KB of data to be written is available and does not move it to the cache, reducing operations.

The execute microinstruction sequence 512 also generates signals indicative of the SLC NVM chip program command to provide the program command to the SLC NVM chip along with the 4KB of data.

And executing the signal which is generated by the micro-instruction sequence 512 and indicates the programming command of the SLC NVM chip, and storing the timing sequence and the constraint condition of the protocol by being compatible with the storage protocol supported by the SLCNVM chip.

By way of further example, if the micro instruction sequence 510 recognizes that the acquired media interface command indicates to perform a programming operation on a TLC-type NVM chip, the micro instruction sequence 512 is invoked and optionally provided with the required parameters for performing the programming of the TLC-type NVM chip. In response, the microinstruction execution unit (see also FIG. 4) executes the microinstruction sequence 514.

By way of example, for a programming operation of a TLC type NVM chip, the amount of data written is 48 KB. The micro instruction sequence 514, when executed, retrieves the 48KB of data to be written (the storage location of which is provided by the media interface command) and stores it in the program data cache. Optionally, the unit of each shift of data of the micro instruction sequence 514 (also including the micro instruction sequence 512) is 4KB, and accordingly, the micro instruction sequence completes the acquisition of data to be written into the TLCNVM chip by 16 data shifts. Optionally, the number of data moves (16) is indicated by a parameter of the microinstruction sequence 510, or the microinstruction sequence 514 itself records the number.

Optionally, the micro instruction sequence 514 only confirms that 48KB of data to be written is available without moving it to the cache, reducing operations.

The execute micro instruction sequence 514 also generates a signal indicating a TLC NVM chip program command to provide the program command to the TLC NVM chip along with 48KB of data.

FIG. 6A is a diagram illustrating a microinstruction according to yet another embodiment of the present application.

Referring also to fig. 3 and 4, the micro instruction sequence includes a plurality of micro instructions, and the media interface controller executes the micro instructions in the micro instruction sequence.

To support multiple types of NVM chips in a single channel mixed setup, "type flag" is set in one, multiple, or all microinstructions (601). The type tag indicates the type of NVM chip on which the microinstruction operates.

Fig. 6A also provides a table showing the meaning of the type flag. For example, a type flag with a value of "0 x 01" indicates that the NVM chip type is a low latency flash memory conforming to the Toggle protocol. The low-latency flash memory conforming to the Toggle protocol includes various features, such as that its memory cell is of SLC type, the data size required for the programming operation is 4KB, the time (unit of microseconds) for the programming completion is typically queried after the program command is issued, and its signal conforms to the timing sequence required by the Toggle protocol. For another example, a type flag with a value of "0 x 02" indicates that the NVM chip type is TLC flash memory conforming to Toggle protocol. The TLC flash memory conforming to the Toggle protocol has various characteristics including, for example, that its memory cell is of the TLC type, the data amount required for the programming operation is 48KB, the time (tens of microseconds) until the programming is completed is typically queried after the program command is issued, and its signal conforms to the timing sequence required by the Toggle protocol. As another example, a type flag with a value of "0 x 03" indicates that the NVM chip type is TLC flash that complies with the ONFI protocol. Various features of TLC flash memory that conforms to the ONFI protocol include, for example, that its memory cells are of the TLC type, the amount of data required to perform the programming operation on it is 16KB or 32KB, the time to program completion (tens of microseconds) typically queried after issuing the program command, the signals of which conform to the timing required by the ONFI protocol. As another example, a type flag with a value of "0 x 04" indicates that the NVM chip type is TLC flash that complies with the ONFI protocol, but operates in SLC mode. Various features of TLC flash memory that conforms to the ONFI protocol when operating in SLC mode include, for example, its memory cells are of SLC type, the amount of data required to perform a programming operation on it is 16KB, the time to program completion (a few microseconds) typically queried after issuing a program command, the signals of which conform to the timing required by the ONFI protocol.

Various microinstructions are provided in chinese patent application No. 201510253428.1 entitled "method and apparatus for executing a microinstruction sequence," chinese patent application No. 201610009789.6 entitled "method and apparatus for checking block page addresses," and chinese patent application No. 201610836531.3 entitled "method and apparatus for generating NVM chip interface commands," which are incorporated herein by reference in their entirety. One or more existing micro instructions, as well as one or more micro instructions that are proposed in the future, may additionally be provided with a "type flag" according to embodiments of the present application to indicate the type of NVM chip to be operated upon.

The "type tag" of the microinstruction indicates the type of NVM chip and also requires one or more features required to describe one or more "type tags" for the media interface controller. According to an embodiment of the present application, the media interface controller further includes one or more NVM configuration register sets, each NVM configuration register set including a plurality of registers for describing features of a corresponding NVM chip.

FIG. 6B illustrates a set of NVM configuration registers according to yet another embodiment of the present application.

In fig. 6B, as an example, there are 4 values of "type flag", which are "0 x 00", "0 x 01", "0 x 02", and "0 x 03", respectively (see also fig. 6A). Each value of the "type flag" corresponds to one of 1 set of NVM configuration registers (610, 620, 630, and 640). The registers of the NVM configuration register set are used for describing the characteristics of the NVM chip respectively.

By way of example, each set of NVM configuration registers includes 4 registers (including a time constraint configuration register, an address format configuration register, a data length configuration register, and a command format configuration register).

The time constraint configuration register records, for example, setup time, hold time, etc. of one or more signals required by the Toggle or ONFI protocols. The address format configuration register records the format of addresses in a storage medium access command, such as the number of bus cycles occupied by address transmission on the DQ signal, the meaning of the address transmitted in each cycle, and the like. The data length configuration register records the data length required to be transmitted by recording the read command/program command. The command format configuration register records, for example, a command encoding indicating a storage medium access command (e.g., "0 x 80" represents the start of a program command for a particular NVM chip type, while "0 x 10" represents the completion of a data transfer of the program command).

Therefore, a group of NVM configuration registers can be obtained according to the type mark field of the microinstruction, so as to obtain various configurable parameters to be used when the storage medium access command is generated, and the storage medium access command is generated on the channel according to the indication of the parameters.

Still alternatively, the microinstruction indicates a "type tag" field. For a particular microinstruction, it uses one or more configuration registers of the set of NVM configuration registers to which the "type tag" field corresponds (without using all configuration registers). For example, for a micro instruction sequence (including one or more micro instructions) used to generate an erase command, it is not necessary to use the data length configuration registers in the set of NVM configuration registers (the erase command does not need to transfer data).

FIG. 7 shows a block diagram of a microinstruction execution unit according to yet another embodiment of the present application.

Microinstructions to be executed are provided to the microinstruction execution unit. The microinstruction execution unit includes a microinstruction decoding unit, a multiplexer, a selector, a plurality of NVM configuration register sets, and a plurality of signal generation units (e.g., a command signal generation unit, an address signal generation unit, a data transmission signal generation unit).

The microinstruction decode unit provides the type tag field of the microinstruction to the selector. The selector is coupled to the plurality of NVM configuration register sets, and selects and outputs one of the NVM configuration register sets according to the value of the type tag field. For a selected set of NVM configuration registers, one or more of the signal generating units are coupled according to the characteristics described by their respective registers. For example, the time constraint information is used in generating the command encoding, address and data of the storage medium access command, and thus the time constraint configuration register is coupled to the command signal generating unit, the address signal generating unit and the data transmission signal generating unit; the address format information is only used when generating the address of the storage medium access command, and thus the address format configuration register is only coupled to the address signal generation unit, and similarly the data length register is only coupled to the data transfer signal generation unit.

The microinstruction decoding unit is also coupled with the command signal generating unit, the address signal generating unit and the data transmission signal generating unit through a multiplexer. The microinstructions of different meanings operate the corresponding signal generating units to operate the signal drivers to generate signals of the storage medium access commands provided to the NVM chips on the channels.

For example, a micro instruction is used to generate a command header (for example, representing a portion of "0 x80 h") of a storage medium access command, and such micro instruction describes values of signals such as ALE, CLE, DQ (for example, ALE is 0, CLE is 1, and DQ is "0 x80 h"). The microinstruction decoding unit supplies such microinstructions to the command signal generating unit through the multiplexer. The command signal generating unit also receives time constraint information supplied from the time constraint configuration register from the selector, and operates the signal driver to set the ALE, CLE, DQ, etc. signals to a specified level state on the channel at a timing satisfying the time constraint, according to the time constraint information.

As another example, a micro instruction that generates the address portion of a storage medium access command (representing a physical address to be accessed, for example, in the case of a program command) describes, for example, a number of cycles of values transmitted on a DQ signal, or a reference that indicates a memory location where the number of cycles of values transmitted on the DQ signal are stored. The address also requires a format, such as the number of cycles that the DQ signal is transmitted, which portion of the address the value to be transmitted corresponds to, etc. The microinstruction decoding unit provides such microinstructions to the address signal generating unit through the multiplexer. The address signal generating unit also receives the address format supplied from the address format configuration register from the selector. The address signal generating unit operates the signal driver to set the signals DQ etc. to specified values on the channels according to the address format. The address signal generating unit also receives time constraint information provided by the time constraint configuration register and sets a signal such as DQ to a specified level state at a timing when the time constraint is satisfied. Optionally, the address indicated by the microinstruction is also transformed according to the address format provided by the address format configuration register. For example, the program sequence number indicated by the media interface command is converted to a physical page number.

As another example, a micro instruction that generates the data portion of a storage medium access command (representing data to be written to an NVM chip, for example, in the case of a program command) describes, for example, a number of cycles of values transmitted on a DQ signal, or a reference that indicates a memory location in a cache where the number of cycles of values transmitted on the DQ signal are stored. Data length is also required for transferring data, e.g., an SLC type NVM chip corresponds to a 4KB program data length, while a TLC type NVM chip corresponds to a 48KB program data length. The microinstruction decoding unit provides such microinstructions to the data signal generating unit through the multiplexer. The data signal generating unit also receives the data length supplied from the data length configuration register from the selector. The data transfer signal generation unit operates the signal driver to set the DQ or the like signals to a specified value on the channel and generate a specified number of DQ signals (for example, 2048 or 4096 DQ signal transfer cycles are required for transferring 4096 bytes of data) according to the data length and the data to be transferred. The address signal generating unit also receives time constraint information provided by the time constraint configuration register and sets a signal such as DQ to a specified level state at a timing when the time constraint is satisfied.

Optionally, the microinstruction execution unit also executes other microinstructions. Some of the micro instructions are used to determine the location of subsequently executed micro instructions (referred to as control micro instructions), and some are used to move data between memory and cache, and these micro instructions do not operate signal drivers. Optionally, the number of DQ signaling cycles required to transfer data to the NVM chip is determined by the control micro instruction, and the required number of DQ signaling cycles is retrieved from the data length configuration register according to a type flag field of the control micro instruction.

In an alternative embodiment, rather than providing a type flag field in each microinstruction, a microinstruction is provided for setting the type flag. Execution of the microinstructions for setting the type flag sets the microinstruction execution unit to use the specified set of NVM configuration registers, and the setting remains valid until the next time it is changed. Thus, storage medium access commands, for example, for different types of NVM chips, are processed through the same micro instruction sequence, thereby reducing the number of micro instruction sequences that need to be stored. For example, a TLC type NVM chip is coupled to an SLC type NVM chip on the same channel. It is necessary to perform the programming operation to the SLC chip first and then to the TLC chip. And the media interface controller has stored therein a sequence of micro instructions for carrying out the programming operation. The method includes the steps of selecting a set of NVM configuration registers corresponding to the SLC type by a micro-instruction for setting a type flag, such that in a subsequent sequence of micro-instructions for performing a program operation, the signal generation unit generates signals on the channel according to the set of NVM configuration registers corresponding to the SLC type. Next, the NVM configuration register set corresponding to the TLC type is selected by the microinstruction for setting the type flag, so that in the next sequence of microinstructions executed to perform the programming operation, the signal generating unit generates a signal on the channel according to the NVM configuration register set corresponding to the TLC type.

FIG. 8 illustrates a block diagram of a media interface controller according to yet another embodiment of the present application.

When different types of NVM chips are mixed on the channel, an application scenario that the high-speed and low-storage-density NVM chips serve as the cache of the high-density NVM chips appears. In such application scenarios, a need arises to copy data from one NVM chip to another NVM chip, or from high speed low density memory cells (e.g., SLC pages) to high density memory cells (e.g., TLC pages) within a channel. In general, the storage command processing unit of the control section issues a media interface command to the media interface controller, reads out data from an SLC page, and temporarily stores in the storage unit of the control section; next, the storage command processing unit issues a media interface command again, and writes the temporarily stored data to a TLC page. However, such an operation requires that copied data be carried out from the media interface controller to the outside of the media interface controller, and a longer data movement distance means higher power consumption and more time consumption.

According to the embodiment shown in FIG. 8, the copying of data between different physical pages within a channel is done internally to the media interface controller.

In contrast to the media interface controller illustrated in fig. 4, the media interface controller in fig. 8 also illustrates a plurality of cache units (810 and 812). Cache units (810 and 812) are architecturally visible operands that the microinstructions of the media interface controller may describe as either a source address or a destination address for data movement. The size of the buffer unit is suitable for accommodating data corresponding to a read command or a program command of the NVM chip.

Channel 820 couples slcvm chip 840 and TLCNVM chip 842, and channel 825 couples slcvm chip 844 and TLCNVM chip 846.

To move the data of the SLCNVM chip 840 to the TLCNVM chip 842, according to the embodiment of fig. 8, the media interface controller issues a read command to the SLCNVM chip 840, and the destination address of the read data is the buffer unit 810. Next, the media interface controller issues a program command to the TLCNVM chip 842, the source address of the data to be written being the cache 810 (the data to be moved that was previously read out from the SLCNVM chip 840). Thus, data that is moved within the channel only moves within the media interface controller and is not transferred outside of the media interface controller. And the shift operation is completed by combining and utilizing the existing micro-command sequence for reading data from the SLCNVM chip and the micro-command sequence for programming data to the TLCNVM chip, and a new micro-command sequence is not required to be provided.

Optionally, the page size of the slcnv m chip (e.g., 4KB) is different from the TLCNVM chip (e.g., 16 KB). To move data, data is read from a plurality of pages (e.g., 4 pages) of the slcnmm chip by a plurality of read commands and recorded in a buffer unit, and then the data is programmed to the slcnmm chip by a single program command.

The buffer cells (810 and 812) are also used to handle the normal operations of programming data to and reading data from the NVM chip. In order to program data, the micro-instruction sequence is executed to move the data to be programmed from the outside of the media interface controller to the cache unit, and then the data in the cache unit is moved to the NVM chip through the operation signal driver. To read data, a micro instruction sequence is executed to move data read from the NVM chip to the cache unit and then to the outside of the media interface controller.

Optionally, the cache unit is associated with a channel. For example, cache unit 810 is dedicated to channel 820, while cache unit 812 is dedicated to channel 825. Thus, in order to copy the data of the slcnv vm chip 844 to the TLCNVM chip 846, the cache unit 812 associated with the channel 825 is used to temporarily store the data to be copied.

Still alternatively, the buffer units are allocated among the channels. Thus, copying data between NVM chips located in different channels is also performed through the cache unit of the media interface controller.

Still optionally, the media interface command provided to the media interface controller indicates a copy operation indicating a physical address of the NVM chip to be read and a physical address of the NVM chip to be programmed. The microinstruction sequence (see also fig. 4) for media interface command processing identifies a media interface command indicating a copy operation, and successively calls the microinstruction sequence for issuing a read command to the NVM chip and the microinstruction sequence for issuing a write command to the NVM chip, and the two microinstruction sequences forward and backward transfer data to be copied using the same cache unit.

Fig. 9A illustrates a block diagram of a media interface controller according to yet another embodiment of the present application.

In the example of fig. 9A, in the same channel, the slcnv vm chip is used as a write cache of the mlc vm chip, and only the slcnv vm chip is used to provide a physical address space of the storage device. For example, the capacities of the

slcnv vm chips

940 and 944 are 16GB, and the capacities of the

mlc vm chips

942 and 946 are 128 GB. Although channel 940 and channel 945 together couple an NVM chip with a capacity of 288GB, the size of the physical address space used by the storage media management unit (see also fig. 2) is 256GB (provided by the MLCNVM chips 942 and 946), so that the storage media management unit need not be concerned with the internal structure of the SLCNVM chip and its allocation of storage resources.

According to the embodiment of fig. 9A, the media interface command provided to the media interface controller by the storage command processing unit indicates the data attribute to be written, and the media interface controller determines whether to write the data indicated by the media interface to the slcnmvm chip or the MLCNVM chip according to the data attribute and the available space of the slcnmvm chip.

By way of example, the media interface command indicates a programming operation and the data to be written is hot data (data to be frequently updated) or data requiring low processing latency, and the media interface command also indicates that the physical address to be written is physical block 2 of the MLCNVM chip 942 (also denoted as M2, where M indicates the MLCNVM chip). The micro-command sequence for media interface command processing (see also fig. 4) allocates an available physical block (e.g., physical block 0, also denoted as S0, where S indicates the slcnmm chip) for the media interface command from the slcnmm chip 940, and calls the micro-command sequence that issues a program command to the slcnmm chip, writing data to the physical block S0. Optionally, the micro instruction sequence also performs changes such as physical page addresses through the corresponding type of NVM configuration register set to issue program commands to the SLCNVM vm chip 940.

In response to allocation of the available physical block S0 from the SLCNVM chip 940 for the physical block M2, the micro command sequence for the media interface command process also records the association of the physical block T2 with the physical block S0 in the block mapping table. According to the embodiment of fig. 9A, the media interface controller provides a block mapping table for each channel, in which entries record physical blocks of the MLCNVM chip in association with physical blocks of the slccnvm chip cached as it. It is understood that the physical blocks of each MLCNVM chip may correspond to the physical blocks of a plurality of slccnvm chips; and the address format configuration register of the NVM configuration register group records the mapping mode from the physical page of the MLCNVM chip to the physical page of the SLCNVM chip.

In the example of FIG. 9A, the entries of the block mapping table provide physical block level mappings. The number of physical blocks in the NVM chip is relatively small (compared to the number of physical pages) and thus the overall size of the block mapping table is not very large and can be accommodated by the media interface controller. While the storage medium management unit (see also fig. 2) maintains a page-level mapping, e.g. recording the corresponding physical address for each 4KB sized segment of the logical address space, for mass storage devices, a page-level mapping requires a large amount of memory space to be occupied.

Referring back to FIG. 9A, in response to receiving the media interface command (denoted as MI-1) again, it instructs to write data to physical block 2(M2) of the MLCNMV chip 942. Regardless of whether the media interface command indicates hot data or data requiring low processing delay, the micro-command sequence for media interface command processing (see also fig. 4) recognizes that physical block M2 is mapped to physical block 0 of SLCNVM vm chip 940 through the block mapping table (S0), which calls a micro-command sequence issuing a program command to the SLCNVM vm chip, writing the data to physical block S0.

Alternatively or additionally, in response to receiving the media interface command (denoted as MI-2) again, it instructs to read data from physical block 2(M2) of the MLCNVM chip 942. The micro-command sequence for media interface command processing (see also fig. 4) recognizes that the physical block M2 is mapped to the physical block 0 of the SLCNVM vm chip 940 through the block mapping table (S0), which calls the micro-command sequence for issuing a read command to the SLCNVM vm chip, and reads out data from the physical block S0 in response to the media interface command (MI-2). It is understood that in executing the micro-instruction sequence for issuing the read command to the SLCNVM vm chip, the physical address indicated by the media interface command (MI-2) is converted into the physical address for the SLCNVM configuration register set.

Further, the storage medium management unit (see also fig. 2) records in the page-level mapping table that the physical address used is still the address of the physical block 2 from the MLCNVM chip 942, instead of the address of the SLCNVM chip 940, in response to the processing of the medium interface command (MI-1). According to the embodiment of fig. 9A, the SLCNVM chips of each channel are used as the cache of the MLCNVM chip of the same channel, and the storage medium management unit only uses the physical address of the MLCNVM chip in the page level mapping table, but does not use the physical address of the slcnmvm chip, i.e. the slcnmvm chip is considered invisible to the storage medium management unit.

Still alternatively, due to the inconsistent block sizes, block 0 and block 1 of the SLCNVM chip 940 (denoted as S0 and S1) are commonly mapped to block 2 of the mlc nvm chip 942 (M2), wherein the total capacity of blocks S0 and S1 is not less than the capacity of block M2. In response to blocks S0 and S1 being full, the media interface controller also copies the data of blocks S0 and S1 to block M2, such as by copying the data as shown in connection with the embodiment of FIG. 8. For example, the microinstruction memory of the media interface controller also stores sequences of microinstructions used to manage the cache. In response to the multiple physical blocks of the slcn vm chip being fully written to which physical blocks of the MLCNVM chip are mapped, in response to the slcn vm chip being fully written (there are no available physical blocks and all used physical blocks are fully written), periodically, or when the channel 940 is idle, a sequence of micro-instructions for managing the cache is executed or a sequence of micro-instructions for a copy operation is invoked to effect the copy from the SLC NVM chip 940 to the MLCNVM chip 942. After the copying is completed, one or more physical blocks of the copied SLCNVM chip are erased, and the block mapping table is also updated, and the physical blocks of the copied SLCNVM chip are deleted from the block mapping table. Since the read command is deleted from the block mapping table, next, if a media interface command indicating a read operation is received, after the micro command sequence for media interface command processing queries the block mapping table, it is recognized that data to be read is recorded in the MLCNVM chip instead of the SLCNVM chip, and thus a micro command sequence for issuing a read command to the MLCNVM chip is called. And optionally, the microinstruction sequence for media interface command processing also sets the type flag field of the invoked microinstruction sequence to indicate the type of NVM chip to be accessed.

Fig. 9B illustrates a block diagram of a media interface controller according to yet another embodiment of the present application.

In the example of fig. 9B, the storage medium management unit knows the internal structure of the SLCNVM chip and the allocation of its storage resources. Thus, the physical address of the slcnvvm chip may exist in a page-level mapping table maintained by the storage medium management unit. Optionally, the page-level mapping table also marks the NVM chip type or characteristics for each physical address (e.g., the physical address is provided by the MLCNVM chip or by the SLCNVM chip). Referring to fig. 9B, the physical address space managed by the storage medium management unit is shown. The physical address space ranges from physical address P0 to physical address Pn. Physical addresses P0-Pm are provided by the SLCNVM chip, and physical addresses Pm +1 through Pn are provided by the MLCNVM chip. In fig. 9B, the second column of the physical address space table indicates by which physical block the physical address of the row is provided.

In turn, the storage command processing unit provides the media interface command to the media interface controller indicating the physical address. The microinstruction sequence (see also fig. 4) for media interface command processing calls the corresponding microinstruction sequence to issue a storage media access command to the NVM chip according to the physical address indicated by the media interface command. Without the need for the media interface controller to maintain a mapping between the physical blocks of the SLCNVM chip and the MLCNVM chip.

The medium interface controller comprises a micro-instruction memory, a micro-instruction execution unit, a signal driver, a scheduler and a status register. The sequence of microinstructions executed by the microinstruction execution unit, along with its state data, is referred to as a thread. The scheduler is coupled to the status register, the micro instruction memory, and the micro instruction execution unit, which is coupled to the signal driver. In this embodiment, the threads correspond to LUNs of the NVM chip one to one, for example. Each thread is used to process storage medium access commands that access a LUN. For a media interface command that indicates a copy operation, it accesses two different LUNs, and the NVM chips to which the two LUNs belong may be of different types. According to an embodiment of the present application, media interface commands that indicate a copy operation are processed by a single thread. The status register stores status data for one or more threads. The thread also owns the cache location.

The running thread has control of the media interface controller. The thread yields itself by executing yield (yield) microinstructions. When a thread yields, its state data is recorded in the state register. And in response, as shown in FIG. 10, the scheduler selects one of the threads from the one or more threads to be executed by the microinstruction execution unit (this process is referred to as scheduling, or scheduling threads). The scheduled thread retrieves its state data from the state register. For example, according to a media interface command to access a certain LUN to be processed, the scheduler schedules a thread corresponding to the LUN so that the thread processes the media interface command during execution. Still by way of example, thread A yields when it is processing media interface command C, but has not yet finished processing. And when the scheduler schedules the thread A again, the thread A can continue to process the media interface command C from the yielding position according to the acquired state information.

Referring to FIG. 10, the media interface controller includes channels (1020 and 1025). Channel 1020 couples slcvm chip 1040 with TLCNVM chip 1042. The slcnv vm chip 1040 includes two LUNs (respectively, LUN (b) and LUN (c)). The slcnv vm chip 1042 includes two LUNs (respectively designated as LUN (a) and LUN (c)). For example, the media interface controller runs 3 threads (respectively denoted as thread a, thread B, and thread C) and uses cache units (respectively denoted as cache unit a, cache unit B, and cache unit C). Thread A is accessing LUN (A), thread B is accessing LUN (B), and thread C is copying data from LUN (C) of SLCNVM chip 1040 to LUN (C) of TLCNVM chip 1042.

The micro instruction sequence of the execution thread C issues a read command to lun (C) of the slcnv vm chip 1040 through the signal driver, moves the read data to the buffer unit C, and issues a program command to lun (C) of the TLCNVM chip 1042 through the signal driver, and writes the data of the buffer unit C to lun (C) of the TLCNVM chip 1042. In this process, thread C may yield. By using a single thread to access both LUNs for processing the copy command, the cache unit C remains owned by thread C and is not used by other threads during the yield of thread C to ensure that the copied data is not corrupted.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A control component comprising a media interface controller for coupling a plurality of NVM chips;

the media interface controller is coupled to the plurality of NVM chips via a plurality of channels;

a first channel of the plurality of channels is coupled to a plurality of NVM chips;

a first NVM chip of the plurality of NVM chips is of a first type and a second NVM chip of the plurality of NVM chips is of a second type; wherein the first type is different from the second type;

the medium interface controller comprises a micro-instruction storage unit, a micro-instruction execution unit and a signal driver;

the microinstruction execution unit executes a sequence of microinstructions to operate the signal driver to provide signals to the plurality of channels.

2. The control component of claim 1,

the micro instruction memory stores a plurality of micro instruction sequences;

the plurality of micro instruction sequences comprise a micro instruction sequence used for processing a medium interface command and a plurality of micro instruction sequences used for providing a storage medium access command for the NVM chip;

and executing the micro instruction sequence for processing the medium interface command, and calling the micro instruction sequence corresponding to the medium interface command and used for providing a storage medium access command for the NVM chip.

3. The control component of claim 1 or 2,

the microinstruction execution unit further includes a plurality of NVM configuration register sets, each NVM configuration register set including a plurality of registers storing characteristics of the NVM chip;

executing the micro instruction sequence for processing the media interface command also sets a type flag;

the microinstruction execution unit accesses one of the plurality of NVM configuration register sets according to the type tag and operates the signal driver to provide signals to the plurality of channels using the characteristic of the NVM chip obtained by accessing the one of the plurality of NVM configuration register sets.

4. The control component of claim 3,

the microinstruction execution unit also comprises a microinstruction decoder and a plurality of signal generation units;

the micro-instruction decoder provides the micro-instruction to one of the plurality of signal generating units according to the meaning of the micro-instruction;

the microinstruction decoder further selects a plurality of registers of one of the plurality of NVM configuration register sets to provide to one or more of the plurality of signal generation units based on the type tag;

the signal generating unit operates the signal driver to provide a signal to one of the plurality of channels according to the microinstructions provided by the microinstruction decoder and the characteristics retrieved from the one of the plurality of NVM configuration register sets.

5. The control component of claim 4,

the plurality of signal generating units comprise a command signal generating unit, an address signal generating unit and/or a data transmission signal generating unit;

the command signal generating unit generates a command header of a storage medium access command according to the microinstruction, and also acquires time constraint information from a time constraint configuration register of the NVM configuration register set to generate an ALE signal and/or a CLE signal on the channel.

6. Control unit according to one of claims 1 to 5,

the media interface controller comprises one or more cache units for caching data read from or to be written to one of the plurality of NVM chips;

the microinstruction execution unit executes a microinstruction sequence used for copying operation to provide a read command to the first NVM chip, record the read data in a first cache unit, and provide a programming command to the second NVM chip to write the data of the first cache unit into the second NVM chip.

7. The control component of claim 6,

the first NVM chip serves as a cache for the second NVM chip;

the media interface controller further includes a block mapping table, entries of which record blocks of the second NVM chip in association with one or more blocks of the first NVM chip;

in response to receiving a first media interface command indicating to write data to a first block of the second NVM chip, accessing the block mapping table for a second block of the first NVM chip associated with the first block; writing write data indicated by the first media interface command to the second block by a sequence of microinstructions for providing a program command to the first type of NVM chip.

8. The control component of claim 7,

the write data size indicated by the first media interface command is the physical page size of the first block;

and when a micro instruction sequence used for providing a programming command for the NVM chip of the first type is executed, acquiring a conversion mode of a physical page address of the second NVM chip and a physical page address of the first NVM chip through an address format configuration register of an NVM configuration register group corresponding to the same type mark, and generating the physical page address of the second block.

9. The control unit according to one of claims 1 to 8,

the media interface controller includes a scheduler for scheduling a plurality of threads to be executed by the microinstruction execution unit, wherein the sequence of microinstructions that are executed, along with their state, are referred to as threads;

a first plurality of threads in the plurality of threads correspond to the LUNs of the plurality of NVM chips one-to-one, each of the first plurality of threads corresponding to a microinstruction sequence for providing a storage medium access command to the NVM chip;

and a second thread of the multiple threads corresponds to the LUN of the first NVM chip to be copied, and the second thread is used for a micro instruction sequence applied to copying operation.

10. A memory device includes a control unit and a plurality of NVM chips; characterized in that the control means are control means according to one of claims 1-9.