CN106569964A - Power-off protection method, power-off protection device, power-off protection system and memory - Google Patents
Power-off protection method, power-off protection device, power-off protection system and memory Download PDFInfo
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- CN106569964A CN106569964A CN201510970145.9A CN201510970145A CN106569964A CN 106569964 A CN106569964 A CN 106569964A CN 201510970145 A CN201510970145 A CN 201510970145A CN 106569964 A CN106569964 A CN 106569964A
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- business datum
- power
- memory
- processor
- bar system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
Abstract
The invention provides a power-off protection method, a power-off protection device, a power-off protection system and a memory. The power-off protection method comprises the steps of acquiring service data which are stored in a memory chip on the condition that power-off occurs in the memory system; and writing the service data into a nonvolatile memory device, wherein the nonvolatile memory device returns the service data to the memory chip on the condition that power supply of the memory system is recovered. The power-off protection method, the power-off protection device, the power-off protection system and the memory provided by the invention settle a problem of service data loss in the memory on the condition of abnormal power-off of the memory system and furthermore protects the service data from loss.
Description
Technical field
The present invention relates to storage server system in server field, protects in particular to a kind of power down
Maintaining method, apparatus and system.
Background technology
With communication and the rapid popularization of electronic technology, associated storage service is also fast development,
Higher and higher requirement it is also proposed to the unfailing performance of storage system, the storage system under various emergency cases
System can be effectively protected system data becomes one of requisite factor of measurement reliability.Cloud is deposited at this stage
Scheme more than storage system using storage server is realized.Traditional memory bar system is by golden finger socket, interior
Memory controller and memory chip are constituted, and memory bar is inserted by finger plug in the internal memory socket of server,
For systems with data store function.But the memory bar system of this server configures is without power down protection
Function, memory chip are volatile storage module again, data in EMS memory meeting when system exception power down
Lose, cause metadata to fail, it is serious in the case of business datum can be caused to destroy.
In for correlation technique, in memory bar system power failure, it is impossible to protect the problem of internal storage data, still
Effective solution is not proposed.
The content of the invention
The invention provides a kind of power-off protection method, apparatus and system, at least to solve in correlation technique
When system exception power down, data in EMS memory can be lost, and cause metadata to fail, it is serious in the case of meeting
The problem for causing business datum to be destroyed.
According to an aspect of the invention, there is provided a kind of power-off protection method, including：
In memory bar system power failure, the business datum preserved in obtaining memory chip；
The business datum is write into Nonvolatile memory devices, wherein, the non-volatile memories are filled
Put in the memory bar system resumes power, the business datum is back to into the memory chip.
Further, the business datum is write into Nonvolatile memory devices, including：
By in business datum write caching；
The business datum is write in the Nonvolatile memory devices by the caching.
According to another aspect of the present invention, there is provided a kind of power-off protection method, including；
The business datum of receiving processor write, the wherein business datum are fallen in memory bar system for processor
When electric, the business datum obtained from memory chip；
In the memory bar system resumes power, the business datum is back to into the memory chip.
Further, the business datum of receiving processor write, including：
The business datum is written in caching by processor；
Receive the business datum of the Buffer forwarding.
Further, in the memory bar system resumes power, the business datum is back to described
Memory chip, including：
The business datum is sent to processor；
The business datum is back to by the memory chip by the processor.
Further, the processor includes：FPGA processor or dsp processor.
According to a further aspect in the invention, there is provided a kind of power-down protection apparatus, including：Acquisition module, uses
When in memory bar system power failure, the business datum preserved in obtaining memory chip；Writing module, is used for
The business datum is write into Nonvolatile memory devices, wherein, the Nonvolatile memory devices exist
During the memory bar system resumes power, the business datum is back to into the memory chip.
According to a further aspect in the invention, there is provided another kind of power-down protection apparatus, including：Receiver module,
For the business datum of receiving processor write, the wherein business datum is fallen in memory bar system for processor
When electric, the business datum obtained from memory chip；Module is returned, for extensive in the memory bar system
When powering again, the business datum is back to into the memory chip.
According to a further aspect in the invention, there is provided a kind of power down protection system, including：Processor, it is non-easy
The property lost storage device, wherein, the processor is connected with Memory Controller Hub and Nonvolatile memory devices,
For in memory bar system power failure, the business datum preserved in obtaining memory chip；By the business number
According to write into Nonvolatile memory devices；The Nonvolatile memory devices, in the memory bar
During system resumes power, the business datum is back to into the memory chip.
Further, the system also includes：Caching, the caching are non-volatile with described with the processor
Storage device connects, in the memory bar system power failure, receiving the business of the processor write
Data, and the business datum is forwarded to into the Nonvolatile memory devices, or, for described interior
When depositing bar system resumes power, the business datum that the Nonvolatile memory devices are sended over is forwarded to
The processor.
Further, the system also includes：Electric supply installation, wherein, electric supply installation for it is following at least
One of be powered：The processor, the Nonvolatile memory devices, caching.
Further, the electric supply installation includes：Electric capacity.
Further, the processor includes：FPGA field programmable gate arrays processor or DSP numbers
Word signal processor.
According to a further aspect in the invention, there is provided a kind of memory bar, including any of the above-described kind of power down protection system
System.
By the present invention, employ in memory bar system power failure, the business preserved in obtaining memory chip
Data simultaneously write the business datum into Nonvolatile memory devices, wherein, the non-volatile memories are filled
Put in the memory bar system resumes power, the business datum is back to into the memory chip.Solution
Memory bar system power failure of having determined causes the problem of service data loss, and then has reached to fall in memory bar system
When electric, business datum is protected not to be lost.
Description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes of the application
Point, the schematic description and description of the present invention is used to explain the present invention, does not constitute to the present invention's
Improper restriction.In the accompanying drawings：
Fig. 1 is the flow chart of power-off protection method according to embodiments of the present invention；
Fig. 2 is another flow chart of power-off protection method according to embodiments of the present invention；
Fig. 3 is the structured flowchart of power-down protection apparatus according to embodiments of the present invention；
Fig. 4 is another structured flowchart of power-down protection apparatus according to embodiments of the present invention；
Fig. 5 is the structured flowchart of power down protection system according to embodiments of the present invention；
Fig. 6 is another structured flowchart of power down protection system according to embodiments of the present invention.
Specific embodiment
Below with reference to accompanying drawing and in conjunction with the embodiments describing the present invention in detail.It should be noted that
In the case of not conflicting, the feature in embodiment and embodiment in the application can be mutually combined.
It should be noted that description and claims of this specification and the term in above-mentioned accompanying drawing "
One ", " second " etc. is for distinguishing similar object, without specific sequentially or first for describing
Order afterwards.
Power-off protection method is provided in the present embodiment, and Fig. 1 is that power down according to embodiments of the present invention is protected
The flow chart of maintaining method, as shown in figure 1, the flow process comprises the steps：
Step S101, in memory bar system power failure, the business datum preserved in obtaining memory chip；
Step S102, the business datum is write into Nonvolatile memory devices, wherein, this is non-easily
The property lost storage device is back to above-mentioned business datum in above-mentioned in the memory bar system resumes power
Deposit chip.
Preferably, step S102 can also be realized by below scheme, and the write of above-mentioned business datum is cached
In：Above-mentioned business datum is write in above-mentioned Nonvolatile memory devices by above-mentioned caching, that is to say, that
Business datum can directly write to Nonvolatile memory devices, it is also possible to be first written to business datum slow
In depositing, business datum is written to by Nonvolatile memory devices by caching then.
The technical scheme of above-described embodiment is illustrated below in conjunction with an example：During memory bar system power failure
Quickly can will be currently running in memory chip and need the business datum size for preserving, draw in the buffer
Corresponding memory space is separated, and data to be protected is needed for depositing.Caching and memory chip are all volatile
Property memorizer, it can read and write at any time, but storage process data that can only be of short duration, so
Typically as operating system or other be currently running the temporary storage medium of program.For this reason,
In memory bar system, processor can control to cache the data write non-volatile memories dress by memory space
Put, Nonvolatile memory devices generally can be FLASH chip herein, so that data are preserved for a long time.When being
System is powered when recovering normal, and memory bar system causes shutdown transient to store because of last time abnormal power-off
Business datum in memory chip is saved in Nonvolatile memory devices, lacks this in memory chip
A little business datums and successional cannot continue normal operation.At this moment being accomplished by Nonvolatile memory devices will
Data are read back in memory chip, it is ensured that the seriality of memory bar system business.Why in processor and non-
It is transitional between volatile storage to add a caching, it is because that processor control memory chip will wherein
Business datum when writing direct in Nonvolatile memory devices speed it is very slow, and pass through first to write data into
When caching writes data into Nonvolatile memory devices by caching again, writing speed is fast, greatly improves
The efficiency of memory bar system operation.
Power-off protection method is additionally provided in the present embodiment, and Fig. 2 is power down according to embodiments of the present invention
Another flow chart of guard method, as shown in Fig. 2 the flow process comprises the steps：
Step S201, the wherein business datum of receiving processor write, the business datum are including processor
When depositing bar system power failure, the business datum obtained from memory chip；
In an optional example, by below scheme, step S201 can also realize that receiving processor is write
The business datum for entering：Above-mentioned business datum is written in caching by processor；Receive above-mentioned caching to turn
The above-mentioned business datum sent out.
Step S202, in above-mentioned memory bar system resumes power, above-mentioned business datum is back to above-mentioned
Memory chip.
The implementation of step S202 has various, in one example, can be realized by below scheme,
Business datum is back to into above-mentioned memory chip：Above-mentioned business datum is sent to processor；By above-mentioned
Above-mentioned business datum is back to above-mentioned memory chip by processor.
When system energization recovers normal, memory bar system causes power-off because of last time abnormal power-off
The business datum that moment is stored in memory chip is saved in Nonvolatile memory devices, memory chip
In lack these director datas and successional cannot continue normal operation.At this moment it is accomplished by non-volatile depositing
Data are read back memory storage module by storage device, it is ensured that the seriality of memory bar system business.Why exist
It is transitional between Nonvolatile memory devices and processor to add a caching, it is because that processor control is non-easily
When the property lost storage device directly reads back the business datum for wherein preserving in memory chip, speed is very slow, and leads to
After first by data read back caching again by caching by data read back memory chip when read back speed soon, greatly
Improve the efficiency of memory bar system operation.
By above-mentioned each step, in memory bar system power failure, the business preserved in obtaining memory chip
Data；Above-mentioned business datum is write into Nonvolatile memory devices, wherein, the non-volatile memories
Above-mentioned business datum is back to above-mentioned memory chip in above-mentioned memory bar system resumes power by device.
Do not have in solving existing memory bar system the measure of power down protection lead to system abnormity power down when business number
According to the problem lost, and then reach in memory bar system power failure, protected business datum not to be lost,
The integrity of memory bar system data under various storage situations is improve, the peace of whole server is increased
Full performance.
Through the above description of the embodiments, those skilled in the art can be understood that basis
The method of above-described embodiment can add the mode of required general hardware platform to realize by software, certainly
Can be by hardware, but the former is more preferably embodiment in many cases.Based on such understanding, this
The part that the technical scheme of invention is substantially contributed to prior art in other words can be with software product
Form is embodied, the computer software product be stored in a storage medium (as ROM/RAM, magnetic disc,
CD) in, use so that a station terminal equipment including some instructions (can be mobile phone, computer, clothes
Business device, or the network equipment etc.) perform the above-mentioned method of each embodiment of the invention.
A kind of power-down protection apparatus are additionally provided in the present embodiment, and the device is used to realize above-described embodiment
And preferred implementation, carried out repeating no more for explanation.As used below, term " mould
Block " can realize the combination of the software and/or hardware of predetermined function.Although the dress described by following examples
Put preferably with software realizing, but hardware, or the realization of the combination of software and hardware is also possible
And be contemplated.
Fig. 3 is the structured flowchart of power-down protection apparatus according to embodiments of the present invention, as shown in figure 3, should
Device is included such as lower module：
Acquisition module 32, in memory bar system power failure, the business number preserved in obtaining memory chip
According to；Writing module 34, for above-mentioned business datum is write into Nonvolatile memory devices, wherein,
Above-mentioned business datum is back to by the Nonvolatile memory devices in above-mentioned memory bar system resumes power
Above-mentioned memory chip.
Power-down protection apparatus are additionally provided in the present embodiment, and Fig. 4 is power down according to embodiments of the present invention
Another structured flowchart of protection device, as shown in figure 4, the device is included such as lower module：
Receiver module 42, for the business datum of receiving processor write, the wherein business datum is process
Device in memory bar system power failure, the business datum obtained from memory chip；Module 44 is returned, is used for
In above-mentioned memory bar system resumes power, above-mentioned business datum is back to into above-mentioned memory chip.
It should be noted that above-mentioned modules can be by software or hardware to realize, for rear
Person, can be accomplished by, but not limited to this：Above-mentioned module is respectively positioned in same processor；
Or, above-mentioned module is located in multiple processors respectively.
Power down protection system is additionally provided in the present embodiment, and the system is used to realize above-described embodiment and excellent
Embodiment is selected, repeating no more for explanation had been carried out.As used below, term " module "
The combination of the software and/or hardware of predetermined function can be realized.Although the system described by following examples compared with
Goodly with software realizing, but hardware, or the realization of the combination of software and hardware be also may and quilt
Conception.
Fig. 5 is a kind of structured flowchart of power down protection system according to embodiments of the present invention, as shown in figure 5,
The system includes：
Processor 52, Nonvolatile memory devices 54, wherein, above-mentioned processor 52, with Memory Controller Hub
56 and Nonvolatile memory devices 54 connect, in memory bar system power failure, obtain memory chip
The business datum preserved in 58；Above-mentioned business datum is write into Nonvolatile memory devices 54；It is above-mentioned
Nonvolatile memory devices 54, in above-mentioned memory bar system resumes power, by above-mentioned business datum
It is back in above-mentioned memory chip 58.
Fig. 6 is a kind of another structured flowchart of power down protection system according to embodiments of the present invention, such as Fig. 6
It is shown, the system in addition to including all modules shown in Fig. 5, also including caching 62 and electric supply installation 64,
The caching 62 is connected with above-mentioned processor 52 with above-mentioned Nonvolatile memory devices 54, for above-mentioned interior
The business datum of the above-mentioned write of processor 52 when depositing bar system power failure, is received, and above-mentioned business datum is turned
Above-mentioned Nonvolatile memory devices 54 are sent to, or, in above-mentioned memory bar system resumes power, inciting somebody to action
The business datum that above-mentioned Nonvolatile memory devices 54 are sended over is forwarded to above-mentioned processor 52.For Denso
64 are put for being powered at least one of：Above-mentioned processor 52, above-mentioned Nonvolatile memory devices
54th, 62 are cached.Preferably, electric supply installation can be electric capacity, when the normal work of memory bar system energization state
When making, electric capacity is charged effect by processor to which.When memory bar system cut-off, electric capacity is carried out
Discharge process is powered to processor, Nonvolatile memory devices or caching.
A kind of memory bar is additionally provided in the present embodiment, and the memory bar includes that any of the above-described is above-mentioned and falls
Electric protection system.The power down protection system is all described in detail above, and here is omitted.
Obviously, those skilled in the art should be understood that each module or each step of the above-mentioned present invention can
Realize with general computing device, they can be concentrated on single computing device, or distribution
On the network constituted by multiple computing devices, alternatively, they can use the executable journey of computing device
Sequence code realizing, it is thus possible to by computing device performing in being stored in storage device, and
And in some cases, shown or described step can be performed with the order being different from herein, or
They are fabricated to each integrated circuit modules respectively, or the multiple modules in them or step are made
Realize into single integrated circuit module.So, the present invention is not restricted to any specific hardware and software
With reference to.
The preferred embodiments of the present invention are the foregoing is only, the present invention is not limited to, for this area
Technical staff for, the present invention can have various modifications and variations.It is all in the spirit and principles in the present invention
Within, any modification, equivalent substitution and improvements made etc. should be included in protection scope of the present invention
Within.
Claims (13)
1. a kind of power-off protection method, it is characterised in that：Including：
In memory bar system power failure, the business datum preserved in obtaining memory chip；
The business datum is write into Nonvolatile memory devices, wherein, the non-volatile memories are filled
Put in the memory bar system resumes power, the business datum is back to into the memory chip.
2. power-off protection method as claimed in claim 1, it is characterised in that：The business datum is write
Enter into Nonvolatile memory devices, including：
By in business datum write caching；
The business datum is write in the Nonvolatile memory devices by the caching.
3. a kind of power-off protection method, it is characterised in that：Including：
The business datum of receiving processor write, wherein, the business datum is processor in memory bar system
During power down, the business datum obtained from memory chip；
In the memory bar system resumes power, the business datum is back to into the memory chip.
4. power-off protection method as claimed in claim 3, it is characterised in that：Receiving processor write
Business datum, including：
The business datum is written in caching by processor；
Receive the business datum of the Buffer forwarding.
5. power-off protection method as claimed in claim 3, it is characterised in that：In the memory bar system
When restoring electricity, the business datum is back to into the memory chip, including：
The business datum is sent to processor；
The business datum is back to by the memory chip by the processor.
6. a kind of power-down protection apparatus, it is characterised in that：Including：
Acquisition module, in memory bar system power failure, the business datum preserved in obtaining memory chip；
Writing module, for the business datum is write into Nonvolatile memory devices, wherein, should
The business datum is back to institute in the memory bar system resumes power by Nonvolatile memory devices
State memory chip.
7. a kind of power-down protection apparatus, it is characterised in that：Including：
Receiver module, for the business datum of receiving processor write, the wherein business datum is processor
In memory bar system power failure, the business datum obtained from memory chip；
Module is returned, in the memory bar system resumes power, the business datum being back to
The memory chip.
8. a kind of power down protection system, it is characterised in that：Including：Processor, Nonvolatile memory devices,
Wherein,
The processor, is connected with Memory Controller Hub and Nonvolatile memory devices, in memory bar system
During system power down, obtain the business datum that preserves in memory chip, and by the business datum write to it is non-easily
In the property lost storage device；
The Nonvolatile memory devices, in the memory bar system resumes power, by the industry
Business data are back to the memory chip.
9. power down protection system as claimed in claim 8, it is characterised in that：The system also includes：
Caching, the caching is connected with the processor with the Nonvolatile memory devices, in the internal memory
The business datum of the processor write during bar system power failure, is received, and the business datum is forwarded to
The Nonvolatile memory devices, or, in the memory bar system resumes power, will be described non-
The business datum that volatile storage is sended over is forwarded to the processor.
10. power down protection system as claimed in claim 8 or 9, it is characterised in that：The system
Also include：Electric supply installation, wherein, electric supply installation is for being powered at least one of：The place
Reason device, the Nonvolatile memory devices, caching.
11. power down protection systems as claimed in claim 10, it is characterised in that：The electric supply installation
Including：Electric capacity.
12. power down protection systems as described in claim 8 or 9 or 11, it is characterised in that：It is described
Processor includes：FPGA field programmable gate arrays processor or DSP.
13. a kind of memory bars, it is characterised in that include：As described in any one of claim 8-12
Power down protection system.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2015106572865 | 2015-10-13 | ||
| CN201510657286 | 2015-10-13 |
Publications (1)
| Publication Number | Publication Date |
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| CN106569964A true CN106569964A (en) | 2017-04-19 |
Family
ID=58508741
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510970145.9A Withdrawn CN106569964A (en) | 2015-10-13 | 2015-12-21 | Power-off protection method, power-off protection device, power-off protection system and memory |
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| CN107193694A (en) * | 2017-05-27 | 2017-09-22 | 郑州云海信息技术有限公司 | A kind of Novel storage system, storage method and device |
| CN108132857A (en) * | 2017-12-15 | 2018-06-08 | 天津津航计算技术研究所 | A kind of FPGA off-positions Exact recovery method |
| CN110096460A (en) * | 2018-01-30 | 2019-08-06 | 北京京东尚科信息技术有限公司 | The method, apparatus and circuit of internal storage data protection |
| CN111192607A (en) * | 2019-12-29 | 2020-05-22 | 浪潮(北京)电子信息产业有限公司 | Power-down protection method and device for storage system and related components |
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| CN113608930A (en) * | 2021-08-24 | 2021-11-05 | 厦门紫光展锐科技有限公司 | System chip and electronic device |
| CN113722158A (en) * | 2021-10-08 | 2021-11-30 | 亿次网联(杭州)科技有限公司 | Electronic equipment, power failure protection method and device thereof, and storage medium |
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Application publication date: 20170419 |