CN103064800A - Power failure protection system and implementation method thereof - Google Patents
Power failure protection system and implementation method thereof Download PDFInfo
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- CN103064800A CN103064800A CN 201310001287 CN201310001287A CN103064800A CN 103064800 A CN103064800 A CN 103064800A CN 201310001287 CN201310001287 CN 201310001287 CN 201310001287 A CN201310001287 A CN 201310001287A CN 103064800 A CN103064800 A CN 103064800A
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Abstract
The invention discloses a power failure protection system and an implementation method thereof. In case of system power failure, a CPU (central processing unit), a memory, a south bridge chip, an interface conversion circuit for a south bridge and a nonvolatile storage medium, and the nonvolatile storage medium are powered by a battery; and a south bridge chip bus interface is used to transfer data that is not stored by the memory to the corresponding nonvolatile storage medium. Therefore, system power failure is protected without increased cost and increased total battery capacity.
Description
Technical field
The invention belongs to technical field of memory, relate to a kind of power down protection system and its implementation.
Background technology
Special-purpose memory device is very high to the security requirement of data, and when writing data to hard disk, data are to write first internal memory, and then write hard disk from internal memory.Because internal memory belongs to volatile storage medium, data are being write in the process of hard disk by internal memory, suddenly power down is is also interviewed and write in the internal memory into all data of hard disk and will be lost.Therefore, when suddenly power down, memory device must be preserved all data that also do not have enough time to write hard disk in the internal memory, avoids loss of data, i.e. the power down protection of memory device.
Mainly containing at present dual mode comes memory device is carried out power down protection:
One, adopts the battery protection internal memory; As shown in Figure 1, under normal circumstances, give whole memory device power supply by system power supply, guarantee the memory device normal operation; During the unexpected power down of system power supply, powered to internal memory by battery, keep the data in the internal memory not lose; After system power supply was recovered normally, system power supply was given whole memory device power supply again, and the data of preserving in the internal memory are write hard disk.Yet the capacity of battery is limited, therefore the data hold time in the internal memory is limited, and can't persistence.If in the retention time, system power supply is not recovered at this section, the data in the internal memory still can be lost so;
Two, adopt the whole system mode of battery protection, as shown in Figure 2, under normal circumstances, give whole memory device power supply, the normal operation of assurance equipment by system power supply; During the unexpected power down of system power supply, switch to battery by battery to whole memory device power supply, the data that need in the internal memory to preserve are write specify shutdown system behind the hard disk; After system power supply was recovered normally, system power supply was given whole memory device power supply again, will specify the data reading of preserving in the hard disk, and write memory carries out follow-up work.Losing when although this mode can be avoided the data power down, the current ratio that needs to whole system power supply is larger, the data that need in the internal memory to preserve is all write specify behind the hard disk just shutdown system, battery capacity is required high, and the volume of battery is large.
Therefore, be necessary to study in fact, a kind of power down protection scheme is provided, can power the power down protection of realization system to storage subsystem in the situation that do not increase the battery volume.
Summary of the invention
For addressing the above problem; the object of the present invention is to provide a kind of power down protection system and its implementation; short, high to battery electric quantity demand problem of data loss problem and power down protection mode holding time during with the resolution system power down realizes not increasing in cost and the battery total capacity situation system is protected in the power supply power-fail situation.
For achieving the above object, technical scheme of the present invention is:
A kind of power down protection system, comprise for the system power supply of giving under normal circumstances system power supply in system, the South Bridge chip that is used for the various interface of control system, the interface translation circuit that is connected with South Bridge chip with CPU (central processing unit) (CPU), be connected with CPU (central processing unit), be used for and the CPU (central processing unit) direct communication non-volatile memory medium and the battery of the data that need protection when depositing the Installed System Memory of the current data of using and program and being used for the storage power down; Wherein, battery links to each other with South Bridge chip, non-volatile memory medium, interface translation circuit, Installed System Memory and CPU (central processing unit), is used for when system power failure each part mentioned above being powered; And CPU (central processing unit) (CPU) is connected with South Bridge chip and Installed System Memory, is used for when the system power supply power down, and the data of utilizing the South Bridge chip bus interface that internal memory is not preserved are sent to corresponding non-volatile memory medium.
Further, described interface translation circuit is connected with South Bridge chip and non-volatile memory medium, is used for the bus interface of South Bridge chip is converted to bus interface corresponding to non-volatile memory medium.
Further, described non-volatile memory medium is compact flash cards, multimedia card, enciphered digital card or flash chip.
Further, the bus interface of described South Bridge chip is interconnection bus of peripheral devices interface, Peripheral Component Interconnect high-speed bus interface, serial peripheral equipment interconnection high-speed bus interface, interconnection bus of peripheral devices expansion interface, serial ATA interface, system for serial small computer interface, ide interface or USB (universal serial bus), or the combination in any of its above-mentioned interface.
Further, the bus interface of described non-volatile memory medium is ide interface, local bus interface or Serial Peripheral Interface.
Another technical scheme of the present invention is:
A kind of power-off protection method comprises the steps:
When the system power supply power down, by interface translation circuit and the non-volatile memory medium power supply of battery to CPU, internal memory, South Bridge chip, south bridge and non-volatile memory medium;
The data of utilizing the South Bridge chip bus interface that internal memory is not preserved are sent to corresponding non-volatile memory medium;
When system power supply is recovered, by system power supply power supply, by South Bridge chip with the data reading preserved in the non-volatile memory medium and write described internal memory.
The present invention is when the system power supply power down, by interface translation circuit and the non-volatile memory medium power supply of battery to CPU, internal memory, South Bridge chip, south bridge and non-volatile memory medium; And the data of utilizing the South Bridge chip bus interface that internal memory is not preserved are sent to corresponding non-volatile memory medium, can realize not increasing in cost and the battery total capacity situation system is protected in the power supply power-fail situation.
Description of drawings
Fig. 1 is a kind of structural representation of power down protection in the prior art;
Fig. 2 is the another kind of structural representation of power down protection in the prior art;
Fig. 3 is the structural representation of power down protection system of the present invention;
Fig. 4 is the operating process schematic diagram of power-off protection method of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
Please refer to shown in Figure 3; power down protection system of the present invention includes for the system power supply of giving under normal circumstances system power supply in system, the South Bridge chip that is used for the various interface of control system, the interface translation circuit that is connected with South Bridge chip with CPU (central processing unit) (CPU), be connected with CPU (central processing unit); be used for and the CPU (central processing unit) direct communication non-volatile memory medium and the battery of the data that need protection when depositing the Installed System Memory of the current data of using and program and being used for the storage power down.Wherein, the interface translation circuit is connected with South Bridge chip and non-volatile memory medium, is used for the bus interface of South Bridge chip is converted to bus interface corresponding to non-volatile memory medium.And battery links to each other with South Bridge chip, non-volatile memory medium, interface translation circuit, Installed System Memory and CPU (central processing unit), is used for when system power failure each part mentioned above being powered.CPU (central processing unit) (CPU) is connected with South Bridge chip and Installed System Memory, is used for when the system power supply power down, and the data of utilizing the South Bridge chip bus interface that internal memory is not preserved are sent to corresponding non-volatile memory medium.
The present invention adopts non-volatile memory medium as the medium of power down protection storage, and the data of utilizing the bus of South Bridge chip by interface translation circuit between the two internal memory not to be preserved are preserved.Wherein, described non-volatile memory medium is compact flash cards (Compact Flash Card, CF), the various ways such as multimedia card (Multimedia Card, MMC), enciphered digital card (Secure Digital Card, SD) or flash memory (flash) chip; The bus interface of described South Bridge chip is interconnection bus of peripheral devices interface, Peripheral Component Interconnect high-speed bus interface, serial peripheral equipment interconnection high-speed bus interface, Peripheral Component Interconnect. bus expansion interface, serial ATA interface, system for serial small computer interface, ide interface or general serial, bus interface, or its above-mentioned combination in any; And the bus interface of described non-volatile memory medium is ide interface, local bus interface or Serial Peripheral Interface etc.
Power-off protection method of the present invention is specially: when the system power supply power down, by interface translation circuit and the non-volatile memory medium power supply of battery to CPU, internal memory, South Bridge chip, south bridge and non-volatile memory medium; The data of utilizing the South Bridge chip bus interface that internal memory is not preserved are sent to corresponding non-volatile memory medium; When system power supply is recovered, by system power supply power supply, by South Bridge chip with the data reading preserved in the non-volatile memory medium and write described internal memory.
In the embodiment of the invention, the data of utilizing the bus interface of South Bridge chip that internal memory is not preserved are input to corresponding a plurality of non-volatile memory mediums; Or the data communication device that a plurality of untapped bus interface of utilizing South Bridge chip is not preserved internal memory is crossed the parallel a plurality of non-volatile memory mediums that are input to correspondence of described interface translation circuit.
Concrete operations flow process diagram when Fig. 4 is power-off protection method application of the present invention, wherein, the concrete steps flow process is as follows:
Step 001: storage system normal operation;
Step 002: judging whether power down of system power supply, is execution in step 004 then, otherwise execution in step 003;
Step 003: by the system power supply power supply, finish;
Step 004: give described South Bridge chip, flash storage medium, interface translation circuit and internal memory power supply by battery;
Step 005: the data communication device that utilizes the bus interface of South Bridge chip that internal memory is not preserved is crossed described interface translation circuit and is sent to corresponding non-volatile memory medium, preserves complete rear shutdown system;
Step 006: start-up system after system power supply is recovered;
Step 007: judging the normal shutdown that whether shut down last time, is execution in step 008 then, otherwise execution in step 009;
Step 008: system normally starts;
Step 009: with data reading and the write memory preserved in the non-volatile memory medium, restart system by interface translation circuit and South Bridge chip;
Step 010: system's startup is finished.
The present invention adopts non-volatile memory medium as the storage medium of power down protection storage, because the power dissipation ratio of non-volatile flash memory storage card and flash chip is lower, therefore, can reduce the requirement to battery capacity; And; Non-volatile flash memory storage card and the development of flash chip capacity can improve the capacity of save data and the demand of memory size by the quantity that increases Nonvolatile memory card or chip rapidly, are easy to upgrading.Non-volatile memory medium has little, the lightweight characteristics of volume, saves system space, even increase the quantity of storage card, on the impact of system architecture also not too.In addition, the employing non-volatile memory medium is preserved the data in the internal memory when power down, and when system power supply was not recovered, data can persistence.Utilize system bus and the non-volatile memories of South Bridge chip, can realize under not increasing in cost and the battery total capacity situation the system power supply power-down conditions, protecting.Secondly, the memory size size that needs protection according to system is determined capacity and the number of devices of non-volatile memory medium, can also stop the power supply to other peripheral modules when power down protection, can reduce to greatest extent system power dissipation.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a power down protection system and its implementation, comprise for the system power supply of giving under normal circumstances system power supply in system, it is characterized in that: the interface translation circuit that also include South Bridge chip for the various interface of control system, is connected with South Bridge chip is with CPU (central processing unit) (CPU), be connected with CPU (central processing unit), be used for and the CPU (central processing unit) direct communication non-volatile memory medium and the battery of the data that need protection when depositing the Installed System Memory of the current data of using and program and being used for the storage power down; Wherein, battery links to each other with South Bridge chip, non-volatile memory medium, interface translation circuit, Installed System Memory and CPU (central processing unit), is used for when system power failure each part mentioned above being powered; And CPU (central processing unit) (CPU) is connected with South Bridge chip and Installed System Memory, is used for when the system power supply power down, and the data of utilizing the South Bridge chip bus interface that internal memory is not preserved are sent to corresponding non-volatile memory medium.
2. power down protection system as claimed in claim 1, it is characterized in that: described interface translation circuit is connected with South Bridge chip and non-volatile memory medium, is used for the bus interface of South Bridge chip is converted to bus interface corresponding to non-volatile memory medium.
3. power down protection system as claimed in claim 2, it is characterized in that: described non-volatile memory medium is compact flash cards, multimedia card, enciphered digital card or flash chip.
4. power down protection system as claimed in claim 3; it is characterized in that: the bus interface of described South Bridge chip is interconnection bus of peripheral devices interface, Peripheral Component Interconnect high-speed bus interface, serial peripheral equipment interconnection high-speed bus interface, interconnection bus of peripheral devices expansion interface, serial ATA interface, system for serial small computer interface, ide interface or USB (universal serial bus), or the combination in any of its above-mentioned interface.
5. power down protection system as claimed in claim 4, it is characterized in that: the bus interface of described non-volatile memory medium is ide interface, local bus interface or Serial Peripheral Interface.
6. a power-off protection method is characterized in that, comprises the steps:
When the system power supply power down, by interface translation circuit and the non-volatile memory medium power supply of battery to CPU, internal memory, South Bridge chip, south bridge and non-volatile memory medium;
The data of utilizing the South Bridge chip bus interface that internal memory is not preserved are sent to corresponding non-volatile memory medium;
When system power supply is recovered, by system power supply power supply, by South Bridge chip with the data reading preserved in the non-volatile memory medium and write described internal memory.
7. power-off protection method as claimed in claim 6 is characterized in that: the data of utilizing the bus interface of South Bridge chip that internal memory is not preserved are input to corresponding a plurality of non-volatile memory mediums; Or the data communication device that a plurality of untapped bus interface of utilizing South Bridge chip is not preserved internal memory is crossed the parallel a plurality of non-volatile memory mediums that are input to correspondence of described interface translation circuit.
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| CN 201310001287 CN103064800A (en) | 2013-01-04 | 2013-01-04 | Power failure protection system and implementation method thereof |
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| CN 201310001287 CN103064800A (en) | 2013-01-04 | 2013-01-04 | Power failure protection system and implementation method thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104239239A (en) * | 2013-06-17 | 2014-12-24 | 瑞祺电通股份有限公司 | Online synchronous backup system method and online synchronous backup system device |
| CN106872908A (en) * | 2017-04-26 | 2017-06-20 | 安徽优旦科技有限公司 | BMS system exception power down SOC guard methods |
| CN107807863A (en) * | 2017-10-26 | 2018-03-16 | 郑州云海信息技术有限公司 | A kind of method and system that CPU Cache data are protected after AC power down |
| CN112131619A (en) * | 2020-09-30 | 2020-12-25 | 天津津航计算技术研究所 | Multi-level data protection circuit and method |
| CN113946290A (en) * | 2021-10-14 | 2022-01-18 | 西安紫光国芯半导体有限公司 | Storage device based on three-dimensional heterogeneous integration and storage system |
| CN117389789A (en) * | 2023-12-08 | 2024-01-12 | 四川恒湾科技有限公司 | Power-down information storage and reporting method and system for O-RU equipment |
-
2013
- 2013-01-04 CN CN 201310001287 patent/CN103064800A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104239239A (en) * | 2013-06-17 | 2014-12-24 | 瑞祺电通股份有限公司 | Online synchronous backup system method and online synchronous backup system device |
| CN106872908A (en) * | 2017-04-26 | 2017-06-20 | 安徽优旦科技有限公司 | BMS system exception power down SOC guard methods |
| CN107807863A (en) * | 2017-10-26 | 2018-03-16 | 郑州云海信息技术有限公司 | A kind of method and system that CPU Cache data are protected after AC power down |
| CN112131619A (en) * | 2020-09-30 | 2020-12-25 | 天津津航计算技术研究所 | Multi-level data protection circuit and method |
| CN113946290A (en) * | 2021-10-14 | 2022-01-18 | 西安紫光国芯半导体有限公司 | Storage device based on three-dimensional heterogeneous integration and storage system |
| CN117389789A (en) * | 2023-12-08 | 2024-01-12 | 四川恒湾科技有限公司 | Power-down information storage and reporting method and system for O-RU equipment |
| CN117389789B (en) * | 2023-12-08 | 2024-03-08 | 四川恒湾科技有限公司 | Power-down information storage and reporting method and system for O-RU equipment |
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