CN108132857A - A kind of FPGA off-positions Exact recovery method - Google Patents
A kind of FPGA off-positions Exact recovery method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
- G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
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Abstract
The present invention provides a kind of FPGA off-positions Exact recovery method, this method adds energy storage and voltage comparator circuit module first outside FPGA, then state is divided for FPGA originals data processing function, determine that state stores information, chip subregion is configured in FPGA later, and detection of power loss and status processing module are added inside FPGA；When FPGA is powered off in data processing, by current state storage information write-in configuration chip, when FPGA restores electricity, reading state storage information, restores state during power-off from configuration chip.The method of the present invention realizes that the off-position of FPGA is restored using energy storage and state cache, compared with the periodic recording mode for extending out nonvolatile storage, higher off-position can be obtained and restore precision, simultaneously because memory accesses are greatly reduced, chip usage time can effectively be extended, enhance the reliability of system work.
Description
Technical field
The invention belongs to off-position restoration methods technical fields, are related to a kind of FPGA off-positions Exact recovery method.
Background technology
Field programmable gate array (Field Programmable Gate Array, FPGA) integrated level is high, the speed of service
Soon, the numerous areas such as space flight, medical treatment are widely used to.But due to FPGA, configuration information is lost after a power failure, can not preserve
Working condition when electric exists in extensive, long-time data processing application and restricts.
Previous FPGA off-positions restoration methods mostly by the way of nonvolatile storage is extended out, periodically will by FPGA
Outer extension memory is written in work state information, restores FPGA according to the final data of write-in memory when restoring electricity after a loss of power
Working condition.Although this mode is realized simple and meets specific state recovery demand to a certain extent, it is limited to
Extend out access cycle and the reading-writing life-span of nonvolatile storage, there are off-positions to restore inaccurate, long-time work for system design
The shortcomings of making poor reliability.
Invention content
(1) goal of the invention
The purpose of the present invention is：The defects of overcoming in the prior art provides a kind of FPGA off-positions Exact recovery method,
It improves FPGA off-positions and restores accuracy and the reliability that works long hours.
(2) technical solution
In order to solve the above technical problem, the present invention provides a kind of FPGA off-positions Exact recovery system, including：Storage
Can and voltage comparator circuit module, be arranged on outside FPGA, for the off-position that judges FPGA and for power-off FPGA in short-term
Between maintain power supply；Detection of power loss and status processing module, are arranged on inside FPGA, for determining the standard of FPGA power down judging results
True property, and key state data carry out integration caching in stage, sub-stage and the sub-stage that FPGA current datas are handled,
Chip is configured in the external FPGA of data cached write-in when FPGA is powered off, caching is read from FPGA configuration chips when FPGA is powered on
Data, for carrying out state recovery to FPGA；Former data processing function module, it is whole for the key state data of FPGA to be carried out
It closes, is read for detection of power loss and status processing module.
Wherein, the energy storage and voltage comparator circuit module include storage capacitor, transient state suppression circuit module, anti-return two
Pole pipe and voltage comparator circuit module, anti-return diode one end connect the anode of power supply, and the connection of transient state suppression circuit module is anti-
The cathode of reflux diode and power supply, storage capacitor and transient state suppression circuit wired in parallel, voltage comparator circuit module connection electricity
Source anode, the anti-return diode other end and detection of power loss and status processing module, the both ends connection FPGA of storage capacitor；Energy storage
Capacitance is for maintenance power supply in the short time after a loss of power；Transient state suppression circuit module is used to carry out transient state suppression to supply voltage
System；Current reflux when anti-return diode is for avoiding storage capacitor maintenance power supply after a loss of power, so as to extend FPGA after power-off
Working time；Voltage comparator circuit module is made of accurate divider resistance and voltage comparator, and accurate divider resistance is used for will
The range that the limiting voltage of two input terminal of comparator allows in device, while can be compared according to the positive pressure difference of anti-return diode
It is poor compared with two input terminal voltage of device to be adjusted, power down is avoided to judge by accident.
Wherein, voltage transformation module is also connected between the storage capacitor and FPGA, turned for the voltage of FPGA will to be supplied
It is changed to the range of voltage values that FPGA is applicable in.
Wherein, the former data processing function module includes input buffer module, data processing module and output caching mould
Block, input buffer module receive data input, and data are handled by data processing module and determine that state stores information, place
Data after reason carry out data output by output buffer module；Data processing module connects detection of power loss and status processing module,
It is used for transmission state storage information.
Wherein, the FPGA configurations chip is logically separated into Liang Ge areas, and subregion one divides for storing FPGA configuration data
For storage state storage information and state effective marker, whether state effective marker shows current state storage information in area two
Effectively.
Wherein, the detection of power loss and status processing module include major state machine, detection of power loss, state cache, verification,
State processing and configuration chip read-write totally 6 submodules, wherein major state loom module are used for according to powering on and off-position
Coordinate each module work；Detection of power loss submodule is used for filtering interference signals, ensures the accuracy of detection of power loss result；State is delayed
It deposits submodule and carries out integration caching for key state data in the stage, sub-stage and the sub-stage that handle current data, and
Be sent to verification submodule by data cached, at the same receive check results and by the result be added to it is former it is data cached in；Verification
Submodule can both verify stage, sub-stage data and the key state data for integrating caching, generate verification data,
The state storage information read back from configuration chip can be verified, confirm the correctness of data；State processing submodule exists
It is responsible for control configuration chip when FPGA is powered on and reads and writes submodule reading state effective marker and state storage letter from configuration chip
Breath, and carry out state recovery is determined whether according to the verification situation of effective marker and state storage information, it is born when FPGA is powered off
Duty reading state from state cache submodule stores information, and is judged whether according to the stage that current data is handled by the information
Configuration chip is written with state effective marker；Configuration chip read-write submodule is used to implement the number to FPGA configuration chips subregion two
According to read-write；After the completion of detection of power loss and status processing module addition, exploitation tool generation FPGA configuration data, and pass through
Downloading wire will be in data programming to one space of subregion of configuration chip.
The present invention also provides a kind of FPGA off-positions Exact recovery methods, include the following steps：
Step 1 adds energy storage and voltage comparator circuit module outside FPGA；
Step 2 divides state for FPGA originals data processing function, determines that state stores information；
Chip subregion is configured in FPGA by step 3；
Step 4 adds detection of power loss and status processing module inside FPGA；
It is powered off in step 5, FPGA data processing procedure, by current state storage information write-in configuration chip；
Step 6, FPGA restore electricity, and reading state storage information, restores state during power-off from configuration chip.
Wherein, in the step 2, FPGA original data processing functions are the originals inside FPGA in addition to off-position restores function
Some data processing functions；It determines that state stores information, is that FPGA original data processing functions are divided into several stages, then will
Each divided stages are several sub-stages, the key state data that each sub-stage needs record are determined, by these key states
Data and stage, sub-stage data carry out integration verification, and the integration information for having added in verification data is determined as state storage
Information.
Wherein, in the step 5, when FPGA is powered off, voltage comparator circuit module output reverse phase, the power down inspection of FPGA inside
It surveys submodule confirmation after interference is filtered out and is currently at power-down state, the state of current cache storage information is sentenced later
It is disconnected；If current data has handled completion, without chip write operation is configured, directly terminate；If current data is not located
Reason is completed, then by two space of subregion of the state storage information write-in configuration chip with verification data, while chip will be configured
Interior state effective marker is set to effective status.
Wherein, in the step 6, when restoring electricity, FPGA first from configuration chip in reading state effective marker and
State stores information, if state effective marker is invalid state, need not carry out state recovery, FPGA original data processing functions
Module directly works；If state effective marker is effective status, state storage information is verified, if check results
Correctly, then state recovery is carried out, i.e. use state storage information restores data processing state, and state is had criterion later
Will is set to invalid state；If check results mistake, restore without state, but there is still a need for state effective marker is set to nothing
Effect state；After state effective marker is set in vain, former data processing function module work, until power-off.
(3) advantageous effect
The FPGA off-position Exact recovery methods that above-mentioned technical proposal is provided, first outside FPGA add energy storage and
Then voltage comparator circuit module divides state for FPGA originals data processing function, determine that state stores information, later by FPGA
Chip subregion is configured, and detection of power loss and status processing module are added inside FPGA；When FPGA breaks in data processing
When electric, by current state storage information write-in configuration chip, when FPGA restores electricity, reading state stores from configuration chip
Information restores state during power-off.This method realizes that the off-position of FPGA is restored using energy storage and state cache, non-with extending out
The periodic recording mode of volatile memory is compared, and can be obtained higher off-position and be restored precision, simultaneously because being greatly decreased
Memory accesses, can effectively extend chip usage time, enhance the reliability of system work.This method was being implemented
Power supply only need to be simply changed in journey and exports voltage comparator and introduces FPGA, without substantially being changed to FPGA hardware connection
It is dynamic, there is stronger practical value.
Description of the drawings
Fig. 1 is a kind of FPGA off-positions Exact recovery system connection relationship diagram of the present invention.
Fig. 2 is detection of power loss and status processing module operation stream in a kind of FPGA off-positions Exact recovery method of the present invention
Cheng Tu.
Specific embodiment
To make the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to the present invention's
Specific embodiment is described in further detail.
In order to improve the precision and functional reliability of the recovery of FPGA off-positions, present invention firstly provides a kind of FPGA power-off
State Exact recovery system, the system include：Energy storage and voltage comparator circuit module, are arranged on outside FPGA, for judging
The off-position of FPGA and the FPGA short time to power off maintain power supply；Detection of power loss and status processing module, are arranged on FPGA
Inside, for determining the accuracy of FPGA power down judging results, and stage, sub-stage and the sub- rank that FPGA current datas are handled
Key state data carry out integration caching in section, and the external FPGA of data cached write-in is configured chip when FPGA is powered off,
Chip reading cache data is configured from FPGA when FPGA is powered on, for carrying out state recovery to FPGA；Former data processing function mould
Block for the key state data of FPGA to be integrated, is read for detection of power loss and status processing module.
Wherein, energy storage and voltage comparator circuit module include storage capacitor, transient state suppression circuit module, anti-return diode
With voltage comparator circuit module, anti-return diode one end connects the anode of power supply, transient state suppression circuit module connection anti-return
The cathode of diode and power supply, storage capacitor and transient state suppression circuit wired in parallel, voltage comparator circuit module connection power supply is just
Pole, the anti-return diode other end and detection of power loss and status processing module, the both ends connection FPGA of storage capacitor；Storage capacitor
For maintaining power supply in the short time after a loss of power；Transient state suppression circuit module is used to carry out transient state inhibition to supply voltage；It is anti-
Reflux diode for avoid after a loss of power storage capacitor maintain power supply when current reflux, so as to extend power-off after FPGA work
Time；Voltage comparator circuit module is made of accurate divider resistance and voltage comparator, and accurate divider resistance is used for comparator
The range that the limiting voltage of two input terminals allows in device, while can be according to the positive pressure difference of anti-return diode to comparator two
Input terminal voltage difference is adjusted, and power down is avoided to judge by accident.
Voltage transformation module is also connected between storage capacitor and FPGA, is fitted for the voltage for supplying FPGA to be converted to FPGA
Range of voltage values.
Former data processing function module includes input buffer module, data processing module and output buffer module, and input is slow
Storing module receives data input, and data are handled by data processing module and determine that state stores information, treated counts
Data output is carried out according to by output buffer module；Data processing module connects detection of power loss and status processing module, is used for transmission
State stores information.
FPGA configuration chips are logically separated into Liang Ge areas, and for storing FPGA configuration data, subregion two is used for subregion one
Storage state stores information and state effective marker, and state effective marker shows whether current state storage information is effective.
Detection of power loss and status processing module include major state machine, detection of power loss, state cache, verification, state processing
Totally 6 submodules are read and write with configuration chip, wherein major state loom module powers on for basis and off-position coordinates each mould
Block works；Detection of power loss submodule is used for filtering interference signals, ensures the accuracy of detection of power loss result；State cache submodule
Integration caching is carried out, and number will be cached for key state data in the stage, sub-stage and the sub-stage that handle current data
According to being sent to verification submodule, at the same receive check results and by the result be added to it is former it is data cached in；Verified submodule both
Can to integrate caching stage, sub-stage data and key state data verify, generate verification data, can also to from
The state storage information that configuration chip reads back is verified, and confirms the correctness of data；State processing submodule is powered in FPGA
When be responsible for control configuration chip read and write submodule from configuration chip in reading state effective marker and state storage information, and according to
The verification situation of effective marker and state storage information determines whether carry out state recovery, is responsible for delaying from state when FPGA is powered off
It deposits in submodule reading state and stores information, and judged whether according to the stage that current data is handled the information and state is effective
Mark write-in configuration chip；Configuration chip read-write submodule is used to implement the reading and writing data to FPGA configuration chips subregion two；
After the completion of detection of power loss and status processing module addition, exploitation tool generation FPGA configuration data, and will by downloading wire
In data programming to one space of subregion of configuration chip.
Based on above-mentioned FPGA off-positions Exact recovery system, the present invention also provides a kind of FPGA off-positions Exact recoveries
Method adds energy storage and voltage comparator circuit module first outside FPGA, then divides shape for FPGA originals data processing function
State determines that state stores information, FPGA is configured chip subregion later, and detection of power loss and state processing are added inside FPGA
Module；When FPGA is powered off in data processing, current state storage information write-in configuration chip restores to supply in FPGA
When electric, reading state storage information, restores state during power-off from configuration chip.
This method realizes that the off-position of FPGA is restored using energy storage and state cache, with extending out nonvolatile storage
Periodic recording mode is compared, and can be obtained higher off-position and be restored precision, simultaneously because memory access is greatly reduced
Number can effectively extend chip usage time, enhance the reliability of system work.
Specifically, the method for the present invention includes the following steps：
Step 1 adds energy storage and voltage comparator circuit module outside FPGA；
Energy storage and voltage comparator circuit module are by storage capacitor, transient state suppression circuit module, anti-return diode and voltage
Comparison circuit module composition；Storage capacitor is for maintenance power supply in the short time after a loss of power；Transient state suppression circuit module is used for
Transient state inhibition is carried out to supply voltage；Electric current returns when anti-return diode is for avoiding storage capacitor maintenance power supply after a loss of power
Stream, so as to extend power-off after FPGA working time；Voltage comparator circuit module is by accurate divider resistance and voltage comparator structure
The range for being used to allow the limiting voltage of two input terminal of comparator in device into, accurate divider resistance, while can be according to preventing back
The positive pressure difference of stream diode is adjusted two input terminal voltage difference of comparator, and power down is avoided to judge by accident.
Step 2 divides state for FPGA originals data processing function, determines that state stores information；
FPGA original data processing functions are original data processing functions inside FPGA in addition to off-position restores function；
It determines that state stores information, is that FPGA original data processing functions are divided into several stages, if being then by each divided stages
Dry sub-stage determines the key state data that each sub-stage needs record, by these key state data and stage, sub-stage
Data carry out integration verification, and the integration information for having added in verification data is determined as state storage information.
Chip subregion is configured in FPGA by step 3；
The configuration chip of FPGA is logically separated into Liang Ge areas, subregion one is used to store FPGA configuration data, subregion two
Information and state effective marker are stored for storage state, state effective marker shows whether current state storage information has
Effect.
Step 4 adds detection of power loss and status processing module inside FPGA；
Detection of power loss and status processing module by major state machine, detection of power loss, state cache, verification, state processing and
Chip read-write totally 6 sub- module compositions are configured, wherein major state loom module is used for each with off-position coordination according to powering on
Module works；Detection of power loss submodule is used for filtering interference signals, ensures the accuracy of detection of power loss result；State cache submodule
Block is used for key state data in the stage, sub-stage and the sub-stage that handle current data and carries out integration caching, and will caching
Data are sent to verification submodule, at the same receive check results and by the result be added to it is former it is data cached in；Verify submodule
Both stage, sub-stage data and the key state data for integrating caching can be verified, and generated verification data, it can also be right
The state storage information read back from configuration chip is verified, and confirms the correctness of data；State processing submodule is on FPGA
It is responsible for control configuration chip when electric and reads and writes submodule reading state effective marker and state storage information from configuration chip, and root
Verification situation according to effective marker and state storage information determines whether carry out state recovery, is responsible for when FPGA is powered off from state
Reading state stores information in cache sub-module, and judges whether there is the information and state according to the stage that current data is handled
Valid flag write-in configuration chip；Configuration chip read-write submodule is used to implement the reading and writing data to FPGA configuration chips subregion two；
After the completion of detection of power loss and status processing module addition, exploitation tool generation FPGA configuration data, and pass through downloading wire
It will be in data programming to one space of subregion of configuration chip.
It is powered off in step 5, FPGA data processing procedure, by current state storage information write-in configuration chip；
When FPGA is powered off, voltage comparator circuit module output reverse phase, inside FPGA detection of power loss submodule filter out it is dry
Confirm after disturbing and be currently at power-down state, the state of current cache storage information is judged later；If current data is
It completes through processing, then without chip write operation is configured, directly terminates；If the untreated completion of current data, school will be carried
Two space of subregion of the state storage information write-in configuration chip of data is tested, while the state effective marker being configured in chip is put
For effective status.
Step 6, FPGA restore electricity, and reading state storage information, restores state during power-off from configuration chip；
When restoring electricity, FPGA reading state effective marker and state storage information first from configuration chip, if
State effective marker is invalid state, then need not carry out state recovery, FPGA original data processing function modules directly work；If
State effective marker is effective status, then state storage information is verified, if check results are correct, it is extensive to carry out state
Multiple, i.e. use state storage information restores data processing state, and state effective marker is set to invalid state later；Such as
Fruit check results mistake is then restored, but there is still a need for state effective marker is set to invalid state without state；Have by state
After valid flag is set in vain, former data processing function module work, until power-off.
It is as follows below in a specific example introduction FPGA off-positions Exact recovery method of the present invention：
The FPGA and configuration chip of this example select the EP3C55 and the EPCS128 with company of altera corp respectively, make
With Quartus II development environments, ALTASMI_PARALLEL and RAM are used:2-PORT totally 2 kinds of IP kernels, wherein ALTASMI_
PARALLEL is used to implement the read-write to chip EPCS128 is configured, RAM:2-PORT is used to build state cache submodule.
The application environment of this example is：Board where FPGA is input 28V power supplies, be converted to 28V power supplies inside board+
5V, and+5V is further converted into 3.3V, 2.5V and 1.2V and is powered for FPGA.A complicated algorithm is realized inside FPGA, due to repeatedly
Generation often, calculate that the time is long, if extending out nonvolatile storage mode using previous, FPGA need when calculating repeatedly to
Data are written in nonvolatile storage, necessarily affect the service life of memory, and be limited to extend out the access of nonvolatile storage
Period, FPGA can not at a high speed, uninterrupted must carry out data write-in, therefore off-position accurately can not be recorded.And it uses
The cache way of this method can then realize the accurate writing function of off-position, and due to this method only logarithm in abnormal power-down
According to being recorded, therefore can significantly extend chip usage time, the chip service life is improved, is as follows：
Step 1 adds energy storage and voltage comparator circuit module outside FPGA；
Energy storage and voltage comparator circuit module are by storage capacitor, transient state suppression circuit module, anti-return diode and voltage
Comparison circuit module composition；Storage capacitor uses 2 2600uF capacitances in this example, and transient state suppression circuit module is using transient state electricity
Constrain diode 5KP33A processed, anti-return diode uses HRS20100C, and voltage comparator circuit module uses LM139D, accurately
47K, 4.7K and 51K of 1% precision, 4.7K divider resistances is respectively adopted in divider resistance.
Step 2 divides state for FPGA originals data processing function, determines that state stores information；
Will in FPGA realize algorithm data handling procedure be divided into M stage, the current generation is represented with j, j=1,2 ...,
M；Each stage is divided into N number of sub-stage, current sub-phase is represented with k, k=1,2 ..., N；Determine that each sub-stage needs to remember
Key state data a, b, c, d, e of record, will j, k, a, b, c, d, e integrate after carry out CRC check, obtain check code f, by j, k,
A, b, c, d, e, f are determined as state storage information Z.
Chip subregion is configured in FPGA by step 3；
The configuration chip EPCS128 of FPGA is logically separated into Liang Ge areas, subregion one is used to store FPGA configuration data,
Subregion two shows that Z is effective for storage state storage information Z and state effective marker V, V=1, and V=0 shows that Z is invalid.
Step 4 adds detection of power loss and status processing module inside FPGA；
Detection of power loss and status processing module by major state machine, detection of power loss, state cache, verification, state processing and
Chip read-write totally 6 sub- module compositions are configured, wherein state cache submodule is by RAM:2-PORT IP kernels are built, and chip is configured
Read-write submodule is built by ALTASMI_PARALLELIP cores, remaining submodule is built using logic, the verification submodule of structure
Data check is completed using CRC check mode；After the completion of detection of power loss and status processing module addition, Quartus II are utilized
Developing instrument generate FPGA configuration data, and pass through downloading wire will be in one space of subregion of data programming to EPCS128.
It is powered off in step 5, FPGA data processing procedure, by current state storage information write-in configuration chip；
When FPGA is powered off, voltage comparator circuit module output reverse phase, inside FPGA detection of power loss submodule filter out it is dry
Confirm after disturbing and be currently at power-down state, the state of current cache storage information Z is judged later；If j=M, k in Z
=N and a, b, c, d, e then without chip write operation is configured, directly terminate statistics indicate that current data has handled completion, no
Then by two space of subregion of state storage information Z write-in configuration chips, while the state effective marker V being configured in chip is set to
1。
Step 6, FPGA restore electricity, and reading state storage information, restores state during power-off from configuration chip；
When restoring electricity, FPGA reading state effective marker V and state storage information Z first from configuration chip, such as
Fruit V=0, then need not carry out state recovery, and FPGA original data processing function modules directly work；If V=1 deposits state
Storage information Z is verified, if check results are correct, carries out state recovery, i.e., using j, k, a, b, c, d, e is to data processing
State is restored, and V is set to 0 later；If check results mistake, restore without state, but there is still a need for V is set to 0；
After V is set to 0, former data processing function module work, until power-off.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformation can also be made, these are improved and deformation
Also it should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of FPGA off-positions Exact recovery system, which is characterized in that including：Energy storage and voltage comparator circuit module, if
It puts outside FPGA, for the off-position for judging FPGA and maintains power supply for the FPGA short time of power-off；Detection of power loss and shape
State processing module, is arranged on inside FPGA, for determining the accuracy of FPGA power down judging results, and will be at FPGA current datas
Key state data carry out integration caching in stage of reason, sub-stage and sub-stage, when FPGA is powered off by data cached write-in
External FPGA configuration chips, are configured chip reading cache data, for carrying out state to FPGA when FPGA is powered on from FPGA
Restore；Former data processing function module, for the key state data of FPGA to be integrated, for detection of power loss and state processing
Module is read.
2. FPGA off-positions Exact recovery system as described in claim 1, which is characterized in that the energy storage and voltage compare
Circuit module includes storage capacitor, transient state suppression circuit module, anti-return diode and voltage comparator circuit module, anti-return two
Pole pipe one end connects the cathode of the anode of power supply, transient state suppression circuit module connection anti-return diode and power supply, storage capacitor
With transient state suppression circuit wired in parallel, voltage comparator circuit module connection positive pole, the anti-return diode other end and power down
Detection and status processing module, the both ends connection FPGA of storage capacitor；Storage capacitor is for maintenance in the short time after a loss of power
Power supply；Transient state suppression circuit module is used to carry out transient state inhibition to supply voltage；Anti-return diode is used to avoid after a loss of power
Storage capacitor maintain power supply when current reflux, so as to extend power-off after FPGA working time；Voltage comparator circuit module is by essence
True divider resistance and voltage comparator are formed, and accurate divider resistance is used to permit the limiting voltage of two input terminal of comparator in device
Perhaps range, while two input terminal voltage difference of comparator can be adjusted according to the positive pressure difference of anti-return diode, it avoids
Power down is judged by accident.
3. FPGA off-positions Exact recovery system as claimed in claim 2, which is characterized in that the storage capacitor and FPGA
Between be also connected with voltage transformation module, for the voltage for supplying FPGA to be converted to the range of voltage values that FPGA is applicable in.
4. FPGA off-positions Exact recovery system as claimed in claim 3, which is characterized in that the original data processing function
Module includes input buffer module, data processing module and output buffer module, and input buffer module receives data input, by counting
Data are handled according to processing module and determine that state stores information, data that treated carry out data by output buffer module
Output；Data processing module connects detection of power loss and status processing module, is used for transmission state storage information.
5. FPGA off-positions Exact recovery system as claimed in claim 4, which is characterized in that the FPGA configurations chip exists
Liang Ge areas are logically divided into, subregion one is for storing FPGA configuration data, and subregion two is for storage state storage information and state
Effective marker, state effective marker show whether current state storage information is effective.
6. FPGA off-positions Exact recovery system as claimed in claim 5, which is characterized in that the detection of power loss and state
Processing module includes major state machine, detection of power loss, state cache, verification, state processing and the read-write of configuration chip totally 6 submodules
Block, wherein major state loom module power on for basis and off-position coordinates each module work；Detection of power loss submodule is used
In filtering interference signals, ensure the accuracy of detection of power loss result；State cache submodule is used for the rank handled current data
Key state data carry out integration caching, and be sent to verification submodule by data cached in section, sub-stage and sub-stage, simultaneously
Receive check results and by the result be added to it is former it is data cached in；Verifying submodule both can be to integrating the stage cached, son
Phase data and key state data are verified, and generate verification data, and the state that read back from configuration chip can also be stored
Information is verified, and confirms the correctness of data；State processing submodule is responsible for control configuration chip read-write when FPGA is powered on
Submodule reading state effective marker and state storage information from configuration chip, and information is stored according to effective marker and state
Verification situation determine whether carry out state recovery, be responsible for from state cache submodule reading state when FPGA is powered off and store
Information, and judged whether according to the stage that current data is handled by the information and state effective marker write-in configuration chip；Configuration
Chip read-write submodule is used to implement the reading and writing data to FPGA configuration chips subregion two；In detection of power loss and status processing module
After the completion of addition, exploitation tool generation FPGA configuration data, and pass through point of the downloading wire by data programming to configuration chip
In one space of area.
7. the FPGA off-position Exact recovery methods based on FPGA off-positions Exact recovery system described in claim 6,
It is characterized in that, includes the following steps：
Step 1 adds energy storage and voltage comparator circuit module outside FPGA；
Step 2 divides state for FPGA originals data processing function, determines that state stores information；
Chip subregion is configured in FPGA by step 3；
Step 4 adds detection of power loss and status processing module inside FPGA；
It is powered off in step 5, FPGA data processing procedure, by current state storage information write-in configuration chip；
Step 6, FPGA restore electricity, and reading state storage information, restores state during power-off from configuration chip.
8. based on FPGA off-positions Exact recovery method described in claim 7, which is characterized in that in the step 2, FPGA is former
Data processing function is original data processing function inside FPGA in addition to off-position restores function；Determine state storage letter
Breath, is that FPGA original data processing functions are divided into several stages, is then several sub-stages by each divided stages, determines every
These key state data and stage, sub-stage data are carried out integration school by the key state data that a sub-stage needs record
It tests, and the integration information for having added in verification data is determined as state storage information.
9. based on FPGA off-positions Exact recovery method described in claim 8, which is characterized in that in the step 5, in FPGA
During power-off, voltage comparator circuit module output reverse phase, FPGA inside detection of power loss submodules confirm current place after interference is filtered out
In power-down state, the state of current cache storage information is judged later；If current data has handled completion, no
Configuration chip write operation is carried out, is directly terminated；If the untreated completion of current data, the state with verification data is stored
Two space of subregion of information write-in configuration chip, while the state effective marker being configured in chip is set to effective status.
10. based on FPGA off-positions Exact recovery method described in claim 9, which is characterized in that in the step 6, extensive
When powering again, FPGA reading state effective marker and state storage information first from configuration chip, if state effective marker
For invalid state, then state recovery need not be carried out, FPGA original data processing function modules directly work；If state effective marker
For effective status, then state storage information is verified, if check results are correct, carry out state recovery, i.e., using shape
State storage information restores data processing state, and state effective marker is set to invalid state later；If check results
Mistake is then restored, but there is still a need for state effective marker is set to invalid state without state；It is set to by state effective marker
After invalid, former data processing function module work, until power-off.
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