CN108132857B - FPGA power-off state accurate recovery method - Google Patents
FPGA power-off state accurate recovery method Download PDFInfo
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- CN108132857B CN108132857B CN201711351397.9A CN201711351397A CN108132857B CN 108132857 B CN108132857 B CN 108132857B CN 201711351397 A CN201711351397 A CN 201711351397A CN 108132857 B CN108132857 B CN 108132857B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
- G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
Abstract
The invention provides an accurate recovery method of a power-off state of an FPGA (field programmable gate array). firstly, an energy storage and voltage comparison circuit module is added outside the FPGA, then, the state is divided for the original data processing function of the FPGA, state storage information is determined, then, an FPGA configuration chip is partitioned, and a power-off detection and state processing module is added inside the FPGA; when the FPGA is powered off in the data processing process, the current state storage information is written into the configuration chip, and when the FPGA recovers power supply, the state storage information is read from the configuration chip, and the state is recovered when the power is off. The method of the invention realizes the power-off state recovery of the FPGA by utilizing the energy storage and the state cache, can obtain higher power-off state recovery precision compared with the periodic recording mode of the externally expanded nonvolatile memory, and can effectively prolong the service time of a chip and enhance the working reliability of a system because the access times of the memory are greatly reduced.
Description
Technical Field
The invention belongs to the technical field of power failure state recovery methods, and relates to an FPGA power failure state accurate recovery method.
Background
The Field Programmable Gate Array (FPGA) has high integration level and high operation speed, and is widely applied to various fields such as aerospace, medical treatment and the like. However, because the configuration information of the FPGA is lost after power failure, the working state of the FPGA cannot be saved during power failure, and the FPGA has a limitation in large-scale and long-time data processing.
The traditional FPGA power-off state recovery method mainly adopts a mode of externally expanding a nonvolatile memory, the FPGA periodically writes working state information into the externally expanding memory, and the working state of the FPGA is recovered according to the last data written into the memory when power supply is recovered after power failure. Although the mode is simple to implement and meets the specific state recovery requirement to a certain extent, the mode is limited by the access cycle and the read-write life of the externally-extended nonvolatile memory, and the system design has the defects of inaccurate power-off state recovery, poor long-time working reliability and the like.
Disclosure of Invention
Objects of the invention
The purpose of the invention is: the method overcomes the defects in the prior art, and provides the accurate recovery method of the FPGA power-off state, so that the recovery accuracy of the FPGA power-off state and the long-time working reliability are improved.
(II) technical scheme
In order to solve the above technical problem, the present invention provides an accurate recovery system for a power-off state of an FPGA, which includes: the energy storage and voltage comparison circuit module is arranged outside the FPGA and used for judging the power-off state of the FPGA and maintaining power supply for the power-off FPGA for a short time; the power failure detection and state processing module is arranged in the FPGA and used for determining the accuracy of the FPGA power failure judgment result, integrating and caching key state data in the current data processing stage, the sub-stage and the sub-stage of the FPGA, writing the cached data into an externally-connected FPGA configuration chip when the FPGA is powered off, and reading the cached data from the FPGA configuration chip when the FPGA is powered on for performing state recovery on the FPGA; and the original data processing function module is used for integrating the key state data of the FPGA for power failure detection and state processing module reading.
The energy storage and voltage comparison circuit module comprises an energy storage capacitor, a transient suppression circuit module, an anti-backflow diode and a voltage comparison circuit module, wherein one end of the anti-backflow diode is connected with the positive electrode of a power supply, the transient suppression circuit module is connected with the anti-backflow diode and the negative electrode of the power supply, the energy storage capacitor is connected with the transient suppression circuit module in parallel, the voltage comparison circuit module is connected with the positive electrode of the power supply, the other end of the anti-backflow diode and a power failure detection and state processing module, and two ends of the energy storage capacitor are connected with an FPGA; the energy storage capacitor is used for maintaining power supply in a short time after power failure; the transient suppression circuit module is used for performing transient suppression on the power supply voltage; the anti-backflow diode is used for avoiding current backflow when the energy storage capacitor maintains power supply after power failure, so that the working time of the FPGA after power failure is prolonged; the voltage comparison circuit module is composed of an accurate divider resistor and a voltage comparator, the accurate divider resistor is used for limiting the voltages of two input ends of the comparator within the allowable range of the device, and meanwhile, the voltage difference of the two input ends of the comparator can be adjusted according to the forward voltage difference of the backflow prevention diode, so that power failure misjudgment is avoided.
And a voltage conversion module is also connected between the energy storage capacitor and the FPGA and used for converting the voltage supplied to the FPGA into a voltage value range suitable for the FPGA.
The original data processing function module comprises an input cache module, a data processing module and an output cache module, wherein the input cache module receives data input, the data processing module processes the data and determines state storage information, and the processed data is output by the output cache module; the data processing module is connected with the power failure detection and state processing module and used for transmitting state storage information.
The FPGA configuration chip is logically divided into two areas, wherein the first area is used for storing FPGA configuration data, the second area is used for storing state storage information and a state valid mark, and the state valid mark indicates whether the current state storage information is valid or not.
The power failure detection and state processing module comprises a main control state machine, 6 sub-modules in total, including a power failure detection module, a state cache module, a verification module, a state processing module and a configuration chip read-write module, wherein the main control state machine sub-module is used for coordinating the work of each module according to the power-on state and the power-off state; the power failure detection sub-module is used for filtering interference signals and ensuring the accuracy of a power failure detection result; the state cache submodule is used for integrating and caching key state data in the current data processing stage, the sub-stage and the sub-stage, sending the cached data to the verification submodule, receiving a verification result and adding the result into the original cached data; the checking submodule can check the stage and sub-stage data and the key state data of the integrated cache to generate checking data, and can also check the state storage information read back from the configuration chip to confirm the correctness of the data; the state processing submodule is responsible for controlling the configuration chip read-write submodule to read the state valid flag and the state storage information from the configuration chip when the FPGA is powered on, determining whether to perform state recovery according to the verification condition of the valid flag and the state storage information, and is responsible for reading the state storage information from the state cache submodule when the FPGA is powered off and judging whether to write the information and the state valid flag into the configuration chip according to the current data processing stage; the configuration chip read-write submodule is used for realizing data read-write of a second partition of the FPGA configuration chip; after the power failure detection and state processing module is added, FPGA configuration data are generated by using a development tool, and the data are burnt into a partition space of the configuration chip through a download line.
The invention also provides an accurate recovery method of the FPGA power-off state, which comprises the following steps:
step 1, adding an energy storage and voltage comparison circuit module outside an FPGA;
step 2, dividing states for the FPGA original data processing function, and determining state storage information;
step 3, partitioning the FPGA configuration chip;
step 4, adding a power failure detection and state processing module in the FPGA;
step 5, powering off in the FPGA data processing process, and writing the current state storage information into a configuration chip;
and 6, restoring power supply by the FPGA, reading state storage information from the configuration chip, and restoring the state during power failure.
In the step 2, the original data processing function of the FPGA is the original data processing function in the FPGA except the power-off state recovery function; and determining state storage information, namely dividing the original FPGA data processing function into a plurality of stages, then dividing each stage into a plurality of sub-stages, determining key state data required to be recorded in each sub-stage, performing integration verification on the key state data and the stage and sub-stage data, and determining the integration information added with verification data as the state storage information.
In the step 5, when the FPGA is powered off, the voltage comparison circuit module outputs an inverted phase, the power failure detection submodule inside the FPGA confirms that the FPGA is in a power failure state at present after interference is filtered, and then the state storage information cached at present is judged; if the current data is processed, the write operation of the configuration chip is not carried out, and the process is directly finished; if the current data is not processed, writing the state storage information with the check data into a partition two space of the configuration chip, and simultaneously setting a state valid flag in the configuration chip to be in a valid state.
In the step 6, when power supply is recovered, the FPGA reads the state valid flag and the state storage information from the configuration chip, and if the state valid flag is in an invalid state, the state recovery is not required, and the FPGA original data processing function module directly works; if the state valid flag is in a valid state, checking the state storage information, if the checking result is correct, performing state recovery, namely recovering the data processing state by using the state storage information, and setting the state valid flag to be in an invalid state; if the check result is wrong, the state recovery is not carried out, but the state valid mark still needs to be set to be in an invalid state; and after the state valid flag is set to be invalid, the original data processing functional module works until power is off.
(III) advantageous effects
According to the accurate recovery method for the power-off state of the FPGA, firstly, an energy storage and voltage comparison circuit module is added outside the FPGA, then, the state is divided for the original data processing function of the FPGA, state storage information is determined, then, the FPGA is configured into chip partitions, and a power-off detection and state processing module is added inside the FPGA; when the FPGA is powered off in the data processing process, the current state storage information is written into the configuration chip, and when the FPGA recovers power supply, the state storage information is read from the configuration chip, and the state is recovered when the power is off. The method utilizes the energy storage and the state cache to realize the power-off state recovery of the FPGA, can obtain higher power-off state recovery precision compared with a periodic recording mode of an externally-expanded nonvolatile memory, and can effectively prolong the service time of a chip and enhance the working reliability of a system because the access times of the memory are greatly reduced. In the implementation process, the method only needs to simply change the power supply and introduce the output of the voltage comparator into the FPGA, the hardware connection of the FPGA does not need to be greatly changed, and the method has high practical value.
Drawings
FIG. 1 is a schematic diagram of a connection relationship of an accurate recovery system for an FPGA power-off state according to the present invention.
FIG. 2 is a flow chart of the operation of the power down detection and status processing module in the method for accurately recovering the power down status of the FPGA.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
In order to improve the precision and the working reliability of the FPGA power-off state recovery, the invention firstly provides an FPGA power-off state accurate recovery system, which comprises: the energy storage and voltage comparison circuit module is arranged outside the FPGA and used for judging the power-off state of the FPGA and maintaining power supply for the power-off FPGA for a short time; the power failure detection and state processing module is arranged in the FPGA and used for determining the accuracy of the FPGA power failure judgment result, integrating and caching key state data in the current data processing stage, the sub-stage and the sub-stage of the FPGA, writing the cached data into an externally-connected FPGA configuration chip when the FPGA is powered off, and reading the cached data from the FPGA configuration chip when the FPGA is powered on for performing state recovery on the FPGA; and the original data processing function module is used for integrating the key state data of the FPGA for power failure detection and state processing module reading.
The energy storage and voltage comparison circuit module comprises an energy storage capacitor, a transient suppression circuit module, an anti-backflow diode and a voltage comparison circuit module, wherein one end of the anti-backflow diode is connected with the positive electrode of a power supply, the transient suppression circuit module is connected with the anti-backflow diode and the negative electrode of the power supply, the energy storage capacitor is connected with the transient suppression circuit module in parallel, the voltage comparison circuit module is connected with the positive electrode of the power supply, the other end of the anti-backflow diode and a power failure detection and state processing module, and two ends of the energy storage capacitor are connected with an FPGA; the energy storage capacitor is used for maintaining power supply in a short time after power failure; the transient suppression circuit module is used for performing transient suppression on the power supply voltage; the anti-backflow diode is used for avoiding current backflow when the energy storage capacitor maintains power supply after power failure, so that the working time of the FPGA after power failure is prolonged; the voltage comparison circuit module is composed of an accurate divider resistor and a voltage comparator, the accurate divider resistor is used for limiting the voltages of two input ends of the comparator within the allowable range of the device, and meanwhile, the voltage difference of the two input ends of the comparator can be adjusted according to the forward voltage difference of the backflow prevention diode, so that power failure misjudgment is avoided.
And a voltage conversion module is also connected between the energy storage capacitor and the FPGA and used for converting the voltage supplied to the FPGA into a voltage value range suitable for the FPGA.
The original data processing function module comprises an input cache module, a data processing module and an output cache module, wherein the input cache module receives data input, the data processing module processes the data and determines state storage information, and the processed data is output by the output cache module; the data processing module is connected with the power failure detection and state processing module and used for transmitting state storage information.
The FPGA configuration chip is logically divided into two areas, wherein the first area is used for storing FPGA configuration data, the second area is used for storing state storage information and a state valid mark, and the state valid mark indicates whether the current state storage information is valid or not.
The power failure detection and state processing module comprises 6 sub-modules including a main control state machine, power failure detection, state caching, verification, state processing and configuration chip reading and writing, wherein the main control state machine sub-module is used for coordinating the work of each module according to the power-on state and the power-off state; the power failure detection sub-module is used for filtering interference signals and ensuring the accuracy of a power failure detection result; the state cache submodule is used for integrating and caching key state data in the current data processing stage, the sub-stage and the sub-stage, sending the cached data to the verification submodule, receiving a verification result and adding the result into the original cached data; the checking submodule can check the stage and sub-stage data and the key state data of the integrated cache to generate checking data, and can also check the state storage information read back from the configuration chip to confirm the correctness of the data; the state processing submodule is responsible for controlling the configuration chip read-write submodule to read the state valid flag and the state storage information from the configuration chip when the FPGA is powered on, determining whether to perform state recovery according to the verification condition of the valid flag and the state storage information, and is responsible for reading the state storage information from the state cache submodule when the FPGA is powered off and judging whether to write the information and the state valid flag into the configuration chip according to the current data processing stage; the configuration chip read-write submodule is used for realizing data read-write of a second partition of the FPGA configuration chip; after the power failure detection and state processing module is added, FPGA configuration data are generated by using a development tool, and the data are burnt into a partition space of the configuration chip through a download line.
Based on the FPGA outage state accurate recovery system, the invention also provides an FPGA outage state accurate recovery method, firstly, an energy storage and voltage comparison circuit module is added outside the FPGA, then, the state is divided for the original data processing function of the FPGA, the state storage information is determined, then, the FPGA is configured with chip partitions, and a power failure detection and state processing module is added inside the FPGA; when the FPGA is powered off in the data processing process, the current state storage information is written into the configuration chip, and when the FPGA recovers power supply, the state storage information is read from the configuration chip, and the state is recovered when the power is off.
The method utilizes the energy storage and the state cache to realize the power-off state recovery of the FPGA, can obtain higher power-off state recovery precision compared with a periodic recording mode of an externally-expanded nonvolatile memory, and can effectively prolong the service time of a chip and enhance the working reliability of a system because the access times of the memory are greatly reduced.
Specifically, the method comprises the following steps:
step 1, adding an energy storage and voltage comparison circuit module outside an FPGA;
the energy storage and voltage comparison circuit module consists of an energy storage capacitor, a transient suppression circuit module, a backflow prevention diode and a voltage comparison circuit module; the energy storage capacitor is used for maintaining power supply in a short time after power failure; the transient suppression circuit module is used for performing transient suppression on the power supply voltage; the anti-backflow diode is used for avoiding current backflow when the energy storage capacitor maintains power supply after power failure, so that the working time of the FPGA after power failure is prolonged; the voltage comparison circuit module is composed of an accurate divider resistor and a voltage comparator, the accurate divider resistor is used for limiting the voltages of two input ends of the comparator within the allowable range of the device, and meanwhile, the voltage difference of the two input ends of the comparator can be adjusted according to the forward voltage difference of the backflow prevention diode, so that power failure misjudgment is avoided.
Step 2, dividing states for the FPGA original data processing function, and determining state storage information;
the original data processing function of the FPGA is the original data processing function in the FPGA except the power-off state recovery function; and determining state storage information, namely dividing the original FPGA data processing function into a plurality of stages, then dividing each stage into a plurality of sub-stages, determining key state data required to be recorded in each sub-stage, performing integration verification on the key state data and the stage and sub-stage data, and determining the integration information added with verification data as the state storage information.
Step 3, partitioning the FPGA configuration chip;
the configuration chip of the FPGA is logically divided into two areas, wherein the first area is used for storing FPGA configuration data, the second area is used for storing state storage information and a state valid mark, and the state valid mark indicates whether the current state storage information is valid or not.
Step 4, adding a power failure detection and state processing module in the FPGA;
the power failure detection and state processing module consists of 6 submodules, namely a main control state machine, power failure detection, state caching, verification, state processing and configuration chip reading and writing, wherein the main control state machine submodules are used for coordinating the work of each module according to the power-on state and the power-off state; the power failure detection sub-module is used for filtering interference signals and ensuring the accuracy of a power failure detection result; the state cache submodule is used for integrating and caching key state data in the current data processing stage, the sub-stage and the sub-stage, sending the cached data to the verification submodule, receiving a verification result and adding the result into the original cached data; the checking submodule can check the stage and sub-stage data and the key state data of the integrated cache to generate checking data, and can also check the state storage information read back from the configuration chip to confirm the correctness of the data; the state processing submodule is responsible for controlling the configuration chip read-write submodule to read the state valid flag and the state storage information from the configuration chip when the FPGA is powered on, determining whether to perform state recovery according to the verification condition of the valid flag and the state storage information, and is responsible for reading the state storage information from the state cache submodule when the FPGA is powered off and judging whether to write the information and the state valid flag into the configuration chip according to the current data processing stage; the configuration chip read-write submodule is used for realizing data read-write of a second partition of the FPGA configuration chip; after the power failure detection and state processing module is added, FPGA configuration data are generated by using a development tool, and the data are burnt into a partition space of the configuration chip through a download line.
Step 5, powering off in the FPGA data processing process, and writing the current state storage information into a configuration chip;
when the FPGA is powered off, the voltage comparison circuit module outputs an inverted phase, a power failure detection submodule inside the FPGA confirms that the FPGA is in a power failure state at present after interference is filtered, and then stored information of the state cached at present is judged; if the current data is processed, the write operation of the configuration chip is not carried out, and the process is directly finished; if the current data is not processed, writing the state storage information with the check data into a partition two space of the configuration chip, and simultaneously setting a state valid flag in the configuration chip to be in a valid state.
Step 6, the FPGA recovers power supply, reads state storage information from the configuration chip, and recovers the state during power failure;
when power supply is recovered, the FPGA reads a state valid flag and state storage information from the configuration chip, if the state valid flag is in an invalid state, state recovery is not needed, and an original data processing function module of the FPGA directly works; if the state valid flag is in a valid state, checking the state storage information, if the checking result is correct, performing state recovery, namely recovering the data processing state by using the state storage information, and setting the state valid flag to be in an invalid state; if the check result is wrong, the state recovery is not carried out, but the state valid mark still needs to be set to be in an invalid state; and after the state valid flag is set to be invalid, the original data processing functional module works until power is off.
The specific steps of the accurate recovery method for the power-off state of the FPGA are described as follows by a specific example:
the FPGA and the configuration chip of the embodiment respectively adopt EP3C55 of Altera and EPCS128 of the same company, use a Quartus II development environment, use ALTAMI _ PARALLEL and RAM:2-PORT to share 2 kinds of IP cores, wherein the ALTAMI _ PARALLEL is used for realizing reading and writing of the EPCS128 of the configuration chip, and the RAM:2-PORT is used for building a state cache submodule.
The application environment of this example is: the board card where the FPGA is located supplies power for inputting 28V, the 28V power supply is converted into +5V inside the board card, and the +5V is further converted into 3.3V, 2.5V and 1.2V to supply power for the FPGA. Due to the fact that iteration times are multiple and calculation time is long, if the traditional external expansion nonvolatile memory mode is adopted, the FPGA needs to write data into the nonvolatile memory for multiple times during calculation, the service life of the memory is influenced inevitably, the access cycle of the external expansion nonvolatile memory is limited, the FPGA cannot write the data at high speed and uninterruptedly, and therefore accurate recording of the power-off state cannot be achieved. The cache mode of the method can realize the function of accurately recording the power-off state, and the method can obviously prolong the service time of the chip and prolong the service life of the chip because the method records data only when abnormal power-off occurs, and the method comprises the following specific steps:
step 1, adding an energy storage and voltage comparison circuit module outside an FPGA;
the energy storage and voltage comparison circuit module consists of an energy storage capacitor, a transient suppression circuit module, a backflow prevention diode and a voltage comparison circuit module; in the example, 2 2600uF capacitors are adopted as the energy storage capacitors, a transient voltage suppression diode 5KP33A is adopted as the transient suppression circuit module, HRS20100C is adopted as the backflow prevention diode, LM139D is adopted as the voltage comparison circuit module, and 1% precision voltage dividing resistors of 47K, 4.7K, 51K and 4.7K are respectively adopted as the precise voltage dividing resistors.
Step 2, dividing states for the FPGA original data processing function, and determining state storage information;
dividing a data processing process for realizing an algorithm in the FPGA into M stages, wherein the current stage is represented by j, and j is 1, 2. Dividing each stage into N sub-stages, where the current sub-stage is denoted by k, k being 1, 2. Determining key state data a, b, c, d and e required to be recorded in each sub-stage, integrating j, k, a, b, c, d and e, then performing CRC to obtain a check code f, and determining j, k, a, b, c, d, e and f as state storage information Z.
Step 3, partitioning the FPGA configuration chip;
the configuration chip EPCS128 of the FPGA is logically divided into two areas, wherein one area is used for storing FPGA configuration data, the other area is used for storing state storage information Z and a state valid mark V, wherein the Z is valid when V is 1, and the Z is invalid when V is 0.
Step 4, adding a power failure detection and state processing module in the FPGA;
the power failure detection and state processing module consists of 6 submodules including a master control state machine, a power failure detection module, a state cache module, a verification module, a state processing module and a configuration chip read-write module, wherein the state cache submodule is constructed by a RAM (random access memory) -2-PORT IP core, the configuration chip read-write submodule is constructed by an ALTASMI-PARALLELIP core, the other submodules are constructed by logics, and the constructed verification submodule completes data verification by using a CRC (cyclic redundancy check) mode; after the power failure detection and state processing module is added, FPGA configuration data is generated by using a Quartus II development tool, and the data is burnt into a partition space of the EPCS128 through a download line.
Step 5, powering off in the FPGA data processing process, and writing the current state storage information into a configuration chip;
when the FPGA is powered off, the voltage comparison circuit module outputs an inverted phase, a power failure detection submodule inside the FPGA confirms that the FPGA is in a power failure state at present after interference is filtered, and then state storage information Z cached at present is judged; and if j is M, k N and a, b, c, d, e data in Z indicate that the current data has been processed, not performing configuration chip write operation, and ending directly, otherwise writing the state storage information Z into a partition two space of the configuration chip, and simultaneously setting a state valid flag V in the configuration chip to 1.
Step 6, the FPGA recovers power supply, reads state storage information from the configuration chip, and recovers the state during power failure;
when power supply is recovered, the FPGA reads a state valid flag V and state storage information Z from a configuration chip, if V is 0, state recovery is not needed, and an original data processing function module of the FPGA directly works; if V is 1, checking the state storage information Z, if the checking result is correct, performing state recovery, namely recovering the data processing state by using j, k, a, b, c, d, e, and then setting V to be 0; if the check result is wrong, the state recovery is not carried out, but V still needs to be set to be 0; and after the V is set to be 0, the original data processing functional module works until the power is cut off.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. The utility model provides an accurate recovery system of FPGA outage state which characterized in that includes: the energy storage and voltage comparison circuit module is arranged outside the FPGA and used for judging the power-off state of the FPGA and maintaining power supply for the power-off FPGA for a short time; the power failure detection and state processing module is arranged in the FPGA and used for determining the accuracy of the FPGA power failure judgment result, integrating and caching key state data in the current data processing stage, the sub-stage and the sub-stage of the FPGA, writing the cached data into an externally-connected FPGA configuration chip when the FPGA is powered off, and reading the cached data from the FPGA configuration chip when the FPGA is powered on for performing state recovery on the FPGA; and the original data processing function module is used for integrating the key state data of the FPGA for power failure detection and state processing module reading.
2. The accurate recovery system of the power-off state of the FPGA of claim 1 wherein the energy storage and voltage comparison circuit module comprises an energy storage capacitor, a transient suppression circuit module, a backflow prevention diode and a voltage comparison circuit module, wherein one end of the backflow prevention diode is connected to an anode of the power supply, the transient suppression circuit module is connected to the backflow prevention diode and a cathode of the power supply, the energy storage capacitor is connected in parallel with the transient suppression circuit module, the voltage comparison circuit module is connected to the anode of the power supply, the other end of the backflow prevention diode and the power-off detection and state processing module, and two ends of the energy storage capacitor are connected to the FPGA; the energy storage capacitor is used for maintaining power supply in a short time after power failure; the transient suppression circuit module is used for performing transient suppression on the power supply voltage; the anti-backflow diode is used for avoiding current backflow when the energy storage capacitor maintains power supply after power failure, so that the working time of the FPGA after power failure is prolonged; the voltage comparison circuit module is composed of an accurate divider resistor and a voltage comparator, the accurate divider resistor is used for limiting the voltages of two input ends of the comparator within the allowable range of the device, and meanwhile, the voltage difference of the two input ends of the comparator can be adjusted according to the forward voltage difference of the backflow prevention diode, so that power failure misjudgment is avoided.
3. The accurate recovery system of the FPGA power-off state of claim 2 wherein a voltage conversion module is further connected between the energy storage capacitor and the FPGA for converting the voltage supplied to the FPGA into a voltage value range suitable for the FPGA.
4. The FPGA off-state accurate recovery system according to claim 3, wherein the original data processing function module comprises an input cache module, a data processing module and an output cache module, the input cache module receives data input, the data processing module processes the data and determines state storage information, and the processed data is output by the output cache module; the data processing module is connected with the power failure detection and state processing module and used for transmitting state storage information.
5. The FPGA power-off state accurate recovery system of claim 4, wherein the FPGA configuration chip is logically divided into two regions, a first region is used for storing FPGA configuration data, and a second region is used for storing state storage information and a state valid flag, wherein the state valid flag indicates whether the current state storage information is valid.
6. The accurate recovery system of claim 5, wherein the power-down detection and status processing module comprises 6 sub-modules including a main control state machine, a power-down detection, a status cache, a verification, a status processing, and a configuration chip, wherein the main control state machine sub-module is configured to coordinate operations of the modules according to power-up and power-down states; the power failure detection sub-module is used for filtering interference signals and ensuring the accuracy of a power failure detection result; the state cache submodule is used for integrating and caching key state data in the current data processing stage, the sub-stage and the sub-stage, sending the cached data to the verification submodule, receiving a verification result and adding the result into the original cached data; the checking submodule can check the stage and sub-stage data and the key state data of the integrated cache to generate checking data, and can also check the state storage information read back from the configuration chip to confirm the correctness of the data; the state processing submodule is responsible for controlling the configuration chip read-write submodule to read the state valid flag and the state storage information from the configuration chip when the FPGA is powered on, determining whether to perform state recovery according to the verification condition of the valid flag and the state storage information, and is responsible for reading the state storage information from the state cache submodule when the FPGA is powered off and judging whether to write the information and the state valid flag into the configuration chip according to the current data processing stage; the configuration chip read-write submodule is used for realizing data read-write of a second partition of the FPGA configuration chip; after the power failure detection and state processing module is added, FPGA configuration data are generated by using a development tool, and the data are burnt into a partition space of the configuration chip through a download line.
7. The FPGA power-off state accurate recovery method based on the FPGA power-off state accurate recovery system of claim 6, characterized by comprising the following steps:
step 1, adding an energy storage and voltage comparison circuit module outside an FPGA;
step 2, dividing states for the FPGA original data processing function, and determining state storage information;
step 3, partitioning the FPGA configuration chip;
step 4, adding a power failure detection and state processing module in the FPGA;
step 5, powering off in the FPGA data processing process, and writing the current state storage information into a configuration chip;
and 6, restoring power supply by the FPGA, reading state storage information from the configuration chip, and restoring the state during power failure.
8. The FPGA power-off state accurate recovery method based on claim 7, characterized in that in the step 2, the original FPGA data processing function is the original FPGA data processing function except the power-off state recovery function; and determining state storage information, namely dividing the original FPGA data processing function into a plurality of stages, then dividing each stage into a plurality of sub-stages, determining key state data required to be recorded in each sub-stage, performing integration verification on the key state data and the stage and sub-stage data, and determining the integration information added with verification data as the state storage information.
9. The FPGA power-off state accurate recovery method based on claim 8, characterized in that in the step 5, when the FPGA is powered off, the voltage comparison circuit module outputs an inverted phase, the power-off detection sub-module in the FPGA confirms that the FPGA is in a power-off state currently after interference is filtered, and then the current cached state storage information is judged; if the current data is processed, the write operation of the configuration chip is not carried out, and the process is directly finished; if the current data is not processed, writing the state storage information with the check data into a partition two space of the configuration chip, and simultaneously setting a state valid flag in the configuration chip to be in a valid state.
10. The accurate recovery method of the power-off state of the FPGA according to claim 9, wherein in the step 6, when the power supply is recovered, the FPGA reads the state valid flag and the state storage information from the configuration chip at first, and if the state valid flag is in an invalid state, the state recovery is not required, and the FPGA original data processing function module directly works; if the state valid flag is in a valid state, checking the state storage information, if the checking result is correct, performing state recovery, namely recovering the data processing state by using the state storage information, and setting the state valid flag to be in an invalid state; if the check result is wrong, the state recovery is not carried out, but the state valid mark still needs to be set to be in an invalid state; and after the state valid flag is set to be invalid, the original data processing functional module works until power is off.
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