CN103984610A - FPGA (Field Programmable Gate Array) based power failure protection system and method - Google Patents
FPGA (Field Programmable Gate Array) based power failure protection system and method Download PDFInfo
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Abstract
The invention relates to an FPGA (Field Programmable Gate Array) based power failure protection system and an FPGA based power failure protection method. The system comprises a power failure detection module, a power supply module, a CPU (Central Processing Unit) minimum system, an FPGA processing module and a reset control module, wherein the power supply module is used for supplying power to other four parts respectively, the power failure detection module is used for detecting whether to power failure occurs and outputting a monitoring signal; the FPGA processing module is connected with the power failure detection module for detecting the monitoring signal output by the power failure detection module; the CPU minimum system is connected with the FPGA processing module for receiving a power failure warning signal from the FPGA processing module and outputting a reset control signal; the reset control module is connected with the CPU minimum system for resetting. The system overcomes the disadvantages that the used standby battery has large volume, high cost, short life, poor reliability and the like, and utilizes the own resources to provide a method for timely backing up and protecting system data and programs under a condition that the system is powered down suddenly, and the system has the advantages of small volume, low cost, easiness in realization, high reliability and the like.
Description
Technical field
The present invention relates to communications electronics technical field, especially relate to a kind of power down protection system and method based on FPGA.
Background technology
Along with communication and the development of electronic technology, the unfailing performance of equipment has been proposed to more and more higher requirement, under various emergency case, equipment can protection system, and normal Start-up and operating performance becomes one of the requisite standard of reliability of weighing afterwards.In the process of the unexpected power down of equipment, because the various piece of system is in uncontrollable level state, program file and data just may be destroyed, and the system that affects is normally moved.Therefore,, in the high equipment of reliability requirement, must provide power-down protection circuit.
At present, have the method for several power down protections: a kind of can be for equipment provides standby power supply, guarantee to break down or power down in the situation that, standby power supply may work as equipment and powers at primary power; Also have by reserve battery and coordinate charge-discharge circuit or power management chip, after system power supply power down, utilize reserve battery to power for equipment, assurance equipment part function operation within a period of time is normal.
Several method above all can guarantee equipment normal operation or the normal operation of part after power down, but also also has some problems in practical application:
1. use backup battery, need to weigh equipment power dissipation, cost, all many-sided requirements such as volume, especially, in the situation that current cost requirement is more and more higher, backup battery only just can be used under specific (special) requirements.
2. use battery, coordinate charge-discharge circuit or power management chip, for saving the functional requirement after cost and balance device looses power, use battery to become selection good in a lot of situations.But battery can take larger area when PCB layout, even requirement is not very high situation to equipment volume, also average life is short, reliability is poor, high in cost of production shortcoming, moreover the most more complicated of charge-discharge circuit, cost is higher again to increase power management chip.
Summary of the invention
The object of the invention is the defect existing in order to overcome classic method; utilize equipment existing resource; in the situation that not increasing cost; a kind of simple and quick method is provided, can, in power down moment, have detected power-off signal; and control reset control module; CPU minimum system to equipment resets, with protection system program file and data, and the normal start-up and operation of system after guaranteeing.
The invention provides a kind of power down protection system based on FPGA, comprise detection of power loss module, power module, CPU minimum system, FPGA processing module, reset control module;
The input end of power module is connected with the input end of detection of power loss module; The output terminal of power module is connected with detection of power loss module, FPGA processing module, CPU minimum system and reset control module respectively, and it is powered;
Detection of power loss module is connected with power module, the power down for detection of whether, and output monitoring signal;
The input end of FPGA processing module is connected with the output terminal of detection of power loss module, for detection of the pilot signal of detection of power loss module output;
The input end of CPU minimum system is connected with the output terminal of FPGA processing module, receives the power fail warning signal from FPGA processing module, and exports reseting controling signal;
Reset control module is connected with CPU minimum system, for it is resetted.
Further, described detection of power loss module comprises stabilivolt D1 and the optocoupler H1 linking together.
Further, the input of the power supply of described detection of power loss module is connected with stabilivolt D1 one end with R2 through divider resistance R1.
Further, between the described stabilivolt D1 other end and optocoupler H1, the current path being formed by R3 and R4.
Further, the output terminal of described optocoupler H1 is connected with pull-up resistor R5, and exports detection of power loss signal.
Further, described FPGA processing module comprises and receives I/O, sends I/O, Ir interface module, receive I/O respectively with send I/O, Ir interface module connects;
Receive I/O for receiving the power-off signal of detection of power loss module output; Send I/O for power-off signal is transmitted to CPU minimum system; In addition, FPGA also needs the interface by Ir, and power-off signal is reported to main equipment, produces alarm signal.
Further, described CPU minimum system mainly comprises the CPU processing module linking together, FLASH program storage block.
Further, described CPU processing module is used for receiving the power-off signal from FPGA processing module, and receives the reset signal of Self-resetting control module together with FLASH program storage block;
Further, described reset control module comprises system monitoring chip, for receiving the control signal from CPU processing module, produces reset signal simultaneously, and CPU minimum system is resetted.
Further, described power module comprises DC-DC conversion chip, energy storage inductor L1, the storage capacitor C1 connecting successively.
In addition, the present invention also provides a kind of power-off protection method, said method comprising the steps of:
The fluctuation of step 1, detection of power loss module output voltage, if voltage fluctuation arrives threshold value, causes that detection module Voltage-output changes;
Step 2, FPGA processing module detect level by I/O interface, and judge, if high level, explanation is power-down state; Being judged as low level, is normal condition;
Step 3, CPU minimum system detect the high level of FPGA processing module output, send reseting controling signal to the control module that resets;
Step 4, reset control module, after receiving control signal, start immediately, to CPU minimum system, send reset signal.
Detailed process is: under normal circumstances, output terminal is FPGA processing module through energy storage inductor L1 and storage capacitor C1 in the input of power module, CPU minimum system, and power-fail detection circuit and the power supply of reset control module, guarantee that it normally works.The power-off signal that power-fail detection circuit detects is normal.When power-down conditions appears in system, power module input voltage drops to certain threshold value, after power-fail detection circuit, output abnormality signal is to FPGA processing module, FPGA processing module detects abnormal signal, be transmitted to the CPU processing module of CPU minimum system, CPU processing module is sent control signal, control reset control module, reset control module is sent reset signal immediately to CPU minimum system, the modules such as CPU processing module wherein and FLASH program storage block are resetted, with this, come protection system program and data, assurance system can be after power supply input recovers normally, normal start-up and operation.
The invention has the advantages that:
Overcome use reserve battery volume large, cost is high, and the life-span is short; the shortcomings such as poor reliability, utilize the homegrown resource of system own, in the situation that not increasing additional circuit cost; provide a kind of under System Sudden power-down conditions, fast the method for timely backup and protection system data and program.Have volume little, cost is low, realizes easily high reliability.
Accompanying drawing explanation
Fig. 1 is the schematic block circuit diagram of the embodiment of the present invention.
Fig. 2 is the power module of the embodiment of the present invention, power-fail detection circuit block diagram.
Fig. 3 is the FPGA processing module of the embodiment of the present invention, CPU minimum system, reset control module block diagram.
Fig. 4 is the power-off protection method process flow diagram of the embodiment of the present invention.
embodiment
Below in conjunction with drawings and Examples, the invention will be further described.
As shown in Fig. 1 ~ Fig. 3, the present invention relates to a kind of power down protection system based on FPGA, comprise power module, owing to giving the power supply of system each several part and detection voltage is provided; Detection of power loss module, the power down for detection of whether; FPGA processing module, for receiving and forward detection of power loss signal; CPU minimum system, for receiving detection of power loss signal, and sends reseting controling signal; Reset control module, for exporting reset signal.
The input supply voltage of the input end connection device of power module, is detected voltage, and output terminal is connected with energy storage inductor L1 and storage capacitor C1, and after energy storage inductor and electric capacity, output voltage connects rear class link, and it is powered.
Because the power supply of equipment is often far above FPGA, I/O work and the interface voltages such as CPU, need to carry out dividing potential drop and processing by detecting voltage.The one-level dividing potential drop that normal work input voltage first forms through resistance R 1 and R2, then after stabilivolt D1, become the DC voltage of 3.2V left and right, input to the photoelectrical coupler with isolation and switching function.Photoelectrical coupler is comprised of two parts, is respectively light emitting diode and the triode with switching function.The collector of triode connects pull-up resistor to 3.3V(Power).The circuit that R2 and R3 form during in off state, provides current path at light emitting diode.The positive pole of light emitting diode connects stabilivolt D1 output, and negative pole connects one end of divider resistance R3.Light emitting diode is also connected with R4, the other end ground connection of R3.When supply voltage is normal, lumination of light emitting diode is when conducting state, and phototriode is in conducting state, and current collection is low level very, and detection of power loss signal is low level; Supply voltage declines, and drops to a certain threshold value, and light emitting diode is not luminous when off state, and phototriode is in cut-off state, and current collection is high level very, and detection of power loss signal is high level.
FPGA processing module, by I/O interface, receives the detection voltage of falling, and judges whether power down, on the one hand by status information, by Ir interface, reports upper level equipment, meanwhile, by I/O interface, status information is passed to the CPU processing module of CPU minimum system.CPU processing module receives power-down state, as is power-down state, just sends reseting controling signal, gives reset control circuit.Reset control circuit, after receiving the control signal that CPU processing module sends, resets CPU minimum system immediately.The system file of equipment etc. is all stored in Flash module, is comprised that the CPU minimum system of Flash resets before power down, has effectively protected system file.
As shown in Figure 4, the embodiment of the present invention also relates to a kind of circuit power fail safeguard method, comprises the following steps:
S401, equipment supply voltage, is civil power (48V direct current or 220V alternating current) process D.C. regulated power supply, converts direct supply to, is all generally stable output.But in some cases,, civil power possibility shakiness or abnormal power-down, cause source of stable pressure output to have the mains ripple of fluctuation equipment may reach threshold value;
S402, the output of detection of power loss module, the fluctuation of voltage arrives threshold value, causes that detection module Voltage-output changes, and goes to step S403;
S403, FPGA processing module is by I/O interface detection of power loss level, and judgement is as being high level, and explanation is power-down state, goes to step S404; Being judged as low level, is normal condition, goes to step S401;
S404, CPU detects the high level of FPGA processing module output, goes to step S405;
S405, sends reseting controling signal, goes to step S406;
S406, reset control circuit, after receiving control signal, starts immediately, sends reset signal, goes to step S407;
S407, reset CPU minimum system.
By above-mentioned example, can be found out; the invention provides a kind of power down protection guard method and circuit; overcome use reserve battery volume large; cost is high; the shortcomings such as the life-span is short, poor reliability, in the situation that not increasing additional circuit cost; provide a kind of under System Sudden power-down conditions, fast the method for timely backup and protection system data and program.
Above-mentioned example of the present invention is only for explanation method of the present invention realizes; any people who is familiar with this technology is in the disclosed technical scope of the present invention; all can expect easily its variation and replacement, so within protection domain of the present invention all should be encompassed in the protection domain being limited by claims.
Claims (10)
1. the power down protection system based on FPGA, is characterized in that: comprise detection of power loss module, power module, CPU minimum system, FPGA processing module, reset control module;
The input end of power module is connected with the input end of detection of power loss module; The output terminal of power module is connected with detection of power loss module, FPGA processing module, CPU minimum system and reset control module respectively, and it is powered;
Detection of power loss module, is connected with power module, the power down for detection of whether, and output monitoring signal;
The input end of FPGA processing module is connected with the output terminal of detection of power loss module, for detection of the pilot signal of detection of power loss module output;
The input end of CPU minimum system is connected with the output terminal of FPGA processing module, receives the power fail warning signal from FPGA processing module, and exports reseting controling signal;
Reset control module is connected with CPU minimum system, for it is resetted.
2. a kind of power down protection system based on FPGA as claimed in claim 1, is characterized in that: described detection of power loss module comprises stabilivolt D1 and the optocoupler H1 linking together.
3. a kind of power down protection system based on FPGA as claimed in claim 2, is characterized in that: the power supply input of described detection of power loss module is connected with stabilivolt D1 one end with R2 through divider resistance R1.
4. a kind of power-down protection apparatus based on FPGA as claimed in claim 3, is characterized in that: the current path being comprised of R3 and R4 between the described stabilivolt D1 other end and optocoupler H1.
5. a kind of power down protection system based on FPGA as claimed in claim 4, is characterized in that: the output terminal of described optocoupler H1 is connected with pull-up resistor R5, and exports detection of power loss signal.
6. a kind of power down protection system based on FPGA as claimed in claim 1, is characterized in that: described FPGA processing module comprises reception I/O, sends I/O, and Ir interface module receives I/O and is connected with transmission I/O, Ir interface module respectively.
7. a kind of power down protection system based on FPGA as claimed in claim 1, is characterized in that: described CPU minimum system comprises CPU processing module and the FLASH program storage block linking together.
8. a kind of power down protection system based on FPGA as claimed in claim 7, it is characterized in that: described CPU processing module is used for receiving the power-off signal from FPGA processing module, and receives the reset signal of Self-resetting control module together with FLASH program storage block; Described reset control module comprises system monitoring chip, for receiving the control signal from CPU processing module, produces reset signal simultaneously, and CPU minimum system is resetted.
9. a kind of power down protection system based on FPGA as claimed in claim 1, is characterized in that: described power module comprises DC-DC conversion chip, energy storage inductor L1, the storage capacitor C1 connecting successively.
10. utilize power down protection system described in claim 1 ~ 9 to carry out a method for power down protection, it is characterized in that: comprise the following steps,
The fluctuation of step 1, detection of power loss module output voltage, if voltage fluctuation arrives threshold value, causes that detection module Voltage-output changes;
Step 2, FPGA processing module detect level by I/O interface, and judge, if high level, explanation is power-down state; Being judged as low level, is normal condition;
Step 3, CPU minimum system detect the high level of FPGA processing module output, send reseting controling signal to the control module that resets;
Step 4, reset control module, after receiving control signal, start immediately, to CPU minimum system, send reset signal.
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| CN104461392A (en) * | 2014-12-08 | 2015-03-25 | 中北大学 | CH378-based high-speed serial data U disk recording device |
| CN104460440A (en) * | 2014-11-18 | 2015-03-25 | 中国兵器工业集团第二一四研究所苏州研发中心 | Programmable logic device internal highly-reliable automatic reset method |
| CN105426266A (en) * | 2014-08-15 | 2016-03-23 | 研祥智能科技股份有限公司 | Real-time clock calibration method and system |
| CN105739657A (en) * | 2016-02-02 | 2016-07-06 | 西安诺瓦电子科技有限公司 | Circuit structure applied to embedded system |
| WO2016110088A1 (en) * | 2015-01-06 | 2016-07-14 | 中兴通讯股份有限公司 | Method and apparatus for clearing power failure alarm information |
| CN106201775A (en) * | 2016-06-24 | 2016-12-07 | 广东电网有限责任公司电力科学研究院 | A kind of information power-down protection apparatus, guard method and embedded system |
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| WO2017054487A1 (en) * | 2015-09-30 | 2017-04-06 | 中兴通讯股份有限公司 | Power-down protection method and apparatus, and electronic device |
| CN107943259A (en) * | 2016-10-13 | 2018-04-20 | 普天信息技术有限公司 | Power-off reset method and apparatus based on VxWorks system |
| CN108132857A (en) * | 2017-12-15 | 2018-06-08 | 天津津航计算技术研究所 | A kind of FPGA off-positions Exact recovery method |
| CN109031038A (en) * | 2018-05-25 | 2018-12-18 | 烽火通信科技股份有限公司 | A kind of method and circuit for realizing power fail warning in PON far end system |
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| CN111162597A (en) * | 2018-11-08 | 2020-05-15 | 合肥欣奕华智能机器有限公司 | Power-down protection circuit and robot control system |
| CN111244881A (en) * | 2020-03-12 | 2020-06-05 | 甄十信息科技（上海）有限公司 | Method and device for automatically restarting electronic equipment in case of power failure or jamming |
| CN113391690A (en) * | 2021-07-07 | 2021-09-14 | 南京英锐创电子科技有限公司 | FLASH abnormal power failure protection circuit, device and method |
| CN113746061A (en) * | 2021-09-01 | 2021-12-03 | 中国航空工业集团公司西安航空计算技术研究所 | Short-time power failure recoverable system and short-time power failure recovering method |
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| CN105426266A (en) * | 2014-08-15 | 2016-03-23 | 研祥智能科技股份有限公司 | Real-time clock calibration method and system |
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| CN105739657A (en) * | 2016-02-02 | 2016-07-06 | 西安诺瓦电子科技有限公司 | Circuit structure applied to embedded system |
| CN106201775A (en) * | 2016-06-24 | 2016-12-07 | 广东电网有限责任公司电力科学研究院 | A kind of information power-down protection apparatus, guard method and embedded system |
| CN106292987B (en) * | 2016-08-09 | 2019-03-15 | 浪潮(北京)电子信息产业有限公司 | A kind of processor power-off sequential control system and method |
| CN106292987A (en) * | 2016-08-09 | 2017-01-04 | 浪潮(北京)电子信息产业有限公司 | A kind of processor power-off sequential control system and method |
| CN107943259A (en) * | 2016-10-13 | 2018-04-20 | 普天信息技术有限公司 | Power-off reset method and apparatus based on VxWorks system |
| CN108132857A (en) * | 2017-12-15 | 2018-06-08 | 天津津航计算技术研究所 | A kind of FPGA off-positions Exact recovery method |
| CN109031038A (en) * | 2018-05-25 | 2018-12-18 | 烽火通信科技股份有限公司 | A kind of method and circuit for realizing power fail warning in PON far end system |
| CN111162597A (en) * | 2018-11-08 | 2020-05-15 | 合肥欣奕华智能机器有限公司 | Power-down protection circuit and robot control system |
| CN111162597B (en) * | 2018-11-08 | 2021-08-24 | 合肥欣奕华智能机器有限公司 | Power-down protection circuit and robot control system |
| CN110224479A (en) * | 2019-05-22 | 2019-09-10 | 珠海格力电器股份有限公司 | A kind of power-down protection apparatus, control system and its power-off protection method |
| CN110308778A (en) * | 2019-06-24 | 2019-10-08 | 杭州迪普科技股份有限公司 | A kind of lower electric protection method and electronic equipment of CF card |
| CN111244881A (en) * | 2020-03-12 | 2020-06-05 | 甄十信息科技（上海）有限公司 | Method and device for automatically restarting electronic equipment in case of power failure or jamming |
| CN113391690A (en) * | 2021-07-07 | 2021-09-14 | 南京英锐创电子科技有限公司 | FLASH abnormal power failure protection circuit, device and method |
| CN113391690B (en) * | 2021-07-07 | 2024-04-23 | 南京英锐创电子科技有限公司 | FLASH abnormal power-down protection circuit, device and method |
| CN113746061A (en) * | 2021-09-01 | 2021-12-03 | 中国航空工业集团公司西安航空计算技术研究所 | Short-time power failure recoverable system and short-time power failure recovering method |
| CN113746061B (en) * | 2021-09-01 | 2023-06-23 | 中国航空工业集团公司西安航空计算技术研究所 | Short-time power failure recoverable system and short-time power failure recovery method |
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