CN105739657A - Circuit structure applied to embedded system - Google Patents
Circuit structure applied to embedded system Download PDFInfo
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- CN105739657A CN105739657A CN201610072835.7A CN201610072835A CN105739657A CN 105739657 A CN105739657 A CN 105739657A CN 201610072835 A CN201610072835 A CN 201610072835A CN 105739657 A CN105739657 A CN 105739657A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
Abstract
The invention relates to a circuit structure applied to an embedded system. The circuit structure has the functions of power down protection and false power down reset to solve the problem in the prior art that user or system files are damaged after equipment power down happens when embedded system equipment is used, and carries out function perfection and optimization processing on a traditional power down protection mechanism. Specifically, a power down signal sampling circuit and a power down reset control circuit are additionally arranged on a circuit structure with the power down protection mechanism in the prior art, and therefore, an operating system can automatically carry out system reset after the operating system in the embedded system enters a to-be-shutdown state due to false power down.
Description
Technical field
The present invention relates to embedded system technology field, particularly to a kind of circuit structure with power-down protection being applied to embedded system.
Background technology
Embedded system is a kind of dedicated computer system embedding and designing for application-specific inside controlled device.Generally believe embedded system be based on computer technology, software and hardware can cutting such that it is able to adapt to the dedicated computer system in practical application, function, reliability, cost, volume, power consumption being strict with.From hardware point of view it is believed that embedded system is control program storage flush bonding processor panel in memory, it is broadly divided into the hardware components such as processor, memorizer, input and output (I/O), wherein I/O part is made up of various functional peripheral hardwares, thus rich and varied embedded hardware function can be realized.From software respective, embedded OS is responsible for the distribution of whole soft and hardware resources of embedded system, task scheduling, controls, coordinates concurrent activities.Android, iOS etc. of μ C/OS-II, Linux, WindowsEmbedded, VxWorks and current comparatively main flow are had at present in the widely used operating system of built-in field.
But current Embedded System Product still suffers from more problem from stability angle; such as, lack protection under equipment burst power-down conditions or seldom have rational power down protection mechanism to strengthen system stability, because the file that operating system or user are stored sometimes by equipment under being not carried out the unexpected power-down conditions of system closedown order causes certain damage.The such as embedded system device of the existing WindowsEmbeddedCompact of use (being called for short WinCE) system, operating system file damages problem to have certain probability to occur after all there is device looses power.It is that the storage chip used when storage due to hardware device coordinates the defect brought with operating system that this problem produces.During equipment emergency power off, WinCE operating system does not do preservation process work, it is possible to damage user data, system file even has infringement cause the serious problems such as system cannot start.
As it is shown in figure 1, in former hardware scheme, preserve relevant circuit part to file from the 5V supply voltage of externally input by powering directly to system master circuit after anti-circnit NOT, simultaneous memory works.When the urgent power down of 5V input supply voltage, foregoing circuit part meeting directly power-off simultaneously, such memorizer is possible to situation irregular working occur, causes that system or user file are lost.
Therefore, for strengthening system stability, present invention applicant Xi'an Novastar Electronic Technology Co., Ltd. is 201510253611.1 at the application number of application on 05 18th, 2015, the Chinese invention patent application that denomination of invention is " being applied to circuit structure and the power-off protection method of embedded system " proposes a kind of power down protection mechanism, as shown in Figure 2, it is to increase power-down protection circuit and farad capacitor in hardware designs basis shown in Fig. 1, software design plays a role after system learns power-down state, namely triggering system level is interrupted after learning power-down state, process in function in interrupt status and do in stable condition monitoring, such as the down trigger really caused for power supply power-fail, notice application layer processes work.Do signal during application layer software design to wait, if obtaining the success of power-off message, carry out processing work, first user data is preserved, it is then shut off the program being currently running, last software sends order makes system enter suspend resting state and state to be shut down, after this action completes, farad capacitor has discharged, whole system power down；So the storage file of whole equipment is served protective effect.
During normal use, occurring that circuit structure shown in burst power-down conditions Fig. 2 can enter power down protection state in the manner described above, whole system obtains protection.But there is a kind of situation in use; if power supply recovers after there is short time shake; power-down protection circuit can be triggered equally; but it is non-genuine power-down state also; system can enter into state to be shut down according to normal processing mode equally; at this moment whole system is in a dormant state, and user cannot normally use systemic-function.As can be seen here, circuit structure shown in Fig. 2 yet suffers from the space of optimization further.
Summary of the invention
Therefore; the present invention proposes a kind of circuit structure being applied to embedded system, the problem damaged with user or system file after solving the device looses power occurred during embedded system device in prior art uses and existing power down protection mechanism is done perfect in shape and function and optimization process.
nullSpecifically，A kind of circuit structure being applied to embedded system that the embodiment of the present invention proposes，Including: power voltage input terminal、Power-down protection circuit、Storage capacitor、System master circuit and memorizer，Described power-down protection circuit electrically connects the power end of described power voltage input terminal and described system master circuit and external interrupt port and for producing system break to carry out whether power down process is in true power-down state to the supply voltage judging described power voltage input terminal and completes file after the supply voltage of described power voltage input terminal is in true power-down state and preserve to described memorizer and make system entrance state to be shut down through being triggered described system master circuit by described external interrupt port after the supply voltage power down monitoring described power voltage input terminal，Described storage capacitor electrically connects described power-down protection circuit and for being powered to the described power end of described system master circuit by described power-down protection circuit after the supply voltage power down of described power voltage input terminal.Furthermore, described in be applied to the circuit structure of embedded system and also include: power-off signal sample circuit and power-off reset control circuit；Wherein, described power-off signal sample circuit electrically connects described power voltage input terminal and has sampled voltage outfan, described power-off reset control circuit electrically connects the reset terminal of described sampled voltage outfan and described system master circuit and for judging whether the supply voltage of described power voltage input terminal is in true power-down state according to the sampled voltage of described sampled voltage outfan output, whether the supply voltage monitoring described power voltage input terminal after the supply voltage of described power voltage input terminal is in true power-down state recovers and produces the reseting controling signal reset terminal to described system master circuit after the supply voltage monitoring described power voltage input terminal recovers to be in the described system master circuit of state to be shut down with reset system.
In one embodiment of the invention, described power-off signal sample circuit includes the first resistance, the second resistance and electric capacity, described first resistance and described second resistance are serially connected between described power voltage input terminal and earthing potential, and described electric capacity and described first resistance concatenated and the second resistor coupled in parallel are between described power voltage input terminal and described earthing potential.
In one embodiment of the invention, described power-off reset control circuit includes microcontroller, and one the oneth I/O mouth of described microcontroller and one the 2nd I/O mouth are electrically connected described sampled voltage outfan and the described reset terminal of described system master circuit.
In one embodiment of the invention, described power-down protection circuit includes: status monitoring circuit, electrically connects described power voltage input terminal and for exporting the monitor value of the supply voltage whether power down representing described power voltage input terminal；State notifying circuit, electrically connect the described external interrupt port of described status monitoring circuit and described system master circuit, for judging the supply voltage whether power down of described power voltage input terminal according to described monitor value and producing power-down state after the supply voltage power down of described power voltage input terminal and inform the described external interrupt port of described system master circuit to trigger described system master circuit generation system break；And power down holding circuit, be connected electrically between the described power end of described power voltage input terminal and described system master circuit and electrically connect described storage capacitor, for when the non-power down of supply voltage of described power voltage input terminal to the charging of described storage capacitor and the supply voltage of described power voltage input terminal is transferred to the described power end of described system master circuit and be used at described power voltage input terminal supply voltage power down time utilize described storage capacitor to power to the described power end of described system master circuit.
In one embodiment of the invention, described state notifying circuit and described power-off reset control circuit share described microcontroller, and one the 3rd I/O mouth of described microcontroller is used for receiving described monitor value, and one the 4th I/O mouth of described microcontroller electrically connects the described external interrupt port of described system master circuit.
In one embodiment of the invention, described microcontroller is single-chip microcomputer or arm processor.
In one embodiment of the invention, described state notifying circuit is comparison circuit.
In one embodiment of the invention, described power down holding circuit includes: the first diode, resistance and the second diode；The positive electrical of described first diode connects described status monitoring circuit, and the negative electricity of described first diode connects the described power end of described system master circuit；Described resistance is connected electrically between negative pole and the described storage capacitor of described first diode, the positive electrical of described second diode connects the negative pole of negative electricity described first diode of connection of described storage capacitor and described second diode, thus described resistance and described second diodes in parallel are between the negative pole and described storage capacitor of described first diode.
In one embodiment of the invention, described storage capacitor is farad capacitor.
In one embodiment of the invention; the described circuit structure being applied to embedded system also includes anti-circnit NOT; described anti-circnit NOT has voltage input end and voltage output end; the described voltage input end of described anti-circnit NOT is as described power voltage input terminal; described power-down protection circuit electrically connects the described voltage output end of described anti-circnit NOT to realize electrically connecting described power voltage input terminal, and described power-off signal sample circuit electrically connects the described voltage output end of described anti-circnit NOT to realize electrically connecting described power voltage input terminal.
From the foregoing, it will be observed that the embodiment of the present invention can realize following beneficial effect: a) file can be protected after embedded system power down to be not damaged by；B) protection user data is not destroyed, and makes the reliability of user file increase；C) protection system file is not damaged by, and solves this problem and causes that system cannot the normal problem such as startup；And d) add power-down state erroneous judgement detection.
By the detailed description below with reference to accompanying drawing, other side and the feature of the present invention become apparent upon.It is understood that this accompanying drawing is only the purpose design of explanation, not as the restriction of the scope of the present invention.It should also be noted that unless otherwise noted, it is not necessary to scale accompanying drawing, they only try hard to structure described herein and flow process are described conceptually.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is existing a kind of module diagram preserving relevant circuit part to file.
Fig. 2 is the module diagram that existing another kind and file preserve relevant circuit part.
Fig. 3 is the module diagram that a kind of of the embodiment of the present invention and file preserve relevant circuit part.
Fig. 4 is the particular circuit configurations citing of status monitoring circuit shown in Fig. 3.
Fig. 5 is the particular circuit configurations citing of power down holding circuit shown in Fig. 3.
Fig. 6 is the particular circuit configurations citing of power-off signal sample circuit shown in Fig. 3.
Fig. 7 is the particular circuit configurations citing of power-off reset control circuit shown in Fig. 3.
Fig. 8 is the detection of power loss reset control flow chart that power-off reset control circuit shown in Fig. 3 performs.
Fig. 9 is a kind of operating system power down process realizing power down protection and the power-off reset flow chart of the embodiment of the present invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Referring to Fig. 3; a kind of circuit structure being applied to embedded system that the embodiment of the present invention provides has urgent power down protection and pseudo-power-off reset function, comprising: anti-circnit NOT 31, power-down protection circuit 33, farad capacitor 35, system master circuit 37, memorizer 38, power-off signal sample circuit 391 and power-off reset control circuit 393.
Wherein, anti-circnit NOT 31 has power voltage input terminal and voltage output end, described power voltage input terminal is for receiving the supply voltage V0 (such as 5V DC voltage) of input, and described voltage output end is for output voltage V1 (the 5V DC voltage after such as stablizing).In the present embodiment, anti-circnit NOT 31 is such as be made up of single diode, it is also possible to be formed by connecting by metal-oxide-semiconductor and resistance, or other various existing reverse connection prevention protection circuits.It is understood that anti-circnit NOT 31 protects circuit as one, it also contemplates for dispensing under some particular demands.
Power-down protection circuit 33 is connected electrically between voltage output end (V1 outfan) and the power end of system master circuit 27 of anti-circnit NOT 31, and it specifically comprises the steps that status monitoring circuit 331, state notifying circuit 333 and power down holding circuit 335.Wherein, status monitoring circuit 331 electrically connects the voltage output end of anti-circnit NOT 31 and for monitoring the partial pressure value of the output voltage V1 of the voltage output end of anti-circnit NOT 31 as monitor value, status monitoring circuit 331 typically pressure sampling circuit, such as shown in Fig. 4, pressure sampling circuit includes resistance R1 and resistance R2, resistance R1 and R2 is connected between voltage output end (V1 outfan) and the earthing potential of anti-circnit NOT 31, and the node voltage (namely partial pressure value of V1) between resistance R1 and R2 is as monitor value Vdet outfan.State notifying circuit 333 is connected electrically between monitor value Vdet outfan and the interruptive port of system master circuit 37 of status monitoring circuit 331, and it such as includes single-chip microcomputer；At this, single-chip microcomputer can utilize the monitor value Vdet outfan of an I/O mouth status of electrically connecting observation circuit 331, thus single-chip microcomputer can judge supply voltage (V0) the input whether power down of anti-circnit NOT 31 according to the monitor value Vdet received and generate power-down state notice when power down and produce system-level interruption with triggering system governor circuit 37, the I/O mouth that single-chip microcomputer is connected with the external interrupt port of system master circuit 37 is then as power-down state notice outfan；It is understandable that, single-chip microcomputer herein is mainly used for judging supply voltage (V0) the input whether power down of anti-circnit NOT 31 according to monitor value Vdet, therefore single-chip microcomputer can also replace to comparison circuit, by being compared to produce power-down state notice (such as representing high level or the low level value of comparative result) by monitor value Vdet and the reference voltage preset.The side a and b of power down holding circuit 335 is electrically connected status monitoring circuit 331 and the power end of system master circuit 37, and farad capacitor 35 mounts to power down holding circuit 335；In the present embodiment, as shown in Figure 5, power down holding circuit 335 such as includes diode D1, D2 and resistance R3, positive pole (A end) the such as V1 end shown in electrical connection graph 4 of diode D1, the power end of negative pole (B end) the electrical connection system governor circuit 37 of diode D1, resistance R3 and diode D2 is connected in parallel between the negative pole (B end) of farad capacitor 35 and diode D1；More specifically, the positive electrical of diode D2 connects the negative pole (B end) of the negative electricity connection diode D1 of farad capacitor 35 and diode D2.
Farad capacitor 35 belongs to double layer capacitor, its for store electric energy and when power down power end to system master circuit 37 power；It is understood that farad capacitor 35 can also replace to other type storage capacitor with enough electrical power storage abilities.
System master circuit 37 is as the main control part of embedded system, and it typically can be provided with operating system such as WindowsCE operating system.In the present embodiment, system master circuit 37 such as includes microprocessor such as arm processor etc., memory read/write circuit and other peripheral circuit.
Memorizer 38 electrical connection system governor circuit 37, it is such as nonvolatile memory, as flash memory (such as NANDFLASH) etc., is not specifically limited at this.
Power-off signal sample circuit 391 is connected electrically between voltage output end (V1 outfan) and the power-off reset control circuit 393 of anti-circnit NOT 31, it is such as shown in Fig. 6, including resistance R4 and R5 being serially connected between voltage output end (V1 outfan) and the earthing potential of anti-the circnit NOT 31 and electric capacity C1 being connected between V1 outfan and earthing potential, namely electric capacity C1 and series resistor R4, R5 is in parallel, and the node voltage between resistance R4 and R5 is sampled voltage Vs.
Power-off reset control circuit 393 electrically connects between sampled voltage Vs outfan and the reset terminal of system master circuit 37 of power-off signal sample circuit 391, it is such as shown in Fig. 7, including single-chip microcomputer such as STM8S003F3 single-chip microcomputer and connect single-chip microcomputer necessary circuitry element as resistance, electric capacity etc..
Power-off signal sample circuit 391 passes through R4, R5 electric resistance partial pressure obtains analogue signal (namely the sampled voltage Vs) input pin 20 to the I/O mouth such as STM8S003F3 single-chip microcomputer of single-chip microcomputer, obtain digital voltage value after being carried out analog-to-digital conversion process by single-chip microcomputer to judge whether enter power-down state and judge that whether power-down state is stable again through software algorithm, judging that power-down state stable (namely V0 is in true power-down state), if power loss recovery signal being detected afterwards, initiates reseting controling signal to system master circuit 37, the operating system making system master circuit 37 resets again, thus departing from pseudo-power-down state, and then the state to be shut down after making system no longer rest on power down protection.
Specifically, as shown in Figure 8, the software of SCM Based power-off reset control circuit 393 enters power down waiting state after it initializes I/O and intervalometer, if create power-off signal by detecting sampled voltage Vs and trigger entrance power-off signal judgement of stability, if being that (corresponding power-down state is stable for true power-off signal really, namely V0 is in true power-down state), then single-chip microcomputer enters power loss recovery level monitoring state (namely waiting power loss recovery level)；If now the supply voltage V0 of the power voltage input terminal of anti-circnit NOT 31 recovers again, then judge that this power-down state is as pseudo-power-down state, thus initiating reseting controling signal and such as sending the reset terminal to system master circuit 37 by the pin 10 of the STM8S003F3 of Fig. 7, with the operating system of reset system master circuit 37, it is further continued for cycle detection afterwards；If waiting time-out, then the true power down of decision-making system enters done state.
Additionally, refer to Fig. 9, it realizes operating system power down process and the power-off reset flow chart of power down protection for the present embodiment.Specifically, after operating system initialization etc. to be interrupted and wait that hardware power-down state notifies, if learning power-down state by state notifying circuit 333 afterwards, triggering system is interrupted and does power-down state judgement of stability in interrupt processing function, after power-down state is stablized in acquisition, directly notice system layer does respective handling, here system layer software can drive or kernel level process for kernel level, data file preservation work (namely preserve data file to memorizer 38) is done after response power-down state, preserve calling system after work disposal completes and hang up (suspend) order, system is made to enter state to be shut down；Afterwards, if discharged the reseting controling signal being previously received from power-off reset control circuit 393 at farad capacitor 35, then the operating system of system master circuit 37 resets again；Whereas if farad capacitor has discharged, then whole system power down.This way it is possible to realize the storage file of whole embedded system is served protective effect and system can be made again to reset under pseudo-power-down state.
Finally it is worth mentioning that, when the state notifying circuit 333 shown in Fig. 3 includes single-chip microcomputer, power-off reset control circuit 393 and state notifying circuit 333 can share a single-chip microcomputer, correspondingly, this single-chip microcomputer utilizes two I/O mouths receive the monitor value Vdet of status monitoring circuit 331 output and the sampled voltage Vs of power-off signal sample circuit 391 output respectively and utilize two other I/O mouth to the external interrupt port of the external interrupt port of respectively connection system governor circuit 37 and reset terminal such as arm processor and reset terminal.It addition, in other embodiments of the invention, the single-chip microcomputer in power-off reset control circuit 393 can also replace to other microcontrollers such as arm processor.
The above, it it is only presently preferred embodiments of the present invention, not the present invention is done any pro forma restriction, although the present invention is disclosed above with preferred embodiment, but it is not limited to the present invention, any those skilled in the art, without departing within the scope of technical solution of the present invention, when the technology contents of available the disclosure above makes a little change or is modified to the Equivalent embodiments of equivalent variations, in every case it is without departing from technical solution of the present invention content, according to any simple modification that above example is made by the technical spirit of the present invention, equivalent variations and modification, all still fall within the scope of technical solution of the present invention.
Claims (10)
- null1. the circuit structure being applied to embedded system，Including: power voltage input terminal、Power-down protection circuit、Storage capacitor、System master circuit and memorizer，Described power-down protection circuit electrically connects the power end of described power voltage input terminal and described system master circuit and external interrupt port and for producing system break to carry out whether power down process is in true power-down state to the supply voltage judging described power voltage input terminal and completes file after the supply voltage of described power voltage input terminal is in true power-down state and preserve to described memorizer and make system entrance state to be shut down through being triggered described system master circuit by described external interrupt port after the supply voltage power down monitoring described power voltage input terminal，Described storage capacitor electrically connects described power-down protection circuit and for being powered to the described power end of described system master circuit by described power-down protection circuit after the supply voltage power down of described power voltage input terminal；It is characterized in that, described in be applied to the circuit structure of embedded system and also include:Power-off signal sample circuit and power-off reset control circuit；Wherein, described power-off signal sample circuit electrically connects described power voltage input terminal and has sampled voltage outfan, described power-off reset control circuit electrically connects the reset terminal of described sampled voltage outfan and described system master circuit and for judging whether the supply voltage of described power voltage input terminal is in true power-down state according to the sampled voltage of described sampled voltage outfan output, whether the supply voltage monitoring described power voltage input terminal after the supply voltage of described power voltage input terminal is in true power-down state recovers and produces the reseting controling signal reset terminal to described system master circuit after the supply voltage monitoring described power voltage input terminal recovers to be in the described system master circuit of state to be shut down with reset system.
- 2. it is applied to the circuit structure of embedded system as claimed in claim 1, it is characterized in that, described power-off signal sample circuit includes the first resistance, the second resistance and electric capacity, described first resistance and described second resistance are serially connected between described power voltage input terminal and earthing potential, and described electric capacity and described first resistance concatenated and the second resistor coupled in parallel are between described power voltage input terminal and described earthing potential.
- 3. it is applied to the circuit structure of embedded system as claimed in claim 1, it is characterized in that, described power-off reset control circuit includes microcontroller, and one the oneth I/O mouth of described microcontroller and one the 2nd I/O mouth are electrically connected described sampled voltage outfan and the described reset terminal of described system master circuit.
- 4. it is applied to the circuit structure of embedded system as claimed in claim 3, it is characterised in that described power-down protection circuit includes:Status monitoring circuit, electrically connects described power voltage input terminal and for exporting the monitor value of the supply voltage whether power down representing described power voltage input terminal；State notifying circuit, electrically connect the described external interrupt port of described status monitoring circuit and described system master circuit, for judging the supply voltage whether power down of described power voltage input terminal according to described monitor value and producing power-down state after the supply voltage power down of described power voltage input terminal and inform the described external interrupt port of described system master circuit to trigger described system master circuit generation system break；AndPower down holding circuit, be connected electrically between the described power end of described power voltage input terminal and described system master circuit and electrically connect described storage capacitor, for when the non-power down of supply voltage of described power voltage input terminal to the charging of described storage capacitor and the supply voltage of described power voltage input terminal is transferred to the described power end of described system master circuit and be used at described power voltage input terminal supply voltage power down time utilize described storage capacitor to power to the described power end of described system master circuit.
- 5. it is applied to the circuit structure of embedded system as claimed in claim 4, it is characterized in that, described state notifying circuit and described power-off reset control circuit share described microcontroller, and one the 3rd I/O mouth of described microcontroller is used for receiving described monitor value, and one the 4th I/O mouth of described microcontroller electrically connects the described external interrupt port of described system master circuit.
- 6. it is applied to the circuit structure of embedded system as claimed in claim 5, it is characterised in that described microcontroller is single-chip microcomputer or arm processor.
- 7. it is applied to the circuit structure of embedded system as claimed in claim 4, it is characterised in that described state notifying circuit is comparison circuit.
- 8. it is applied to the circuit structure of embedded system as claimed in claim 4, it is characterised in that described power down holding circuit includes: the first diode, resistance and the second diode；The positive electrical of described first diode connects described status monitoring circuit, and the negative electricity of described first diode connects the described power end of described system master circuit；Described resistance is connected electrically between negative pole and the described storage capacitor of described first diode, the positive electrical of described second diode connects the negative pole of negative electricity described first diode of connection of described storage capacitor and described second diode, thus described resistance and described second diodes in parallel are between the negative pole and described storage capacitor of described first diode.
- 9. it is applied to the circuit structure of embedded system as claimed in claim 1, it is characterised in that described storage capacitor is farad capacitor.
- 10. it is applied to the circuit structure of embedded system as claimed in claim 1, it is characterized in that, the described circuit structure being applied to embedded system also includes anti-circnit NOT, described anti-circnit NOT has voltage input end and voltage output end, the described voltage input end of described anti-circnit NOT is as described power voltage input terminal, described power-down protection circuit electrically connects the described voltage output end of described anti-circnit NOT to realize electrically connecting described power voltage input terminal, described power-off signal sample circuit electrically connects the described voltage output end of described anti-circnit NOT to realize electrically connecting described power voltage input terminal.
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| CN107196405A (en) * | 2017-06-15 | 2017-09-22 | 上海诺仪表有限公司 | A kind of power switching apparatus and method and instrument |
| CN112002359A (en) * | 2020-08-20 | 2020-11-27 | 北京浪潮数据技术有限公司 | Control device and control method for access of solid state disk after power failure |
| CN112562764A (en) * | 2020-12-15 | 2021-03-26 | 上海维宏电子科技股份有限公司 | Circuit and method for power-down protection of embedded system |
| CN112748789A (en) * | 2019-10-29 | 2021-05-04 | 中车株洲电力机车研究所有限公司 | Power failure event processing method and device and storage medium |
| CN113054964A (en) * | 2021-03-10 | 2021-06-29 | 浙江禾川科技股份有限公司 | Reset system and embedded system |
| CN114353159A (en) * | 2021-12-10 | 2022-04-15 | 北新集团建材股份有限公司 | Temperature regulating system, floor energy storage structure and energy-saving building |
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