CN112748789A - Power failure event processing method and device and storage medium - Google Patents
Power failure event processing method and device and storage medium Download PDFInfo
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- CN112748789A CN112748789A CN201911040018.3A CN201911040018A CN112748789A CN 112748789 A CN112748789 A CN 112748789A CN 201911040018 A CN201911040018 A CN 201911040018A CN 112748789 A CN112748789 A CN 112748789A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
Abstract
The power failure event processing method, device and storage medium provided by the present disclosure include: when the electronic equipment generates a power failure event, receiving a trigger signal; determining the power failure event as a false power failure event according to the trigger signal; and canceling the power failure protection state of the electronic equipment, which is entered by the power failure event, and recovering the execution of normal business logic. Through the arrangement, the problems that the electronic equipment cannot exit in the power failure protection state for a long time and cannot recover normal service logic execution due to a false power failure event are effectively solved, and economic loss caused by normal service interruption is effectively reduced.
Description
Technical Field
The present disclosure relates to the field of electronic devices, and in particular, to a method and an apparatus for processing a power-down event, and a storage medium.
Background
The importance of the power supply to the electronic equipment is just as important as the heart to human beings, and the electronic equipment cannot work normally without the continuous power supply of the power supply. When events such as automatic power-off, shutdown and power failure occur in the electronic device, the events are collectively referred to as power-down events. When a power-down event occurs, all application systems of the electronic device cannot continue to operate, and data being executed in a processor of the electronic device is also subject to loss. At present, a power-down protection function is realized in the industry by combining software and hardware, and when a power-down event occurs, the time-delay power-down circuit supplies power to the electronic equipment (generally for several seconds) so as to ensure that the processor part has time to execute the power-down protection action after the electronic equipment loses external power supply. When the external power supply is abnormal, the electronic equipment enters a power-down protection state, the normal service control logic of the equipment is possibly limited to a certain extent because the equipment is in the power-down protection state in the period, even the equipment is required to perform safe guidance and no service control logic is executed any more under the scene with high safety requirement, and the power-down protection state is kept until the equipment is completely powered off.
Disclosure of Invention
In order to solve the above problems, the present disclosure provides a method, an apparatus, and a storage medium for processing a power down event. The method and the device have the advantages that the power failure event is identified, and after the power failure event is determined to be the false power failure event, the power failure protection state of the electronic equipment, which is caused by the power failure event, is cancelled, and the execution of normal service logic is recovered. The problem that the electronic equipment cannot exit from a power failure protection state for a long time and cannot recover normal service control logic due to a false power failure event is solved, normal service interruption is effectively avoided, and economic loss of enterprises is reduced.
In order to achieve the above object, in a first aspect of the embodiments of the present disclosure, a method for processing a power failure event is provided, including:
when the electronic equipment generates a power failure event, receiving a trigger signal;
determining the power failure event as a false power failure event according to the trigger signal;
and canceling the power failure protection state of the electronic equipment, which is entered by the power failure event, and recovering the execution of normal business logic.
Optionally, when the trigger signal is a first power down interrupt signal, determining that the power down event is a false power down event according to the trigger signal includes:
after receiving the first power failure interrupt signal, starting timing;
and if the timing length is equal to or greater than the preset time length, determining that the power failure event is a false power failure event.
Optionally, when the trigger signal is a delayed power supply signal, determining that the power down event is a false power down event according to the trigger signal includes:
counting the duration of the delayed power supply signal;
and if the duration is equal to or greater than the preset duration, determining that the power failure event is a false power failure event.
Optionally, when the trigger signal is a second power down interrupt signal, determining that the power down event is a false power down event according to the trigger signal includes:
counting the duration of the change level of the second power down interrupt signal;
and if the duration is less than the preset duration, determining that the power failure event is a false power failure event.
Optionally, the preset time length is greater than or equal to a theoretical power supply time length of a delayed power down circuit in the electronic device.
In a second aspect of the embodiments of the present disclosure, a power failure event processing apparatus is provided, including: the power failure interrupt circuit, the delay power failure circuit and the controller are connected;
the power failure interrupt circuit is configured to send an interrupt signal to the controller when a power failure event occurs to the electronic equipment;
the delayed power-down circuit is configured to send a delayed power supply signal to the controller when the electronic equipment generates a power-down event;
the controller is configured to determine that the power failure event is a false power failure event according to the interrupt signal or the delayed power supply signal, cancel a power failure protection state of the electronic device due to the power failure event, and resume execution of normal service logic.
Optionally, the interrupt signal further includes a first power down interrupt signal, and the controller is further configured to:
when the controller receives the first power-down interrupt signal sent by the power-down interrupt circuit, timing is started after the first power-down interrupt signal is received;
and if the timing length is equal to or greater than the preset time length, determining that the power failure event is a false power failure event.
Optionally, the controller is further configured to:
when the controller receives the delayed power supply signal sent by the delayed power failure circuit, counting the duration of the delayed power supply signal;
and if the duration is equal to or greater than the preset duration, determining that the power failure event is a false power failure event.
Optionally, the interrupt signal comprises a second power down interrupt signal, and the controller is further configured to:
when the controller receives the second power-down interrupt signal sent by the power-down interrupt circuit, counting the duration of the change level of the second power-down interrupt signal;
and if the duration is less than the preset duration, determining that the power failure event is a false power failure event.
In a third aspect of the embodiments of the present disclosure, a storage medium is provided, on which a computer program is stored, and when the computer program is executed by one or more processors, the method for processing the power failure event is implemented.
By adopting the technical scheme, the following technical effects can be at least achieved:
the method comprises the steps of receiving a trigger signal when a power failure event occurs, enabling the electronic equipment to enter a power failure protection state and stop execution of normal service logic, determining that the power failure event is a false power failure event according to the duration of the trigger signal, canceling the power failure protection state of the electronic equipment due to the power failure event, and recovering execution of the normal service logic. The problem that the electronic equipment cannot exit from the power failure protection state for a long time and cannot recover normal service control logic due to a false power failure event is solved, the interruption of normal service is effectively avoided, and the economic loss of enterprises is reduced.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings.
Fig. 1 is a schematic flow chart of a power failure event processing method provided by the present disclosure.
Fig. 2 is a schematic structural diagram of a power down event processing apparatus provided in the present disclosure.
Fig. 3 is a schematic flow chart of a first scheme implemented in step S120 in fig. 1.
Fig. 4 is a schematic flow chart of a second scheme implemented in step S120 in fig. 1.
Fig. 5 is a schematic flow chart of a third scheme implemented in step S120 in fig. 1.
In the drawings, like parts are designated with like reference numerals, and the drawings are not drawn to scale.
Detailed Description
Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples, so that how to apply technical means to solve technical problems and achieve the corresponding technical effects can be fully understood and implemented. Various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the disclosure. The embodiments and various features in the embodiments of the present application can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the related art, the power failure of the electronic device is only caused by unstable external power supply or short-time power supply drop but does not result in actual power failure of the device, and such a power failure event is called a false power failure event.
The inventor of the present disclosure finds that when a false power failure event occurs to an electronic device, the electronic device will be in a power failure protection state for a long time and cannot spontaneously exit from the power failure protection state, and a normal service control logic cannot be recovered.
Example one
Fig. 2 is a schematic structural diagram of a power down event processing apparatus according to an exemplary embodiment of the present disclosure. As shown in fig. 2, the power down event processing apparatus 100 may include a delayed power down circuit 10, a power down interrupt circuit 20, and a controller 30. The external power supply 200 is electrically connected with the power failure processing device 100 and supplies power to the power failure processing device 100 and the service logic processor 300; the delayed power-down circuit 10 and the power-down interrupt circuit 20 are respectively electrically connected with the controller 30, the delayed power-down circuit 10 is used for sending a delayed power supply signal to the controller 30, and the power-down interrupt circuit 20 is used for sending an interrupt signal to the controller 30; the controller 30 controls the input and output of the service logic processor 300.
The disclosure provides a method for processing a power failure event, which aims to solve the problems that when a false power failure event occurs, an electronic device is in a power failure protection state for a long time and cannot spontaneously exit the state, and a normal service control logic cannot be recovered. Fig. 1 is a schematic flow chart of a power down event processing method proposed by the present disclosure, and as shown in fig. 1, the power down event processing method mainly includes the following steps S110 to S130.
In step S110, when a power down event occurs to the electronic device, a trigger signal is received.
The power failure event refers to an event that the electronic equipment cannot normally work due to power failure, power loss or the fact that the quality of power cannot meet the requirement.
The trigger signal may be, but is not limited to, a trigger electrical signal or a trigger optical signal, and is not specifically limited herein, and may be set according to actual requirements.
In this embodiment, the trigger signal is a trigger electrical signal.
And when the trigger signal is received, triggering to execute a power-down protection action and entering a power-down protection state, wherein the execution of the normal business logic is also stopped.
For example, when a power-off event occurs, a trigger signal is received, and at this time, the delayed power-off circuit 10 continues to supply power to the controller 30, and causes the controller 30 to enter a power-off protection state to store data generated during the current program execution process, and simultaneously suspends the external control behavior of the controller 30.
Therefore, the consequences of loss of the history data related to the electronic equipment, uncertain external control behaviors and the like caused by the power failure event can be avoided, the safety is effectively improved, and the economic loss caused by the power failure event is reduced.
In step S120, the power down event is determined as a false power down event according to the trigger signal.
When the trigger electrical signal comprises a trigger electrical signal, the trigger electrical signal may comprise a delayed power supply signal, a second power down interrupt signal or a first power down interrupt signal.
The second power-down interrupt signal is a continuous electrical signal with a rising edge or a falling edge, and the first power-down interrupt signal is an electrical signal at a certain time point.
As can be appreciated, when the electronic device has a power down event, the delayed power down circuit 20 transmits the delayed power supply signal, and the controller 30 receives the delayed power supply signal; the power down interrupt circuit 10 transmits the second power down interrupt signal, and the controller 30 receives the second power down interrupt signal; the power down interrupt circuit 10 transmits the first power down interrupt signal, which is received by the controller 30.
It should be noted that the preset time length is longer than or equal to the theoretical power supply time that the electronic equipment can be supported to continuously supply power until the electronic equipment is completely powered off after the delayed power down circuit is fully charged once, and the theoretical power supply time length is recorded as Tdly_pwr_spy. When the trigger electrical signal is a first interrupt signal, the specific process of step S120 is as shown in fig. 3.
In step S1201, after receiving the first power down interrupt signal, timing is started.
When the first power down interrupt signal is received, controller 30 internally starts timing.
In step S1202, if the timing length is equal to or greater than a preset time length, it is determined that the power down event is a false power down event.
Comparing the timing duration with a preset duration, wherein the preset duration selected at this time can be greater than or equal to the theoretical power supply duration T of the delayed power-down circuit 20dly_pwr_spy(ii) a In order to ensure the detection accuracy, the preset time is set to be T which is 1.5-2 times longerdly_pwr_spyAnd in the time length range, if the timing time length is equal to or greater than the preset time length, determining that the power failure event is a false power failure event, and if the timing time length is less than the preset time length, determining that the power failure event is a true power failure event.
For example, when a power-down event occurs, the first power-down interrupt signal is a discontinuous point-like electrical signal at the time of the power-down event, the power-down interrupt circuit 10 transmits the first power-down interrupt signal, and the controller 30 starts timing when receiving the first power-down interrupt signal; assuming that the delayed power down circuit 20 is theoretically capable of supporting the electronic device for 5 seconds of power supply, the value of the preset time period may be in the range of [5, + ∞), but to ensure the accuracy of the detection, we set the preset time period to an arbitrary value within the range of the value of [7.5, 10], assuming that the preset time period is set to 7.5 seconds here, when the timing time period of the first power down interrupt signal is equal to or greater than 7.5 seconds, then the power down event is determined to be a false power down event; and when the duration of the delayed power supply signal is less than 7.5 seconds, determining that the power failure event is a true power failure event.
When the trigger electrical signal is a delayed power supply signal, the specific process of step S120 is as shown in fig. 4.
In step S1203, the duration of the delayed power supply signal is counted.
When the delayed power supply signal is received, the controller 30 starts to count the time duration of the delayed power supply signal after the power-down event occurs.
In step S1204, if the duration is equal to or greater than a preset duration, it is determined that the power down event is a false power down event.
Comparing the duration with a preset duration, wherein the preset duration selected at this time may be greater than or equal to the theoretical power supply duration T of the delayed power down circuit 20dly_pwr_spy(ii) a In order to ensure the detection accuracy, the preset time is set to be T which is 1.5-2 times longerdly_pwr_spyWithin the time length range; and if the duration of the delayed power supply signal is equal to or greater than the preset duration, determining that the power failure event is a false power failure event, and if the duration of the delayed power supply signal is less than the preset duration, determining that the power failure event is a true power failure event.
For example, when a power down event occurs, the delayed power down circuit 20 transmits a delayed power supply signal, and at this time, a continuous delayed power supply signal is continuously output until the delayed power down circuit 20 is completely powered down; the controller 30 starts timing when receiving the power supply signal; assuming that the delay circuit theory can support 5 seconds of power supply of the electronic device, the value of the preset time length can be in a range of [5, + ∞), but in order to guarantee the detection accuracy, the value of the preset time length is set to be any value in a range of [7.5, 10], assuming that the preset time length is selected to be 7.5 seconds, and when the duration of the delay power supply signal is equal to or greater than 7.5 seconds, the power failure event is determined to be a false power failure event; and when the duration of the delayed power supply signal is less than 7.5 seconds, determining that the power failure event is a true power failure event.
When the trigger electrical signal is a second power down interrupt signal, the specific process of step S120 is as shown in fig. 5.
In step S1205, the duration of the level change of the second power down interrupt signal is counted.
And starting timing by detecting the rising edge or the falling edge of the second power-down interrupt signal until the rising edge becomes the falling edge or the falling edge becomes the rising delay to finish timing, so as to obtain the duration of a high level or a low level.
In step S1206, if the duration is less than a preset duration, it is determined that the power down event is a false power down event.
Comparing the duration of the high level or the low level with a preset duration, where the preset duration is equal to the theoretical power supply duration T of the delayed power-down circuit 20dly_pwr_spy. If the duration is less than the preset duration, determining that the power failure event is a false power failure event, and if the duration is equal to or greater than the preset duration, determining that the power failure event is a true power failure event.
For example, the second power down interrupt signal is a continuous high level electrical signal during normal power supply, when a power down event occurs, the high level electrical signal generates a falling edge and is attenuated into a low level electrical signal, and when the external power supply does not recover the normal power supply, a section of low level electrical signal is continuously output; and counting the duration of the low-level signal by taking the falling edge as a mark for starting timing, setting the preset duration to be 5 seconds if the delay circuit theory can support 5 seconds of power supply of the electronic equipment, determining that the current power failure event is a false power failure event if the duration is 4 seconds, and determining that the current power failure event is a true power failure event if the duration is 6 seconds.
It is understood that the timing is performed in the controller 30, and when the power down event is a true power down event, the electronic device (including the controller 30) may be completely powered down before the preset time period is not reached, and the timing may also stop, and is naturally less than the preset time period.
Therefore, the false power failure can be identified in a signal identification and processing mode under the condition of not changing hardware, and the cost of the electronic equipment is effectively reduced.
In step S130, the power down protection state of the electronic device due to the power down event is cancelled and the execution of normal service logic is resumed.
When the power failure event is determined to be a false power failure event, the external power supply recovers to be normally powered on, the problems of data loss and the like are not caused, the electronic equipment does not need to be in a power failure protection state any more, the external power supply can continue to support the operation of the electronic equipment, the power failure protection state of the electronic equipment, which is caused by the power failure event, needs to be cancelled, the execution of normal business logic is recovered, the electronic equipment continues to operate, manual intervention is not needed, and the subsequent operation of the electronic equipment is delayed.
By applying the power failure event processing method disclosed by the invention, no matter whether the power failure event is false power failure or not, as long as the power failure event occurs, a trigger signal is transmitted, as long as the trigger signal is received, the electronic equipment enters a protection state and stops the execution of service logic, until the false power failure event is determined after the time length of the trigger signal is compared with the preset time length, at the moment, the electronic equipment exits from the power failure protection state and recovers the execution of normal service logic, the data loss and some control uncertain behaviors are avoided after the electronic equipment enters the power failure protection state, the electronic equipment continues to operate after the electronic equipment exits from the power failure protection state, manual intervention is not needed, the normal service interruption caused by the false power failure event is effectively avoided, and the economic loss of enterprises is reduced.
Example two
Referring to fig. 2, the present disclosure provides a power down event processing apparatus 100, which can be applied to the above power down event processing method, where the power down event processing apparatus 100 includes: a power down interrupt circuit 10, a delayed power down circuit 20, and a controller 30.
The power down interrupt circuit 10 is configured to send an interrupt signal to the controller 30 when a power down event occurs to the electronic device.
Since the power down interrupt circuit 10 monitors the power state of the external power source 200, when the external power source 200 has a power down event, the power down interrupt circuit 10 will send an interrupt signal to the controller 30.
Wherein the interrupt signal may be, but is not limited to, a second power down interrupt signal or a first power down interrupt signal.
The delayed power down circuit 20 is configured to send a delayed power signal to the controller 30 when a power down event occurs in the electronic device.
When the external power supply 200 supplies power normally, the delayed power-down circuit 20 is charged, the delayed power-down circuit 20 at least comprises an energy storage capacitor, the fully charged energy storage capacitor is equivalent to a lead, when the external power supply 200 generates a power-down event, the delayed power-down circuit 20 continues to supply power to the electronic equipment, a delayed power-down signal is transmitted at the moment to ensure that the electronic equipment has time to execute a power-down protection action after losing the power of the external power supply 200, but when the power-down event is a false power-down event, the delayed power-down circuit 20 is charged before completely losing power, so the delayed power-down circuit 20 is always in a continuous charging and discharging state under the condition of no manual intervention, and the transmitted delayed power-down signal is also in a continuous non-attenuation state.
Therefore, when a power failure event occurs, the electronic device has time to execute a power failure protection action through the intervention power supply of the delayed power failure circuit 20, enters a power failure protection state and suspends the execution of service logic, so that the problems of data loss or uncertain external control behavior and the like are avoided, and the loss is effectively recovered.
The controller 30 is configured to determine that the power down event is a false power down event according to the interrupt signal or the delayed power supply signal, cancel a power down protection state of the electronic device due to the power down event, and resume execution of normal service logic.
When the controller 30 receives the interrupt signal or the delayed power supply signal, it enters a power-down protection state and suspends normal service logic execution of the service logic execution processor 300, and when it is determined that the power-down event is a false power-down event, the controller 30 exits the power-down protection state and resumes execution of normal service logic in the service logic processor 300.
For a specific description of determining whether the power down event is a false power down event, reference may be made to the first embodiment, and a repeated description of the same technical content is omitted here.
EXAMPLE III
The present embodiment provides a storage medium on which a computer program is stored, where the computer program is executed by one or more processors to implement the power down event processing method as described in the first embodiment.
The method implemented when the computer program of the power failure event processing method executed on the processor is executed may refer to the specific embodiment of the power failure event processing method disclosed in the present disclosure, and details are not described here again.
The processor may be an integrated circuit chip having information processing capabilities. The Processor may be a general-purpose Processor including a Central Processing Unit (CPU), a Network Processor (NP), and the like.
It should be understood that the disclosed methods and apparatus may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.
Claims (10)
1. A power down event processing method is characterized by comprising the following steps:
when the electronic equipment generates a power failure event, receiving a trigger signal;
determining the power failure event as a false power failure event according to the trigger signal;
and canceling the power failure protection state of the electronic equipment, which is entered by the power failure event, and recovering the execution of normal business logic.
2. The power down event processing method according to claim 1, wherein when the trigger signal includes a first power down interrupt signal, determining that the power down event is a false power down event according to the trigger signal includes:
after receiving the first power failure interrupt signal, starting timing;
and if the timing length is equal to or greater than the preset time length, determining that the power failure event is a false power failure event.
3. The method for processing the power down event according to claim 1, wherein when the trigger signal includes a delayed power supply signal, determining the power down event as a false power down event according to the trigger signal includes:
counting the duration of the delayed power supply signal;
and if the duration is equal to or greater than the preset duration, determining that the power failure event is a false power failure event.
4. The power down event processing method according to claim 1, wherein when the trigger signal includes a second power down interrupt signal, determining that the power down event is a false power down event according to the trigger signal includes:
counting the duration of the change level of the second power down interrupt signal;
and if the duration is less than the preset duration, determining that the power failure event is a false power failure event.
5. The power down event processing method according to any one of claims 2 to 4, wherein the preset time period is greater than or equal to a theoretical power supply time period of a delayed power down circuit in the electronic device.
6. A power down event processing apparatus, comprising: the power failure interrupt circuit, the delay power failure circuit and the controller are connected;
the power failure interrupt circuit is configured to send an interrupt signal to the controller when a power failure event occurs to the electronic equipment;
the delayed power-down circuit is configured to send a delayed power supply signal to the controller when the electronic equipment generates a power-down event;
the controller is configured to determine that the power failure event is a false power failure event according to the interrupt signal or the delayed power supply signal, cancel a power failure protection state of the electronic device due to the power failure event, and resume execution of normal service logic.
7. The power down event processing apparatus of claim 6, wherein the interrupt signal further comprises a first power down interrupt signal, the controller further configured to:
when the controller receives the first power-down interrupt signal sent by the power-down interrupt circuit, timing is started after the first power-down interrupt signal is received;
and if the timing length is equal to or greater than the preset time length, determining that the power failure event is a false power failure event.
8. The power down event processing device of claim 6, wherein the controller is further configured to:
when the controller receives the delayed power supply signal sent by the delayed power failure circuit, counting the duration of the delayed power supply signal;
and if the duration is equal to or greater than the preset duration, determining that the power failure event is a false power failure event.
9. The power down event processing device of claim 6, wherein the interrupt signal comprises a second power down interrupt signal, the controller further configured to:
when the controller receives the second power-down interrupt signal sent by the power-down interrupt circuit, counting the duration of the change level of the second power-down interrupt signal;
and if the duration is less than the preset duration, determining that the power failure event is a false power failure event.
10. A storage medium having stored thereon a computer program, wherein the computer program, when executed by one or more processors, implements a power down event processing method as claimed in any one of claims 1 to 5.
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| US20100169065A1 (en) * | 2008-12-31 | 2010-07-01 | Maulik Joshi | Simulating loss of logic power state due to processor power conservation state |
| CN102156679A (en) * | 2011-04-18 | 2011-08-17 | 苏州捷泰科信息技术有限公司 | PCIE interface-based solid state disk power-down protection method and device |
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Application publication date: 20210504 |