JPS63103311A - Processing method for microcomputer system at time of service interruption - Google Patents

Processing method for microcomputer system at time of service interruption

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Publication number
JPS63103311A
JPS63103311A JP61249038A JP24903886A JPS63103311A JP S63103311 A JPS63103311 A JP S63103311A JP 61249038 A JP61249038 A JP 61249038A JP 24903886 A JP24903886 A JP 24903886A JP S63103311 A JPS63103311 A JP S63103311A
Authority
JP
Japan
Prior art keywords
voltage
power supply
supply voltage
microcomputer system
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61249038A
Other languages
Japanese (ja)
Inventor
Seiichirou Uga
宇賀 勢一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP61249038A priority Critical patent/JPS63103311A/en
Publication of JPS63103311A publication Critical patent/JPS63103311A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the reliability of a microcomputer system by restarting automatically the system operation as long as the power supply voltage drops less than a prescribed level owing to an instantaneous service interruption of the power supply, etc., is reset to its original level within a prescribed period of time. CONSTITUTION:The DC power supply voltage VC supplied to a microcomputer system is impressed on a voltage detecting circuit 2. The circuit 2 transmits a signal that is changed to logical L from a logical H to an output terminal 3 when the voltage VC drops less than the voltage V1 and then to an output terminal 4 when the VC drops less than the voltage V2 respectively (V1>V2). The output of the terminal 3 is supplied to a data bus of a CPU and a terminal NMI via a buffer circuit 5 and a flip-flop circuit 6 respectively. While the output of the terminal 4 is supplied to a reset terminal of the CPU via inverter circuits 7 and 8, etc. Thus the operation can be restarted automatically without stopping working of the microcomputer system as long as the dropped voltage VC is reset to its original level within a prescribed period of time.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はマイクロコンピュータシステムのAC電源が瞬
時停電した箭または雑音等で電源電圧が瞬時所定値以下
になった場合の処理方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a processing method when the AC power supply of a microcomputer system momentarily drops below a predetermined value due to a momentary power outage or noise.

(従来の技術) n器やH22の制御をマイクロコンピュータシステムに
より行なうことがあるが、このようなマイクロコンピュ
ータシステムは、停電または雑音等で動作中に電源の供
給が遮断されたり、電圧の低下によりプログラムやデー
タが破壊されてしまって、次に電源が供給されて動作の
開始をしても、マイクロコンピュータシステムが正常な
動作を出来ない場合が生じる。
(Prior art) N-units and H22s are sometimes controlled by a microcomputer system, but such microcomputer systems cannot be used when the power supply is cut off during operation due to a power outage or noise, or due to a drop in voltage. If programs and data are destroyed, the microcomputer system may not be able to operate normally even if power is supplied and the microcomputer system starts operating again.

そこで、多くの場合、電源の供給が遮断した時、自動的
にプログラムを正常終了させてバックアップバッテリに
よりデータを保持する1能を有するマイクロコンピュー
タシステムがある。
Therefore, in many cases, there are microcomputer systems that have the ability to automatically terminate a program normally and retain data using a backup battery when the power supply is cut off.

通常、このようなバックアップバッテリを為するマイク
ロコンピュータシステムは、電源の電圧が低下した場合
、停電が起こるであろうと見なし、前記の停電時の正常
終了のための処理(停電処理)を実行した後、マイクロ
コンピュータシステムの動作を停止するか、または強制
的にリセットして終了するようにしている。
Normally, a microcomputer system that serves as such a backup battery assumes that a power outage will occur when the power supply voltage drops, and after executing the process for normal termination in the event of a power outage (power outage processing). , the microcomputer system stops operating or is forced to reset and terminate.

(発明が解決しようとする問題点) このような従来のマイクロコンピュータシステムの停電
時の処理方法は、AC電源が瞬時停電したことにより検
出回路が停電として停電処理を開始しているにもかかわ
らず、直後にAC電源の電圧が正常値に回復しても、マ
イクロコンビ1−タシステムは動作を停止してしまう問
題点があった。
(Problem to be Solved by the Invention) The conventional microcomputer system's processing method in the event of a power outage is that even though the detection circuit has started processing the power outage as a power outage due to a momentary power outage in the AC power supply, There was a problem in that even if the voltage of the AC power supply recovered to a normal value immediately after that, the microcombinator system would stop operating.

更に、静電気または外来雑音により、瞬時、電源電圧が
低下してこれが検出回路により停電として検知し、停電
処理をし動作を停止してしまうこともあり、雑音に対す
るマージンがあまりとれず、高信頼性が要求されるシス
テムにこのような従来のマイクロコンピュータシステム
の停電時の処理方法は使用出来ないという問題点があっ
た。
Furthermore, static electricity or external noise can cause an instantaneous drop in the power supply voltage, which is detected by the detection circuit as a power outage, and the power outage is handled and the operation is stopped. This leaves little margin for noise, resulting in high reliability. There is a problem in that such conventional microcomputer system processing methods during power outages cannot be used in systems that require the following.

(問題点を解決する為の手段) 本発明は上記問題点を解決するために、マイクロコンピ
ュータシステムの動作中に停電が起きた時に、電源電圧
が所定値以下に低下したことを検知し、電源電圧が遮断
する前に動作を停止させたり、リセット等の割り込みを
して停電処理を行なうマイクロコンピュータシステムに
おいて、マイクロコンピュータシステムへの電源電圧が
供給されて、第1の電圧とこの第1の電圧より低い第2
の電圧とを検出した時にそれぞれ送出信号の状態が変化
する第1および第2の出力端子を有する電圧検出回路と
、第1の出力端子のの信号の状態をCP(Jに供給する
バッフ7回路と、前記電源電圧が第1の電圧よりも高い
状態から低い状態に推移したことを前記CPUに送出す
るフリップフロップ回路と、第2の出力端子の出力信号
が一端に供給される第1の抵抗器と、この第1の抵抗器
の他端が接続される他端が接地された第2の抵抗器およ
び他端に前記電源電圧が供給されたコンデンサと、第1
の抵抗器のIl!!端よりの出力信号により前記CPU
へのリセット信号を得る回路とを備え、前記?11i源
電圧が第1の電圧以下になった時に前記CPUへ割りこ
みをして停電処理を行ない、所定時間内に前記電源電圧
が回復した際には、停電処理の復帰処理を行ない、前記
電源電圧が第2の電圧以下になった時に前記CPUをリ
セットするようにしたマイクロコンピュータシステムの
停電時の処理方法を提供する。
(Means for Solving the Problems) In order to solve the above problems, the present invention detects that the power supply voltage has dropped below a predetermined value when a power outage occurs during the operation of a microcomputer system, and In a microcomputer system that handles a power outage by stopping operation before the voltage is cut off or by issuing an interrupt such as a reset, the power supply voltage is supplied to the microcomputer system, and the first voltage and this first voltage are lower second
a voltage detection circuit having first and second output terminals, each of which changes the state of a sending signal when detecting a voltage of a flip-flop circuit that sends information to the CPU that the power supply voltage has changed from a state higher than a first voltage to a state lower than the first voltage; and a first resistor to which an output signal from a second output terminal is supplied. a second resistor whose other end to which the other end of the first resistor is connected is grounded, and a capacitor whose other end is supplied with the power supply voltage;
of the resistor Il! ! The output signal from the end causes the CPU to
and a circuit to obtain a reset signal to the above? 11i When the power supply voltage becomes lower than the first voltage, the CPU is interrupted to perform power outage processing, and when the power supply voltage is restored within a predetermined time, the power outage processing recovery processing is performed and the power supply A method for processing a power outage in a microcomputer system is provided, in which the CPU is reset when the voltage becomes lower than a second voltage.

(実施VA> 第1図は本発明のマイクロコンピュータシステムの停電
時の処理方法を説明するためのブロック系統図、第2図
は同フローチャート、第3図は同波形のタイムチャート
をそれぞれ示す。
(Implementation VA> FIG. 1 is a block system diagram for explaining the processing method at the time of power outage in the microcomputer system of the present invention, FIG. 2 is a flowchart of the same, and FIG. 3 is a time chart of the same waveforms.

第1図において、1はマイクロコンビコータシステムに
供給される直流の電源電圧Vcが供給される入力端子で
、この入力端子1に供給された電圧は、電圧検出回路2
に供給される。
In FIG. 1, reference numeral 1 denotes an input terminal to which a DC power supply voltage Vc is supplied to the micro combi coater system.
supplied to

この電圧検出回路2は、例えば定電圧ダイオード等を利
用した周知の回路により電源電圧Vcが電圧V1以下の
時、出力端子3に、電源電圧Vcが電圧■2以下の時、
出力端子4にそれぞれ論理Hの信@(以下、単に1」と
いう)から論理りの信号(以下、単にLという)に状態
が変化した信号を送出する回路であり、ここでは電圧1
の方が電圧■2より大なるものとする。
This voltage detection circuit 2 uses a well-known circuit using, for example, a constant voltage diode, to output a signal to an output terminal 3 when the power supply voltage Vc is below the voltage V1, and when the power supply voltage Vc is below the voltage 2.
This is a circuit that sends a signal whose state changes from a logic H signal @ (hereinafter simply referred to as 1) to a logic high signal (hereinafter simply referred to as L) to the output terminal 4, and here the voltage is 1.
It is assumed that the voltage is larger than the voltage ■2.

出力端子3の出力信号はバッフ7回路5およびフリップ
フロップ回路6にそれぞれ供給され、このバッファ回路
5およびフリップフロップ回路6のそれぞれの出力信号
は図示しないCPUのデータバス(Data Bus)
およびNMI端子に供給される。
The output signal of the output terminal 3 is supplied to the buffer circuit 5 and the flip-flop circuit 6, respectively, and the output signals of the buffer circuit 5 and the flip-flop circuit 6 are connected to a CPU data bus (not shown).
and the NMI terminal.

下方、出力端子4の出力信号は、抵抗器R1の一端に供
給されており、この抵抗器R1の他端は、他端に電源電
圧VCが供給されている抵抗器R2の一端J3よび他端
が接地されているコンデンサCの一端とにそれぞれ接続
されている。
At the bottom, the output signal of the output terminal 4 is supplied to one end of a resistor R1, and the other end of this resistor R1 is connected to one end J3 and the other end of a resistor R2, the other end of which is supplied with the power supply voltage VC. are connected to one end of a capacitor C which is grounded.

更に、抵抗器R1の他端の出力信号はインバータ回路7
.8をそれぞれシリアルに介して図示しないCPUのリ
セット端子にそれぞれ供給されている。
Furthermore, the output signal at the other end of the resistor R1 is sent to the inverter circuit 7.
.. 8 are each serially supplied to a reset terminal of a CPU (not shown).

次に、本発明のマイクロコンピュータシステムの停電時
の処理方法の動作について第1図乃至第3図と共に説明
する。
Next, the operation of the processing method for a microcomputer system during a power outage according to the present invention will be explained with reference to FIGS. 1 to 3.

第3図(A)のPに示すように瞬時(時間T)だけAC
ラインの電圧が零になったとする。ところが、このAC
ラインの電圧は図示しない変圧器、整流回路、定電圧回
路等により所定の直流電源電圧VCに変換されるが、こ
れらの回路は大容量のコンデンサおよび抵抗を有してい
るので、大きな時定数を有するのが一般的である。
AC for an instant (time T) as shown at P in Figure 3 (A).
Suppose that the line voltage becomes zero. However, this AC
The line voltage is converted to a predetermined DC power supply voltage VC by a transformer, rectifier circuit, constant voltage circuit, etc. (not shown), but these circuits have large capacitors and resistors, so they have a large time constant. It is common to have one.

従って、電源電圧Vcは第3図(B)に図示の如くある
時定数で減少し、電圧v1以下になると、電圧検出回路
2の出力端子3の出力信号は第3図(C)に図示の如く
ト1からLに状態が変化し、CPUは今まで動作してい
たプログラムに対して割り込み動作に入る(第2図のス
テップ1)。
Therefore, the power supply voltage Vc decreases with a certain time constant as shown in FIG. 3(B), and when it becomes less than the voltage v1, the output signal of the output terminal 3 of the voltage detection circuit 2 changes as shown in FIG. 3(C). As shown in FIG. 2, the state changes from G1 to L, and the CPU enters an interrupt operation for the program that has been running so far (step 1 in FIG. 2).

次に、フリップフロップ回路6はHからしへのエツジで
反転した出力信号をCPUのNM[端fに供給すること
により、停電処理を行ないく第2図のステップ2>、C
PtJは停電処理を行なった後、図示しないデータバス
(Data Bus)を介して得られたバッファ回路5
よりの信号を電源電圧Vcが電圧v1以上か否かを判定
する もし、電源電圧VCが電圧v1以上であれば(第2図の
ステップ3のYes) 、CPUは停電処理を油に戻す
復帰処理(第2図のステップ4)を行ない、割り込み開
始峙の通常動作に戻る(第2図のステップ5)。この直
m、cpuはフリップフロップ回路6に信号を送出し、
フリップフロップ回路6の出力信号を第3図(D)に図
示の如くLからHに戻す。
Next, the flip-flop circuit 6 performs power outage processing by supplying the output signal inverted at the edge to H to the NM[end f] of the CPU.
PtJ is a buffer circuit 5 obtained via a data bus (not shown) after performing power outage processing.
Determine whether or not the power supply voltage Vc is higher than the voltage v1 based on the signal from the power supply. If the power supply voltage VC is higher than the voltage v1 (Yes in step 3 in Figure 2), the CPU performs a recovery process that returns the power failure process to oil. (Step 4 in FIG. 2) is carried out, and the process returns to the normal operation at the beginning of the interrupt (Step 5 in FIG. 2). Directly, the CPU sends a signal to the flip-flop circuit 6,
The output signal of the flip-flop circuit 6 is returned from L to H as shown in FIG. 3(D).

ここで、ACラインの電圧が時間Tだけ零になっても、
電源電圧VcがV2以下にならないようにするには整流
回路、定電圧回路等の時定数を選定することにより時間
Tは任意に設定可能である。
Here, even if the voltage of the AC line becomes zero for a time T,
In order to prevent the power supply voltage Vc from falling below V2, the time T can be arbitrarily set by selecting the time constants of the rectifier circuit, constant voltage circuit, etc.

次に、ACラインの電圧零の状態が時間1以上で、電源
電圧Vcが第3図(B)のQ系列に図示の如く、電圧v
2以下になった場合(第2図のステップ6)、電圧検出
回路2はこれを検出して、出力端子4の出力信号はHか
らしに状態が変化し、それまでコンデンサCは抵抗器R
2を介して電源電圧Vcに充電されていたが、抵抗器R
1の一端がしになったので、コンデンサCの電圧は抵抗
器R1を介して放電されることになり、インバータ回路
7のスレショルドレベル以下になると、インバータ回路
7の出力信号はHとなるのでインバータ回路8の出力信
号は第3図(E)のようにしレベルとなり、マイクロコ
ンピュータシステムをリセット、即ち動作を終了させて
しまう。
Next, when the voltage of the AC line is zero for a period of time 1 or more, the power supply voltage Vc becomes the voltage v as shown in the Q series of FIG. 3(B).
2 or less (step 6 in Figure 2), the voltage detection circuit 2 detects this and the output signal at the output terminal 4 changes state to H, and until then the capacitor C is connected to the resistor R.
2 to the power supply voltage Vc, but the resistor R
Since one end of 1 becomes low, the voltage of capacitor C will be discharged through resistor R1, and when it becomes below the threshold level of inverter circuit 7, the output signal of inverter circuit 7 will become H, so the voltage of capacitor C will be discharged through resistor R1. The output signal of the circuit 8 reaches the level shown in FIG. 3(E), and the microcomputer system is reset, that is, the operation is terminated.

(発明の効果) 本発明によれば、バックアップバッテリを有するマイク
ロコンピュータシステムに於て、N 8.の瞬時の停電
および静電気、雑音等で電源電圧が零または所定の電圧
以下になった場合でも、電源電圧が所定の時間内に復帰
すれば、マイクロコンピュータシステムを停止すること
なく、動作を自動的に再動作させることが可能であると
共に、雑音に対するマージンも大きくすることが出来る
特長を有する。
(Effects of the Invention) According to the present invention, in a microcomputer system having a backup battery, N8. Even if the power supply voltage drops to zero or below a predetermined voltage due to an instantaneous power outage, static electricity, noise, etc., if the power supply voltage is restored within the predetermined time, the microcomputer system will continue to operate automatically without stopping. It has the advantage of being able to be re-operated at any time and also having a large margin against noise.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のマイクロコンピュータシステムのP;
!電時の処理方法を説明するためのブロック系統図、第
2図は同フローチャート、第3図は同波形のタイムチャ
ートをそれぞれ示す。 1・・・入力端子、2・・・電圧検出回路、3・・・第
1の出力端子、4・・・第2の出力端I、5・・・バッ
ファ回路、6・・・フリップフロップ回路、7.8・・
・インバータ回路、C・・・コンデンサ、R1・・・第
1の抵抗器、R2・・・第2の抵抗器、T・・・時間、
■1・・・第1の電圧、■2・・・第2の電圧、Vc・
・・直流の電源電圧。
FIG. 1 shows P of the microcomputer system of the present invention;
! FIG. 2 is a block system diagram for explaining the method of processing electric power, FIG. 2 is a flowchart of the same, and FIG. 3 is a time chart of the same waveforms. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Voltage detection circuit, 3... First output terminal, 4... Second output terminal I, 5... Buffer circuit, 6... Flip-flop circuit , 7.8...
・Inverter circuit, C... capacitor, R1... first resistor, R2... second resistor, T... time,
■1...First voltage, ■2...Second voltage, Vc.
...DC power supply voltage.

Claims (1)

【特許請求の範囲】[Claims] マイクロコンピュータシステムの動作中に停電が起きた
時に、電源電圧が所定値以下に低下したことを検知し、
この電源電圧が遮断する前に動作を停止させたり、リセ
ット等の割り込みをして停電処理を行なうマイクロコン
ピュータシステムにおいて、マイクロコンピュータシス
テムへの電源電圧が供給されて、第1の電圧とこの第1
の電圧より低い第2の電圧とを検出した時にそれぞれ送
出信号の状態が変化する第1および第2の出力端子を有
する電圧検出回路と、第1の出力端子の信号の状態をC
PUに供給するバッファ回路と、前記電源電圧が第1の
電圧よりも高い状態から低い状態に推移したことを前記
CPUに送出するフリップフロップ回路と、第2の出力
端子の出力信号が一端に供給される第1の抵抗器と、こ
の第1の抵抗器の他端が接続される他端が接地された第
2の抵抗器および他端に前記電源電圧が供給されたコン
デンサと、第1の抵抗器の他端よりの出力信号により前
記CPUへのリセット信号を得る回路とを備え、前記電
源電圧が第1の電圧以下になった時に前記CPUへ割り
こみをして停電処理を行ない、所定時間内に前記電源電
圧が回復した際には、停電処理の復帰処理を行ない、前
記電源電圧が第2の電圧以下になった時に前記CPUを
リセットするようにしたマイクロコンピュータシステム
の停電時の処理方法。
When a power outage occurs while the microcomputer system is operating, it detects that the power supply voltage has dropped below a predetermined value.
In a microcomputer system that handles a power outage by stopping the operation or by interrupting such as a reset before this power supply voltage is cut off, the power supply voltage is supplied to the microcomputer system, and the first voltage and this first voltage are
A voltage detection circuit has first and second output terminals that each change the state of a sending signal when detecting a second voltage lower than the voltage of C;
A buffer circuit that supplies the PU, a flip-flop circuit that sends to the CPU that the power supply voltage has transitioned from a state higher than the first voltage to a lower state, and an output signal of a second output terminal is supplied to one end. a second resistor whose other end is grounded to which the other end of the first resistor is connected; and a capacitor whose other end is supplied with the power supply voltage; a circuit that obtains a reset signal to the CPU based on an output signal from the other end of the resistor, and interrupts the CPU to perform power outage processing when the power supply voltage becomes lower than a first voltage, and When the power supply voltage is restored within a time, a recovery process of the power failure process is performed, and when the power supply voltage becomes equal to or lower than a second voltage, the CPU is reset. Method.
JP61249038A 1986-10-20 1986-10-20 Processing method for microcomputer system at time of service interruption Pending JPS63103311A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61249038A JPS63103311A (en) 1986-10-20 1986-10-20 Processing method for microcomputer system at time of service interruption

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61249038A JPS63103311A (en) 1986-10-20 1986-10-20 Processing method for microcomputer system at time of service interruption

Publications (1)

Publication Number Publication Date
JPS63103311A true JPS63103311A (en) 1988-05-09

Family

ID=17187075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61249038A Pending JPS63103311A (en) 1986-10-20 1986-10-20 Processing method for microcomputer system at time of service interruption

Country Status (1)

Country Link
JP (1) JPS63103311A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033034U (en) * 1988-06-15 1991-01-14
JPH03501796A (en) * 1988-06-29 1991-04-18 マース,インコーポレィテッド Electronic pay phone open switch interval control method and device
US8916255B2 (en) 2010-03-29 2014-12-23 Ykk Corporation Fastener tape and fastener stringer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55149879A (en) * 1978-09-05 1980-11-21 Motorola Inc Fet voltage level detection circuit
JPS61114323A (en) * 1984-11-09 1986-06-02 Hitachi Ltd Processing method for abnormality of power supply of information processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55149879A (en) * 1978-09-05 1980-11-21 Motorola Inc Fet voltage level detection circuit
JPS61114323A (en) * 1984-11-09 1986-06-02 Hitachi Ltd Processing method for abnormality of power supply of information processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033034U (en) * 1988-06-15 1991-01-14
JPH03501796A (en) * 1988-06-29 1991-04-18 マース,インコーポレィテッド Electronic pay phone open switch interval control method and device
US8916255B2 (en) 2010-03-29 2014-12-23 Ykk Corporation Fastener tape and fastener stringer

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