JPH05108503A - Power failure processing system - Google Patents
Power failure processing systemInfo
- Publication number
- JPH05108503A JPH05108503A JP3167355A JP16735591A JPH05108503A JP H05108503 A JPH05108503 A JP H05108503A JP 3167355 A JP3167355 A JP 3167355A JP 16735591 A JP16735591 A JP 16735591A JP H05108503 A JPH05108503 A JP H05108503A
- Authority
- JP
- Japan
- Prior art keywords
- power failure
- cpu
- power
- circuit
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims abstract description 12
- 238000011084 recovery Methods 0.000 claims description 10
- 230000006870 function Effects 0.000 claims description 2
- 230000007257 malfunction Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は落雷，高負荷モータの起
動等による瞬時の電源電圧の低下（以下、瞬時停電とい
う）と長時間の電源電圧低下（以下、停電という）とを
判別し、マイクロコンピュータのデータの破壊を防止
し、制御回路の誤動作を未然に防ぐことを目的とした停
電処理方式に関するものである。BACKGROUND OF THE INVENTION The present invention distinguishes between a momentary power supply voltage drop (hereinafter referred to as momentary power failure) and a long-term power supply voltage drop (hereinafter referred to as power failure) due to lightning strikes, high-load motor startup, and the like. The present invention relates to a power failure processing method for preventing data destruction of a microcomputer and preventing malfunction of a control circuit.
【０００２】[0002]
【従来の技術】一般にマイクロコンピュータ（以下、Ｃ
ＰＵという）を用いた制御回路において、停電が起こっ
た場合は、電源回復時に必要なデータをメモリ上に保存
し、電源回復時にはＣＰＵがそれらのデータをもとに制
御回路を規定のシーケンス通り動作させるように停電処
理回路を設けることが通常となっている。2. Description of the Related Art Generally, a microcomputer (hereinafter referred to as C
When a power failure occurs in a control circuit using (PU), necessary data is saved in the memory when power is restored, and when power is restored, the CPU operates the control circuit according to the prescribed sequence based on the data. It is usual to provide a power failure processing circuit to do so.
【０００３】従来、この停電処理回路は図３に一例を示
すように、停電時には商用電源の低下を検出する停電検
出回路５からの停電信号を、「Ｈ」レベルから「Ｌ」レ
ベルへの変化を検知できるＣＰＵ１の入力端子６に入力
する構成となっていた。通常、商用電源が停電してから
直流電源回路４の出力電圧がＣＰＵ１の動作電圧以下に
低下するまでに数十［ｍｓ］程度の時間がある。停電が
起こると停電検出回路５が停電を検知し、ＣＰＵ１の入
力端子６に停電検知信号が入力される。するとＣＰＵ１
は現在実行中のプログラムを中断し、停電回復時に必要
なデータをメモリ２に書き込み、そのデータが変化しな
い様、自身の動作を停止せしめることをこの時間内に行
う。一方、停電回復時にはリセット回路８からのリセッ
ト信号がＣＰＵ１のリセット端子９に入力されるためＣ
ＰＵ１は動作を開始する。これらの一連の動作を図４及
び図５により説明する。Conventionally, this power failure processing circuit changes a power failure signal from a power failure detection circuit 5 for detecting a decrease in commercial power supply from a "H" level to an "L" level when a power failure occurs, as shown in FIG. Is inputted to the input terminal 6 of the CPU 1 capable of detecting the. Usually, it takes several tens [ms] until the output voltage of the DC power supply circuit 4 drops below the operating voltage of the CPU 1 after the commercial power supply fails. When a power failure occurs, the power failure detection circuit 5 detects the power failure, and the power failure detection signal is input to the input terminal 6 of the CPU 1. Then CPU1
Stops the program currently being executed, writes the necessary data to the memory 2 when power is restored, and stops its own operation within this time so that the data does not change. On the other hand, when the power is restored, the reset signal from the reset circuit 8 is input to the reset terminal 9 of the CPU 1 so that C
PU1 starts operation. A series of these operations will be described with reference to FIGS.
【０００４】図４は、従来の停電処理回路を用いた場合
の動作タイミングを示すタイミング図、図５はＣＰＵの
動作フローチャート図である。図４に示すように、停電
が起こると停電検出回路５の停電信号は「Ｈ」レベルか
ら「Ｌ」レベルに変化する。この変化が入力端子６に入
力されるとＣＰＵ１は直ちに現在実行中のプログラムを
中断し、停電回復時に必要なデータをメモリ２に書き込
み、自身の動作を停止せしめる。その後、停電が継続し
た場合は、直流電源回路４の出力電圧がＣＰＵ１の動作
電圧以下まで低下する。一方、停電回復時には、直流電
源回路４の出力電圧がＣＰＵ１の動作電圧以下になり、
その後、数十ｍｓ遅れてリセット回路８が動作し、
「Ｌ」レベルから「Ｈ」レベルへ変化するリセット信号
８をＣＰＵ１のリセット入力端子９に入力する。リセッ
ト入力端子にリセット信号が入力されるとＣＰＵ１は動
作を開始し、バックアップ回路３により保持されている
メモリ２のデータをもとに規定のシーケンスに従い、制
御回路を動作せしめるようになっている。FIG. 4 is a timing chart showing the operation timing when the conventional power failure processing circuit is used, and FIG. 5 is an operation flow chart of the CPU. As shown in FIG. 4, when a power failure occurs, the power failure signal of the power failure detection circuit 5 changes from "H" level to "L" level. When this change is input to the input terminal 6, the CPU 1 immediately interrupts the program that is currently being executed, writes necessary data to the memory 2 when power is restored, and stops its own operation. After that, when the power failure continues, the output voltage of the DC power supply circuit 4 drops to the operating voltage of the CPU 1 or less. On the other hand, when the power is restored, the output voltage of the DC power supply circuit 4 becomes equal to or lower than the operating voltage of the CPU 1,
After that, the reset circuit 8 operates with a delay of several tens of ms,
The reset signal 8 that changes from the “L” level to the “H” level is input to the reset input terminal 9 of the CPU 1. When a reset signal is input to the reset input terminal, the CPU 1 starts its operation and operates the control circuit according to a prescribed sequence based on the data in the memory 2 held by the backup circuit 3.
【０００５】また、図示しないが、実開昭６０−２５０
０２号公報に見られるように、電源電圧が低下する時間
Ｔ1 とＣＰＵが停電処理に必要な時間Ｔ2 とを計数可能
なタイマーなどを用いて、ＣＰＵが瞬断か否か判断し、
瞬断の場合は元の処理を継続し、一定時間経過後も停電
信号が存在していれば瞬時停電ではなく停電であったと
判断し停電処理を行うように構成された制御装置もあ
る。Although not shown in the drawing, the actual construction number 60-250
As can be seen in Japanese Patent Laid-Open No. 02-202, a timer or the like capable of counting the time T 1 for which the power supply voltage drops and the time T 2 required for the CPU to perform a power outage is used to determine whether or not the CPU has an instantaneous interruption,
There is also a control device configured to continue the original processing in the case of a momentary interruption and to judge that it is not an instantaneous power outage but a power outage if the power outage signal is present even after the elapse of a certain time, and perform the power outage processing.
【０００６】さらに、図示しないが、特開昭５８−１０
１３４８公報に見られるように、強制割込みが発生した
ときに割込み要因を調べて割り込み処理を行うか否かを
判定し、割込み要因が不明の場合は無処理で元のルーチ
ンへ戻り、雑音などの影響を最小限にとどめることを目
的とした強制割込処理方式もある。Further, although not shown, JP-A-58-10
As can be seen in Japanese Patent No. 1348, when a forced interrupt occurs, the interrupt factor is checked to determine whether or not the interrupt process is to be performed. If the interrupt factor is unknown, the process returns to the original routine without any processing, and noise etc. There is also a forced interrupt processing method that aims to minimize the effect.
【０００７】[0007]
【考案が解決しようとする課題】しかしながら、図３に
示した従来の停電処理回路では、図５のフローチャート
のように、停電が停電検出回路５によって検出され直流
電源電圧がＣＰＵ１の動作電圧以下に低下するまで継続
すればよいが、停電が非常に短時間であったり、ノイズ
等の外乱により停電信号が瞬間的に「Ｈ」から「Ｌ」に
変化した場合には、ＣＰＵ１は必要なデータをメモリに
書き込み、自身の動作を停止するにもかかわらず直流電
源回路４の出力電圧が低下しない。このため電源電圧回
復時にしか動作しないリセット回路８が動作せず、リセ
ット入力端子９にリセット信号が入力されない。したが
って制御回路は停止したまま、全く動作しないという致
命的な欠点があった。However, in the conventional power failure processing circuit shown in FIG. 3, the power failure is detected by the power failure detection circuit 5 and the DC power supply voltage becomes equal to or lower than the operating voltage of the CPU 1 as shown in the flowchart of FIG. Although it may be continued until it drops, if the power failure is very short or the power failure signal instantaneously changes from "H" to "L" due to disturbance such as noise, the CPU 1 outputs necessary data. The output voltage of the DC power supply circuit 4 does not drop despite writing to the memory and stopping its own operation. Therefore, the reset circuit 8 that operates only when the power supply voltage is restored does not operate, and the reset signal is not input to the reset input terminal 9. Therefore, there is a fatal defect that the control circuit remains stopped and does not operate at all.
【０００８】また、実開昭６０−２５００２号公報に示
されるような停電処理を行う制御装置では、通常、商用
電源の停電が発生してからＣＰＵの作動電源である直流
電源回路の電源電圧が、ＣＰＵの動作電圧の下限まで低
下するまでの時間（これをＴ1 とする。）は数１０［ｍ
ｓ］であり、かつ制御装置の負荷の状態などにより大き
く変動する場合がある。従って、タイマー時間Ｔの設定
は、この電源電圧が低下する時間Ｔ1 とＣＰＵが停電処
理に必要な時間（これをＴ2 とする。）の和よりも短く
しなければならない。すなわち、Ｔ＜Ｔ1 ＋Ｔ2 が必要
条件にとなる。ところで、前述のようにＴ1 は大きく変
動するため、タイマー時間の設定によってはこの条件を
満足することができない場合が発生し、正常な停電処理
ができない可能性がある。すなわち、停電が瞬時停電か
通常の停電かを判断するのにタイマー時間を用いる方式
のものは、瞬時停電がタイマー時間より十分短い場合は
よいが、これ以外の場合は正常な停電処理ができず、停
電回復時に正しい制御が保証されないという致命的な欠
点を有していた。Further, in a control device for performing a power failure process as disclosed in Japanese Utility Model Laid-Open No. 60-25002, the power supply voltage of the DC power supply circuit, which is the operating power supply of the CPU, is usually set after the commercial power supply fails. , The time required for the operating voltage of the CPU to fall to the lower limit (this is T 1 ) is several tens [m
s], and may greatly vary depending on the load condition of the control device. Therefore, the timer time T must be set shorter than the sum of the time T 1 for which the power supply voltage drops and the time required for the CPU to perform the power outage (this is referred to as T 2 ). That is, T <T 1 + T 2 is a necessary condition. By the way, as described above, T 1 fluctuates greatly, so that this condition may not be satisfied depending on the setting of the timer time, and normal power failure processing may not be possible. In other words, the method that uses the timer time to determine whether the power failure is an instantaneous power failure or a normal power failure is good when the instantaneous power failure is sufficiently shorter than the timer time, but in other cases, normal power failure processing cannot be performed. However, it had a fatal drawback that correct control could not be guaranteed when power was restored.
【０００９】また、特開昭５８−１０１３４８公報に示
されるような強制割込処理方式では、電源断による割込
み発生時データをバッテリーサポートされたＲＡＭメモ
リ上に写すという処理は可能であっても停電回復時の処
理に対しては何ら考慮されていない。すなわち、電源断
による強制割込み発生時に電源断であることを認識して
バックアップされたメモリ上にデータを退避させた後、
メインルーチンへ戻り元のプログラムを実行するのであ
れば当然通常使用するＲＡＭ内のデータとバックアップ
されたＲＡＭ内のデータは違うものとならざるを得な
い。従って、通常停電回復後にはバックアップされたＲ
ＡＭ内のデータを使用し、プログラムを実行するようプ
ログラムされていると考えると、停電時には次の流れで
プログラムは実行される。 (1) 停電（割込み発生）→(2) データ退避（割込み処
理）→(3) 元のメインルーチン実行→(4) ＭＰＵ（ＣＰ
Ｕ）停止→(5) 電源回復→(6) バックアップされたＲＡ
Ｍ内のデータを使用してメインルーチン実行となる。従
って、前記(3) 番目の元のメインルーチン実行時におけ
るデータは失われることになり、電源回復時点では前記
(3) 番目元のメインルーチン実行前の時点のデータによ
りメインルーチンを実行することになるため、正常に停
電バックアップできないという問題点があった。Further, in the forced interrupt processing system as disclosed in Japanese Patent Laid-Open No. 58-101348, even if the processing of copying the data at the time of the interrupt due to the power interruption to the RAM memory supported by the battery is possible, the power failure occurs. No consideration is given to the recovery process. That is, after recognizing that the power is cut off when a forced interrupt occurs due to the power cut and saving the data in the backed up memory,
If the original program is executed by returning to the main routine, naturally the data in the RAM normally used and the data in the backed up RAM must be different. Therefore, after normal power failure recovery, backup R
Considering that the data in the AM is used and programmed to execute the program, the program is executed in the following flow at the time of power failure. (1) Power failure (interrupt occurrence) → (2) Data save (interrupt processing) → (3) Original main routine execution → (4) MPU (CP
U) Stop → (5) Power recovery → (6) Backed up RA
The data in M is used to execute the main routine. Therefore, the data will be lost when the (3) th original main routine is executed, and the data will be lost when the power is restored.
(3) Since the main routine is executed according to the data before the execution of the 3rd original main routine, there was a problem that the power failure could not be backed up normally.
【００１０】[0010]
【課題を解決するための手段】本発明はこれらの問題点
を解決するもので、ＣＰＵの入力端子を一つ増加させる
のみで瞬時停電やノイズによる停電信号の変化と、通常
の停電とを停電処理プログラム内で判別し、瞬時停電の
場合はそのまま通常の処理プログラムに戻り制御回路を
継続させて動作させ、通常の停電の場合は停電回復時に
規定のシーケンス通りに制御回路を動作せしめる様に構
成された停電処理方式を提供するものである。すなわ
ち、本発明は、電気信号の「Ｈ」レベルから「Ｌ」レベ
ルへの変化を検知できる入力端子６と、電気信号の
「Ｈ」レベルか「Ｌ」レベルかを検知できる入力端子７
と、リセット端子９とを具備した比較判断機能を有し、
商用電源の停電を検出した後プログラムは停止せずに、
停電回復を入力する停電処理プログラムを実行するよう
にしたＣＰＵ１と、該ＣＰＵ１のデータを記憶するメモ
リ２と、停電時にメモリ２の内容を保持するためのバッ
クアップ回路３と、商用電源の停電を検出し、入力端子
６、７へ信号を発する停電検出回路５と、停電回復時に
ＣＰＵ１の動作を開始せしめるべくＣＰＵ１のリセット
端子９にリセット信号を発するリセット回路８およびこ
れらの回路に電圧，電流を供給する直流電源回路４より
構成されており、停電による停電信号が入力端子６に入
力された場合に、直ちに停電処理（データの退避の処
理）を行い、その停電処理プログラム内で電源回復をす
るか否かを別の入力端子７によりＣＰＵ１で監視し、瞬
時停電の場合はそのまま通常の処理プログラムを継続さ
せて動作させ、通常の停電の場合は停電前の仕事の内容
をメモリ２にて保持し、停電回復時に保持した仕事の内
容に従って制御回路を規定のシーケンス通り動作せしめ
るべく構成された停電処理方式である。SUMMARY OF THE INVENTION The present invention solves these problems by changing the power failure signal due to momentary power failure or noise and normal power failure by only increasing the number of input terminals of the CPU. Determined in the processing program, if there is an instantaneous power failure, return to the normal processing program and continue to operate the control circuit, and if there is a normal power failure, operate the control circuit according to the specified sequence when power is restored It provides a fixed power failure processing method. That is, according to the present invention, the input terminal 6 capable of detecting the change of the electric signal from the “H” level to the “L” level and the input terminal 7 capable of detecting the “H” level or the “L” level of the electric signal.
And a comparison / judgment function having a reset terminal 9,
After detecting the power failure of the commercial power supply, the program does not stop,
A CPU 1 that executes a power failure processing program for inputting power failure recovery, a memory 2 that stores data of the CPU 1, a backup circuit 3 that retains the contents of the memory 2 when a power failure occurs, and a power failure of a commercial power source is detected. Then, the power failure detection circuit 5 which issues a signal to the input terminals 6 and 7, the reset circuit 8 which issues a reset signal to the reset terminal 9 of the CPU 1 so as to start the operation of the CPU 1 when the power failure is restored, and the voltage and current are supplied to these circuits. If the power failure signal due to a power failure is input to the input terminal 6, the power failure processing (data saving processing) is immediately performed and the power is restored in the power failure processing program. Whether or not it is monitored by the CPU 1 through another input terminal 7, and in the case of an instantaneous power failure, the normal processing program is continued and operated, The event of a power failure holds the contents of the previous work power failure in the memory 2 is configured outage management system so allowed to operation sequence as a defined control circuit according to the contents of the job held in the event of a power failure recovery.
【００１１】[0011]
【実施例】本発明の実施例を図１及び図２により説明す
る。停電検出回路５の出力は、ＣＰＵ１の「Ｈ」レベル
から「Ｌ」レベルへの変化を検出できる入力端子６と、
「Ｈ」か「Ｌ」かのレベルを検出できる入力端子７とに
接続されており、停電が起こると、ＣＰＵ１は、入力端
子６に入力されている停電検出回路５の出力である停電
信号の「Ｈ」→「Ｌ」の変化を検出することによって、
停電がおきたことを認識し、直ちに現在実行中のプログ
ラムを中断し、停電回復時に必要なデータをメモリ２に
書き込み、その後入力端子７に入力されている停電信号
のレベルを監視する。つまり、図２の動作フローチャー
ト図に示すように、所定のデータをメモリ２に書き込ん
だ後、停電信号が「Ｈ」レベルか「Ｌ」レベルかをチェ
ックすることにより停電が非常に短時間で回復したかど
うかを判別することが可能となる。入力端子７に入力さ
れている停電信号レベルが「Ｈ」レベルであった場合に
はＣＰＵ１は停電が非常に短時間であったと判断し、中
断していたプログラムを再開し、通常の制御回路の制御
を続ける。また停電信号レベルが「Ｌ」レベルのままで
あった場合は、そのまま停電信号のレベルの監視を続
け、停電信号が「Ｌ」レベルのまま直流電源回路４の出
力電圧がＣＰＵ１の動作電圧以下に低下した場合は、Ｃ
ＰＵ１の動作が停止する。停電回復時にはリセット回路
８からのリセット信号によりＣＰＵ１は動作を再開し、
バックアップ回路３により保持されているメモリ２のデ
ータをもとに制御回路を規定のシーケンス通りに制御す
る。Embodiments of the present invention will be described with reference to FIGS. The output of the power failure detection circuit 5 is an input terminal 6 capable of detecting a change from the “H” level to the “L” level of the CPU 1,
When a power failure occurs, the CPU 1 is connected to the input terminal 7 capable of detecting the level of "H" or "L", and the CPU 1 outputs the power failure signal output from the power failure detection circuit 5 input to the input terminal 6 to the power failure signal. By detecting the change from "H" to "L",
It recognizes that a power failure has occurred, immediately interrupts the program that is currently being executed, writes the necessary data to the memory 2 at the time of power failure recovery, and then monitors the level of the power failure signal input to the input terminal 7. That is, as shown in the operation flow chart of FIG. 2, after writing predetermined data to the memory 2, the power failure is recovered in a very short time by checking whether the power failure signal is at “H” level or “L” level. It is possible to determine whether or not it has been done. When the power failure signal level input to the input terminal 7 is the "H" level, the CPU 1 determines that the power failure is extremely short, restarts the interrupted program, and restarts the normal control circuit. Continue control. If the power failure signal level remains at the “L” level, the power failure signal level is continuously monitored as it is, and the output voltage of the DC power supply circuit 4 falls below the operating voltage of the CPU 1 while the power failure signal remains at the “L” level. If decreased, C
The operation of PU1 stops. At the time of power failure recovery, the CPU 1 restarts the operation by the reset signal from the reset circuit 8,
Based on the data in the memory 2 held by the backup circuit 3, the control circuit is controlled in a prescribed sequence.
【００１２】[0012]
【発明の効果】以上の説明から容易に理解されるよう
に、本発明は停電期間が非常に短い瞬時停電や、ノイズ
等の外乱による停電検出回路５の誤動作によってＣＰＵ
１が停電を検知しても制御回路は正常な動作を継続し、
かつ通常の停電によりＣＰＵの動作が停止した場合も停
電回復時には正しい動作シーケンスにより制御回路を動
作させるという信頼性の高い停電処理方式が得られる。As can be easily understood from the above description, the present invention provides a CPU due to a malfunction of the power failure detection circuit 5 due to an instantaneous power failure with a very short power failure period or a disturbance such as noise.
Even if 1 detects a power failure, the control circuit continues normal operation,
Further, even when the operation of the CPU is stopped due to a normal power failure, a highly reliable power failure processing method in which the control circuit is operated in the correct operation sequence at the time of power failure recovery can be obtained.
【図１】 本発明の停電処理回路のブロック図。FIG. 1 is a block diagram of a power failure processing circuit according to the present invention.
【図２】 本発明の停電処理回路を用いた場合の動作フ
ローチャート図。FIG. 2 is an operation flowchart when the power failure processing circuit of the present invention is used.
【図３】 従来の停電処理回路のブロック図。FIG. 3 is a block diagram of a conventional power failure processing circuit.
【図４】 従来の停電処理回路を用いた場合の動作タイ
ミング図。FIG. 4 is an operation timing chart when a conventional power failure processing circuit is used.
【図５】 従来の停電処理回路を用いた場合の動作フロ
ーチャート図。FIG. 5 is an operation flowchart diagram when a conventional power failure processing circuit is used.
１ ＣＰＵ。 ２ メモ
リ。 ３ バツクアップ回路。 ４ 直流電
源回路。 ５停電検出回路。 ６ 入力端
子。 ７ 入力端子。 ８ リセッ
ト回路。 ９ 入力端子。1 CPU. 2 memory. 3 Backup circuit. 4 DC power supply circuit. 5 Power failure detection circuit. 6 input terminals. 7 Input terminal. 8 Reset circuit. 9 Input terminals.
Claims (1)
ルへの変化を検知できる入力端子６と、電気信号の
「Ｈ」レベルか「Ｌ」レベルかを検知できる入力端子７
と、リセット端子９とを具備した比較判断機能を有し、
商用電源の停電を検出した後プログラムは停止せずに、
停電回復を入力する停電処理プログラムを実行するよう
にしたＣＰＵ１と、該ＣＰＵ１のデータを記憶するメモ
リ２と、停電時にメモリ２の内容を保持するためのバッ
クアップ回路３と、商用電源の停電を検出し、入力端子
６、７へ信号を発する停電検出回路５と、停電回復時に
ＣＰＵ１の動作を開始せしめるべくＣＰＵ１のリセット
端子９にリセット信号を発するリセット回路８およびこ
れらの回路に電圧，電流を供給する直流電源回路４より
構成されており、停電による停電信号が入力端子６に入
力された場合に、直ちに停電処理（データの退避の処
理）を行い、その停電処理プログラム内で電源回復をす
るか否かを別の入力端子７によりＣＰＵ１で監視し、瞬
時停電の場合はそのまま通常の処理プログラムを継続さ
せて動作させ、通常の停電の場合は停電前の仕事の内容
をメモリ２にて保持し、停電回復時に保持した仕事の内
容に従って制御回路を規定のシーケンス通り動作せしめ
るべく構成された停電処理方式。1. An input terminal 6 capable of detecting a change from an “H” level of an electric signal to an “L” level, and an input terminal 7 capable of detecting whether the electric signal is at an “H” level or an “L” level.
And a comparison / judgment function having a reset terminal 9,
After detecting the power failure of the commercial power supply, the program does not stop,
A CPU 1 that executes a power failure processing program for inputting power failure recovery, a memory 2 that stores data of the CPU 1, a backup circuit 3 that retains the contents of the memory 2 when a power failure occurs, and a power failure of a commercial power source is detected. Then, the power failure detection circuit 5 which issues a signal to the input terminals 6 and 7, the reset circuit 8 which issues a reset signal to the reset terminal 9 of the CPU 1 so as to start the operation of the CPU 1 when the power failure is restored, and the voltage and current are supplied to these circuits. If the power failure signal due to a power failure is input to the input terminal 6, the power failure processing (data saving processing) is immediately performed and the power is restored in the power failure processing program. Whether or not it is monitored by the CPU 1 through another input terminal 7, and in the case of an instantaneous power failure, the normal processing program is continued and operated, The event of a power failure holds the contents of the previous work power failure in the memory 2, configured outage management system so allowed to operation sequence as a defined control circuit according to the contents of the job held in the event of a power failure recovery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3167355A JPH06103480B2 (en) | 1991-04-26 | 1991-04-26 | Blackout processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3167355A JPH06103480B2 (en) | 1991-04-26 | 1991-04-26 | Blackout processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05108503A true JPH05108503A (en) | 1993-04-30 |
| JPH06103480B2 JPH06103480B2 (en) | 1994-12-14 |
Family
ID=15848188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3167355A Expired - Lifetime JPH06103480B2 (en) | 1991-04-26 | 1991-04-26 | Blackout processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06103480B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6882903B2 (en) | 2003-03-07 | 2005-04-19 | Orion Electric Company Ltd. | Electric device |
| JP2008052440A (en) * | 2006-08-23 | 2008-03-06 | Toyota Motor Corp | Data holding device |
| AU2015250193B2 (en) * | 2014-04-25 | 2017-01-12 | Siemens Healthcare Diagnostics Inc. | Sample collection unit |
-
1991
- 1991-04-26 JP JP3167355A patent/JPH06103480B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6882903B2 (en) | 2003-03-07 | 2005-04-19 | Orion Electric Company Ltd. | Electric device |
| JP2008052440A (en) * | 2006-08-23 | 2008-03-06 | Toyota Motor Corp | Data holding device |
| AU2015250193B2 (en) * | 2014-04-25 | 2017-01-12 | Siemens Healthcare Diagnostics Inc. | Sample collection unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06103480B2 (en) | 1994-12-14 |
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