JPH10105422A - Control circuit of protecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly output a control signal even at the time of abnormality in the operation of a microprocessor. SOLUTION: The output of CPU 1 is connected to a first switch 3. CPU 1 reads a count value written in a common memory 8 by CPU 5 and judges that the operation of CPU 5 becomes abnormal unless the count value is changed. When the abnormality of CPU 5 is detected, CPU 1 outputs a reset signal and permits CPU 5 to be a reset state. Since the output of CPU 5 is set to be a high level at the time of resetting, a high level signal is given to the control terminal of the first switch and the first switch becomes an ON-state. Thus, the output signal of CPU 1 is outputted to an outside with the switch 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a control circuit for outputting a signal for controlling a protection device.

[0002]

2. Description of the Related Art In a control circuit for controlling a relay such as a protection relay, a single microprocessor cannot specify an output state of the control circuit to a specific state when the microprocessor goes out of control. The circuit has been duplicated by using the same.

FIG. 3 is a diagram showing an example of a conventional control circuit in which two independent circuits having the same configuration are provided. The outputs of the instrument transformer PT and the current transformer CT are input to the two band-pass filters BPF and the amplifier circuits 22 and 23 via the auxiliary transformer 21, respectively. 25. And C
The PUs 24 and 25 perform a calculation for measurement or display and a process of determining the quality of the relay control signal. The input signal Di is input to the CPUs 24 and 25 via the photocouplers 26, and is subjected to predetermined determination processing by the CPUs 24 and 25, and is output as an output signal Do. A response signal Doans of this output signal Do is returned to the CPUs 24 and 25. Further, the CPU 25 outputs a display signal for detecting the operation signal of the operation switch 27 and displaying the operation state to the liquid crystal driver 28 and causes the liquid crystal display unit 29 to display the display signal. In addition, there is a common memory 30 commonly used by the CPUs 24 and 25.

Output signals Do output from the CPUs 24 and 245 are output to control terminals of relays 30 and 31, respectively. The relays 30 and 31 are connected in series, and when the CPUs 24 and 25 are both outputting the output signal Do, the two relays are turned on.

In the circuit described above, since the two CPUs are performing the same processing, the processing load on the two CPUs is equal, and when there is not enough processing capacity to add new processing, It is necessary to add a CPU separately, and there has been a problem that a load on hardware is increased.

It is an object of the present invention to improve the efficiency of processing of two microprocessors and to output a control signal properly even when the operation of the microprocessors is abnormal.

[0007]

The control circuit according to the present invention comprises:
A first microprocessor having a storage unit for storing data, an output terminal for performing predetermined processing on an input signal and outputting the result to the outside, and writing first data to the storage unit; First switch means connected in series to the output terminal of the microprocessor, and writing the second data to the storage means, and determining whether the first microprocessor operates normally from the first data. According to the present invention, the first microprocessor performs ON / OFF of the first switch means based on the determination result, and causes the first microprocessor to perform predetermined processing on the input signal. The second microprocessor monitors the operation of the first microprocessor, and turns on and off the first switch means based on the result. Lee black occurs margin in processor power, it is possible to execute other processing. When the first microprocessor is operating normally, the first switch is turned on to output an output signal of the first microprocessor. When the operation of the first microprocessor is defective, Since the first switch is turned off to cut off the output signal of the first microprocessor, an erroneous output can be prevented and a proper signal can be output to the outside.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram of a control circuit of the protection device according to the embodiment of the present invention.

An input signal Di for controlling ON / OFF of a protection device, for example, a protection relay, is input to an input terminal of a main CPU 1 and also to one input terminal of a second switch 2.

The relay control signal Do output from the output terminal Dd of the CPU 1 is input to the first switch 3,
The signal output from the output terminal Do2 of the CPU1 is input to the reset terminal of the sub CPU5.

The reset terminal RS of the CPU 1
The output of the watchdog timer 6 is connected. The output of the watchdog timer 6 is the NOR gate 4
And the output of the NOR gate 4 is input to the control terminal of the second switch 2 described above. Outputs of the first switch 3 and the second switch 2 are input to an OR gate 7.

The CPU 1 resets the count value of the watchdog timer 6 at regular intervals, and when the CPU 1 is operating normally, the count value of the watchdog timer 6 always becomes less than the certain value. No up signal is output. Therefore, the output of the NOR gate 4 is always at the low level, and the second switch 2 is turned off.

On the other hand, if the operation of the CPU 1 becomes abnormal, the count value of the watchdog timer 6 is not reset by the CPU 1, and a low-level count-up signal is output to the NOR gate 4. As a result, the output signal of the NOR gate 4, that is, the signal given to the control terminal of the second switch 2 becomes high level, and the second switch 2 is turned on. Since the input signal Di is input to the input terminal of the second switch 2, the input signal D
i is output as it is.

Further, the CPU 1 and the CPU 5 are provided in the common memory 8 with write areas for counting up at regular intervals. The write areas are read from each other at regular intervals, and when the count value changes, It is determined that the other CPU is operating normally, and if the count value does not change, it is determined that the operation of the other CPU has become abnormal.

The signal output from the output terminal Do1 of the CPU 5 is input to the control terminal of the first switch 3,
5 is output from the output terminal DO2 of the NOR gate 4
Is being entered.

When the CPU 1 is operating normally,
Since a high-level signal is output from the output terminal Do1 of the CPU 5 to the control terminal of the first switch 3, the first switch 3 is turned on. At this time, after determining whether or not the input signal Di (relay control signal for controlling ON / OFF of the relay) input to the CPU 1 is normal, the output terminal Do1 is determined.
The signal after the determination is output as the relay control signal Do. This output signal Do is output to the outside through the first switch 3 and the OR gate 7.

Next, the operation of the embodiment having the above configuration will be described. First, a case where the CPU 1 and the CPU 5 are operating normally will be described. In this case, a signal for resetting the CPU 5 is not output from the output terminal Do2 of the CPU1. Then, a high-level signal is output from the CPU 5 to the control terminal of the first switch 3, and the first switch 3 is turned on. When an input signal is input to the input terminal Di of the CPU 1, the CPU 1 performs a process of determining whether the signal is normal. If the signal is normal, the CPU 1 outputs the signal (relay control signal) from the output terminal Do1. At this time, since the first switch 3 is on, the relay control signal is output to the outside via the first switch 3 and the OR gate 7.

Next, a case where the operation of the CPU 5 becomes abnormal will be described. As described above, the CPU 5 counts up the count value to be written to the common memory 8 at a constant period, and the CPU 1 reads the count value,
If the count value does not change, it is determined that an abnormality has occurred in the CPU 5.

When detecting an abnormality of the CPU 5, the CPU 1 outputs a reset signal to a reset terminal of the CPU 5 and
PU5 is reset. Although the output of the CPU 5 at the time of resetting becomes high impedance, the output terminals Do1 and D1
Since o2 is pulled up by a resistor, the output terminals Do1 and Do2 attain a high level at reset. When the output terminal Do1 of the CPU 5 goes high,
The high-level signal is supplied to the control terminal of the first switch 3, and the first switch 3 is turned on.

Therefore, even if the operation of the CPU 5 becomes abnormal, the relay control signal, for which the CPU 1 has determined the quality, can be output to the outside via the first switch 3 and the OR gate 7.

Next, a case where the operation of the CPU 1 is abnormal will be described. Similarly to the CPU 5, the CPU 1 counts up the count value to be written to the common memory 8 at a constant cycle. The CPU 5 reads the count value, and if the count value does not change, determines that an abnormality has occurred in the CPU 1. .

When an abnormal operation of the CPU 1 is detected,
5, a low-level signal is output to the NOR gate 4 from the output terminal Do2, and a high-level signal is supplied to the control terminal of the second switch 2 as the output of the NOR gate 4. As a result, the second switch 2 is turned on, and the input signal Di is directly output to the outside via the second switch 2 and the OR gate 7.

Therefore, even if the CPU 1 does not operate properly and cannot judge the quality of the relay control signal, it is possible to directly output a signal that needs to be output even when an error occurs, through the second switch 2.

Next, a case where both the operations of the CPU 1 and the CPU 2 become abnormal will be described. CPU1 and CP
When both U5 are malfunctioning, the CPU 1 does not perform the process of determining the relay control signal. At this time, the first switch 3 is turned off, and the first switch 3 does not output the relay control signal. However, C
When PU1 malfunctions, the watchdog timer 6
Is not reset, a low-level count-up signal is output from the watchdog timer 6 to the NOR gate 4, and a high-level signal is supplied to the control terminal of the second switch 2.

As a result, the second switch 2 is turned on, and an input signal can be directly output via the second switch 2. Therefore, it is possible to output a signal that needs to be output even at the time of abnormality.

According to the first embodiment, two CPs
If any of U1 and U5 malfunctions, the relay control signal can be reliably output. If the CPU1 in charge of the determination process for judging the quality of the relay control signal malfunctions, Another CPU 5 that monitors CPU 1
Turns off the first switch 3, so that the signal output from the CPU 1 is not erroneously output to the outside. Further, since the second switch is turned on under the control of the sub CPU 5 to directly output the relay control signal without passing through the CPU 1, it is possible to reliably output the signal that needs to be output in the event of an abnormality.

Then, only one CPU 1 performs the process of judging the quality of the relay control signal, and the other CPU 5 only needs to monitor the other CPU 1 for an abnormality.
The processing load on U5 is reduced. This makes it possible to cause the CPU 5 that does not perform the relay signal determination processing or the like to take charge of arithmetic processing for measurement, display processing, and the like, thereby increasing the processing amount of the entire control circuit without adding hardware. Can be.

Next, a second embodiment of the present invention will be described with reference to FIG. 2, the same components as those of the circuit block of FIG. 3 described in the related art are denoted by the same reference numerals, and description thereof will be omitted. The second embodiment corresponds to a circuit in which the second switch 2 of the first embodiment is omitted.

The switch 12 is connected to the output side of the CPU 11. The CPU 11 performs a process for determining an input signal (relay control signal), and outputs a signal after the determination to the control terminal of the relay 13 via the switch 12. It has become so. The CPU 11 performs measurement and protection relay calculation (e.g., determination of the quality of a relay control signal). The CPU 15 executes the indicating instrument calculation, the T-link calculation and the like instead of performing the protection relay calculation and the like, and outputs the calculation result to the liquid crystal display unit 16 and the T-link circuit 17.

When an input signal Di is input via the photocoupler 14, the CPU 11 determines the quality of the input signal, and then outputs a signal (relay control signal) Do after the determination to the switch 12. A signal output from an output terminal Do1 of the CPU 15 is input to a control terminal of the switch 12, and the CPU 15 controls the switch 12 to be turned on and off. The signal output from the output terminal Do1 of the CPU 11 is input to the reset terminal RS of the CPU 15. The output terminal Do1 of the CPU 15 is pulled up by a resistor, and outputs a high-level signal to the control terminal of the switch 12 at the time of reset.

The mutual monitoring of the CPUs is performed in the same manner as in the first embodiment. The two CPUs 11 and 15 each increment the count value to be written to the common memory 18 at a fixed period, and simultaneously monitor the other party. The count value is read, and if the read count value does not change, it is determined that the operation of the partner CPU has become defective.

Next, the operation of the second embodiment will be described. First,
The case where the operation of the CPU 15 becomes defective will be described. In this case, when detecting that the count value written in the common memory does not change, the CPU 11
The CPU 15 determines that U15 has failed.
Output a reset signal. The output terminal Do1 of the CPU 15 is pulled up by a resistor, and the output terminal Do1 becomes high level at the time of reset, so that the switch 12 is turned on.

As a result, the relay control signal output from the CPU 11 is output to the control terminal of the relay 13 via the switch 12, and the relay 13 is turned on. Next, C
A case where the operation of the PU 15 becomes defective will be described.
In this case, the CPU 15 reads the count written in the common memory 18 and, when the count value has not changed, determines that the CPU 11 has malfunctioned. Then, the output of the output terminal Do1 is set to the low level, and the switch 12 is turned off. Thereby, the CPU 11
In the case where the operation is defective, it is possible to prevent an erroneous signal from being output via the switch 12.

In the second embodiment, even when the operation of the sub CPU becomes defective, the switch 12 is turned on to
Since the relay control signal of U11 can be output,
Even if the CPU 11 fails, the input signal can be determined and the signal after the determination can be output. When the CPU 11 malfunctions, the output signal of the CPU 11 is prevented from being output to the outside.
Will not be accidentally turned on.

In the above embodiment, the sub CPUs 5, 1
5 is malfunctioning, the main CPUs 1 and 11
The U5 and 11 are reset so that the first switch 3 or the switch 12 is turned on. However, the present invention is not limited to this, and other circuits may be used.
If the operation failure of the switch 5 is detected, the CPU 1 or 11 may output a high-level signal to the control terminals of the switches 3 and 12.

The present invention is not limited to the control circuit of the protection relay, but can be applied to a control circuit for controlling the operation of various protection devices.

[0037]

According to the present invention, a switch is connected to the output of the first microprocessor, and the switch is turned on and off by the second microprocessor, so that the first microprocessor operates normally. When the first microprocessor is malfunctioning, the output can be cut off when the first microprocessor is malfunctioning. Therefore, it is possible to output a necessary signal and not to output an unnecessary signal that causes a malfunction. In addition, by providing the second switch, a necessary signal can be directly output to the outside even when the first microprocessor malfunctions.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a control circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram of a control circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit block diagram of a conventional control circuit.

[Explanation of symbols]

 1, 5, 11, 15, 24, 25 CPU 2 second switch 3 first switch 8, 18 common memory

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H02H 3/05 H02H 3/05 F

Claims (7)

[Claims] 1. A storage device for storing data, an output terminal for performing a predetermined process on an input signal and outputting the result to the outside, and a first device for writing first data to the storage device. A microprocessor, first switch means connected in series to an output terminal of the first microprocessor, and second data written to the storage means,
And a second microprocessor for turning on and off the first switch means based on the result of the determination as to whether or not the first microprocessor is operating normally from the data. The control circuit of the protection device. 2. The first microprocessor determines whether or not the second microprocessor is operating normally from the second data, and determines that the operation of the second microprocessor is abnormal. 2. The control device for a protection device according to claim 1, wherein in said case, said first switch means is turned on to output an output signal of said first microprocessor. A second switch means for directly outputting the input signal when in an on state, wherein the second microprocessor normally operates the first microprocessor based on the first data. 3. A method according to claim 1, further comprising: determining whether the operation is in operation, and controlling the second switch to be on or off based on a result of the determination to directly output or cut off the input signal.
A control circuit of the protection device according to the above. 4. When the second microprocessor determines that the first data is not a normal value and that the operation of the first microprocessor is abnormal, the second microprocessor switches the second switch. 4. The control circuit for a protection device according to claim 1, wherein the control circuit is turned on to directly output the input signal. 5. A timer for resetting a count operation by the first microprocessor, wherein when the count value of the timer becomes larger or smaller than a predetermined value, the operation of the first microprocessor is abnormal. 5. The method according to claim 1, wherein said timer turns on said second switch means and directly outputs said input signal via said second switch means. Protection device control circuit. , 6. The method according to claim 1, wherein the first data is a first count value rewritten by the first microprocessor at regular intervals, and the second data is a constant value by the second microprocessor at regular intervals. The second microprocessor is configured to rewrite the first count value when the first count value does not change.
When the operation of the microprocessor is determined to be abnormal, the second switch means is turned on to directly output the input signal. When the second count value does not change, the first microprocessor Determining that the operation of the second microprocessor is abnormal, turning on the first switch means, and outputting the output signal of the first microprocessor via the first switch. A control circuit for a protection device according to claim 1, 2, 3, 4, or 5. 7. The first switch means, wherein when the first microprocessor determines that the operation of the second microprocessor is abnormal, the first microprocessor resets the second microprocessor. The control circuit according to claim 1, 2, 3, 4, 5, or 65, wherein the control circuit is turned on.