JP3757407B2 - Control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device that monitors an abnormal operation of a control circuit, and more particularly to a control device that has a simple circuit configuration and can also check an abnormal operation of the monitoring circuit itself.
[0002]
[Prior art]
Conventionally, in a control device installed in a field or the like, due to the nature of the control device, it has been necessary to minimize adverse effects on external devices when a failure occurs in the control device.
[0003]
Specifically, it is necessary to prevent abnormal operations such as outputting abnormal control signals to field devices connected to the control device, blocking the data bus on the system side, and damaging the entire system. was there.
[0004]
For this reason, a conventional control device is provided with a monitoring circuit such as a watch dog timer (hereinafter referred to as WDT) to control abnormal operation of the control device, specifically, abnormal operation of a control circuit such as a microprocessor. To detect.
[0005]
If an abnormal operation of the control circuit is detected, the WDT resets the control circuit and cuts off the connection on the system side.
[0006]
FIG. 5 is a block diagram showing the configuration of such a conventional control apparatus. In FIG. 5, 1 is a control circuit such as a microprocessor for controlling the control device, 2 is an address decoder circuit, 3 is a logical product circuit, 4 is a conventional monitoring circuit such as WDT, 5 is a switch circuit, and 100 is data on the system side. The bus 101 is an address signal, 102 is a write enable signal, 103 is a chip select signal, and 104 is a reset signal.
[0007]
The data bus 100 is connected to the control circuit 1 through the switch circuit 5, and the address signal 101 from the control circuit 1 is connected to the address decoder circuit 2. A chip select signal 103 which is an output of the address decoder circuit 2 is connected to one input terminal of the AND circuit 3.
[0008]
The write enable signal 102 from the control circuit 1 is connected to the other input terminal of the AND circuit 3, and the output of the AND circuit 3 is connected to the timer reset terminal of the monitoring circuit 4.
[0009]
Further, the reset signal 104 that is the output of the monitoring circuit 4 is connected to the reset terminal of the control circuit 1 and the control terminal of the switch circuit 5.
[0010]
Here, the operation of the conventional example shown in FIG. 5 will be described. The control circuit 1 is provided with a routine for performing a regular write operation to the monitoring circuit 4 to which an address is assigned in the program.
[0011]
On the other hand, the monitoring circuit 4 measures the time with an internal timer circuit and outputs a reset signal 104 when a certain time is reached, and measures the timer circuit when the timer reset terminal of the monitoring circuit 4 becomes “active”. To reset the time.
[0012]
If the control circuit 1 is operating normally, write processing to the monitoring circuit 4 is performed periodically.
[0013]
Specifically, an address signal 101 and a data signal (not shown) allocated from the control circuit 1 to the monitoring circuit 4 are output in synchronization, and the write enable signal 102 becomes “high level”.
[0014]
The address signal 101 is decoded by the address decoder circuit 2 and the chip select signal 103 becomes “high level”, so that the output of the AND circuit 3 becomes “high level”.
[0015]
For this reason, since the timer circuit of the monitoring circuit 4 is reset and the reset signal 104 is not output, the control circuit 1 continues to operate.
[0016]
If the control circuit 1 is operating abnormally, the periodic writing process to the monitoring circuit 4 is not performed.
[0017]
For this reason, the timer circuit of the monitoring circuit 4 is not reset and reaches a certain time, and the reset signal 104 is output.
[0018]
When the reset signal 104 is output, the control circuit 1 is reset and the abnormal operation is forcibly terminated, the switch circuit 5 is turned “off”, and the connection with the data bus 100 is cut off.
[0019]
As a result, it is possible to suppress adverse effects on external devices even when a failure occurs in the control device.
[0020]
[Problems to be solved by the invention]
However, in the conventional example shown in FIG. 5, the timer reset operation of the monitoring circuit 4 is performed by a write operation to a specific address. For this reason, if the clock of the control circuit 1 is stopped during the write operation, the output of the AND circuit 3 is fixed to “high level”, and the timer circuit of the monitoring circuit 4 remains reset. The monitoring circuit 4 does not function.
[0021]
In addition, even when an abnormal operation such as writing to all addresses occurs, the timer circuit of the monitoring circuit 4 is reset, so that the monitoring circuit 4 does not function.
[0022]
Further, in recent control circuits 1, there are many MPUs (MicroProcessor Units) incorporating peripheral circuits such as memory circuits and I / O circuits, and the address decoder circuit 3 may be unnecessary. In this case, the monitoring circuit 4 Therefore, it is necessary to provide the address decoder circuit 3 and the like, and the number of circuit parts increases, leading to an increase in cost.
[0023]
Further, there is a problem that the control circuit 1 has no method for confirming whether the monitoring circuit 4 is operating normally.
Therefore, the problem to be solved by the present invention is to realize a control device having a simple circuit configuration and capable of confirming an abnormal operation of the monitoring circuit itself.
[0024]
[Means for Solving the Problems]
In order to achieve such a problem, in the first aspect of the present invention,
In a control device that monitors abnormal operation of a control circuit,
A control circuit that reads a target value signal and outputs a set value signal having the same value as the target value signal;
The target value signal is output to the control circuit, and when the target value signal and the set value signal match, the measurement time is reset and the value of the target value signal is changed. And a monitoring circuit that outputs a reset signal to the control circuit when a predetermined time is reached.
[0025]
In order to achieve such a problem, in the second aspect of the present invention,
In the first of the present invention,
A coincidence detection circuit for detecting a coincidence of values between the target value signal and the set value signal;
A target value setting circuit that outputs the target value signal to the control circuit and changes the value of the target value signal based on the output signal of the coincidence detection circuit;
A timer circuit that measures time and outputs the reset signal when the measurement time reaches a certain time and resets the measurement time by an output signal of the coincidence detection circuit is characterized in that .
[0026]
In order to achieve such a problem, in the third aspect of the present invention,
In the first and second aspects of the present invention,
The control circuit monitors a periodic change in the target value signal from the monitoring circuit to determine abnormality of the monitoring circuit.
[0027]
In order to achieve such a problem, in the fourth aspect of the present invention,
In the first to third aspects of the present invention,
The set value signal and the target value signal are 1-bit signals.
[0028]
In order to achieve such a problem, in the fifth aspect of the present invention,
In the fourth of the present invention,
The set value signal and the target value signal are exchanged through an input / output port of the control circuit.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a control apparatus according to the present invention.
[0030]
In FIG. 1, 5 and 100 are assigned the same reference numerals as in FIG. 5, 1a is a control circuit, 4a is a monitoring circuit, 104a is a reset signal, 105 is a set value signal, and 106 is a target value signal.
[0031]
The data bus 100 is connected to the control circuit 1a via the switch circuit 5, the set value signal 105 from the control circuit 1 is connected to the input terminal of the monitoring circuit 4a, and the target value signal 106 from the monitoring circuit 4a is the control circuit 1a. Connected to the input terminal.
[0032]
The reset signal 104a, which is the output of the monitoring circuit 4a, is connected to the reset terminal of the control circuit 1a and the control terminal of the switch circuit 5, respectively.
[0033]
Here, the operation of the embodiment shown in FIG. 1 will be described. The control circuit 1 a provides a routine for periodically reading the target value signal 106 in the program and outputting the set value signal 105 having the same value as the target value signal 106.
[0034]
On the other hand, the monitoring circuit 4a measures the time with a timer circuit provided therein, and outputs a reset signal 104a when a predetermined time is reached, and monitors when the set value signal 105 and the target value signal 106 match. The timer circuit in the circuit 4a is reset and the value of the target value signal 106 is changed.
[0035]
If the control circuit 1a is operating normally, the target value signal 106 is periodically read, and a signal having the same value as the target value signal 106 is output to the monitoring circuit 4a as the set value signal 105.
[0036]
The monitoring circuit 4a compares the set value signal 105 input from the control circuit 1a with the target value signal 106, and when the values match, the timer circuit in the monitoring circuit 4a is reset and the value of the target value signal 106 is set. To change.
[0037]
For this reason, since the measurement time of the timer circuit in the monitoring circuit 4a does not reach a certain time, the reset signal 104a is not output.
[0038]
If the control circuit 1a operates abnormally, the target value signal 106 is periodically read, and the operation of outputting a signal having the same value as the target value signal 106 as the set value signal 105 is not performed.
[0039]
For this reason, the set value signal 105 and the target value signal 106 do not coincide with each other, the timer circuit in the monitoring circuit 4a continues to operate and reaches a certain time, and the reset signal 104a is output.
[0040]
When the reset signal 104a is output, the control circuit 1a is reset and its abnormal operation is forcibly terminated, the switch circuit 5 is turned off, and the connection with the data bus 100 is cut off.
[0041]
On the control circuit 1a side, if the monitoring circuit 4a operates normally, the target value signal 106 changes after a predetermined time since the control circuit 1a changes the value of the set value signal 105. However, the monitoring circuit 4a If the operation is abnormal, the target value signal 106 does not change.
[0042]
That is, on the control circuit 1a side, when there is no periodic change in the target value signal 106 of the monitoring circuit 4a, it can be determined that the monitoring circuit 4a is abnormal.
[0043]
Here, the embodiment shown in FIG. 1 will be described in detail with reference to FIGS. FIG. 2 is a configuration block diagram showing a specific example of the monitoring circuit 4a shown in FIG. 1, and FIGS. 3 and 4 are timing diagrams for explaining the operation of the monitoring circuit 4a in normal and abnormal states.
[0044]
2, 104a, 105 and 106 are assigned the same reference numerals as in FIG. 1, 6 is a coincidence detection circuit, 7 is a target value setting circuit, and 8 is a timer circuit.
[0045]
The set value signal 105 is connected to one input terminal of the coincidence detection circuit 6, and the output of the coincidence detection circuit 6 is connected to the control input terminal of the target value setting circuit 7 and the timer reset terminal of the timer circuit 8.
[0046]
The output of the target value setting circuit 7 is output as a target value signal 106 and is connected to the other input terminal of the coincidence detection circuit 6. The timer circuit 8 outputs a reset signal 104a.
[0047]
3 and 4, (a) is the target value signal 106, (b) is the set value signal 105, (c) is the output signal of the coincidence detection circuit 6, (d) the measurement time of the timer circuit 8, (e ) Is a reset signal 104a.
[0048]
For example, consider a case where the set value signal 105 and the target value signal 106 are “1 bit” signals and the control circuit 1a operates normally.
[0049]
The target value setting circuit 7 changes (a) the target value signal 106 from “1” to “0” at the timing indicated by “A” in FIG. Since the control circuit 1a is operating normally, this change is read, and (b) the set value signal 105 is changed from “1” to “0” at the timing indicated by “B” in FIG.
[0050]
At this time, since “1” is input to both input terminals of the coincidence detection circuit 6, (c) the output of the coincidence detection circuit 6 becomes “high level”. Therefore, (d) the measurement time of the timer circuit 8 is reset at the rising edge of the output signal of the (c) coincidence detection circuit 6 and becomes “0” as indicated by “c” in FIG.
[0051]
Further, (d) since the measurement time in the timer circuit 8 does not reach a certain time, (e) the reset signal 104a is not output.
[0052]
Further, the target value setting circuit 7 changes the target value signal 106 from “0” to “1” at the timing indicated by “e” in FIG. 3 after the time indicated by “d” in FIG. 3 elapses.
[0053]
As described above, the control circuit 1a changes (b) the set value signal 105 from “0” to “1” at the timing indicated by “f” in FIG. 3, and (c) at the rising edge of the output signal of the coincidence detection circuit 6. (D) The measurement time of the timer circuit 8 is reset.
[0054]
That is, if the control circuit 1a is operating normally, (b) the set value signal 105 changes following (a) the change in the target value signal 106, and (d) the timer circuit 8 continues to reset the measurement time. Since the measurement time does not reach a certain time, (e) the reset signal 104a is not output.
[0055]
On the other hand, consider the case where the control circuit 1a operates abnormally. If a failure occurs in the control circuit 1a at the time of "b" in FIG. 4, the target value setting circuit 7 changes the target value signal 106 from "0" to "1" at the timing of "b" in FIG. Even if it is changed to "(b)", the set value signal 105 remains "0" because it cannot follow the change.
[0056]
For this reason, (c) the output of the coincidence detection circuit 6 remains “low level”, and (d) the measurement time of the timer circuit 8 cannot be reset.
[0057]
Accordingly, as shown by “c” in FIG. 4, (d) the measurement time of the timer circuit 8 increases and reaches a certain time indicated by “d” in FIG. 4, and at the timing indicated by “e” in FIG. A reset signal 104a is output.
[0058]
When the reset signal 104a is output, the control circuit 1a is reset and its abnormal operation is forcibly terminated, the switch circuit 5 is turned off, and the connection with the data bus 100 is cut off.
[0059]
Similarly to the above, when there is no periodic change in the target value signal 106, the control circuit 1a can determine that the monitoring circuit 4a is abnormal.
[0060]
As a result, the timer circuit 8 of the monitoring circuit 4a measures the time and outputs a reset signal 104a when a predetermined time is reached. When the set value signal 105 and the target value signal 106 match, the timer circuit 8 is turned off. By resetting and changing the value of the target value signal 106, it is possible to detect and reset the abnormal operation of the control circuit 1a without using a circuit configuration such as an address decoder circuit.
[0061]
In addition, by monitoring the change in the target value signal 106 on the control circuit 1a side, it becomes possible to confirm the abnormal operation of the monitoring circuit 4a itself.
[0062]
Further, since the timer reset operation of the monitoring circuit 4a is not a write operation to a specific address, the problem as in the conventional example does not occur.
[0063]
In particular, since the control circuit 1a must cause the value of the set value signal 105 to follow the value of the target value signal 106, the reset signal 104a is output even if the control circuit 1a falls into a fixed state. Will be.
[0064]
When the set value signal 105 and the target value signal 106 are “1 bit” signals, data can be easily exchanged with the monitoring circuit 4a by using the output port and input port of the control circuit 1a. .
[0065]
This is particularly effective when the monitoring circuit 4a is used in the control circuit 1a that has few usable input / output ports.
[0066]
Of course, the set value signal 105 and the target value signal 106 may be “several bits” signals instead of “1 bit” signals.
[0067]
In the description of FIGS. 3 and 4, the target value setting circuit 7 changes the value of the target value signal 106 after a predetermined time has elapsed. However, the timing of the change may be arbitrary, for example, the output signal of the coincidence detection circuit 6 The value of the target value signal 106 may be changed at the rising edge.
[0068]
In the description of FIG. 4, the output of the reset signal 104a is illustrated as a negative logic output, but may be a positive logic output.
[0069]
【The invention's effect】
As is apparent from the above description, the present invention has the following effects.
When the timer circuit of the monitoring circuit measures the time and reaches a certain time, a reset signal is output, and when the set value signal and the target value signal match, the timer circuit is reset and the value of the target value signal is set. By changing the value and monitoring the periodic change of the target value signal on the control circuit side, it is possible to realize a control device having a simple circuit configuration and capable of confirming an operation abnormality of the monitoring circuit itself.
[Brief description of the drawings]
FIG. 1 is a configuration block diagram showing an embodiment of a control device according to the present invention.
FIG. 2 is a block diagram showing a specific example of a monitoring circuit 4a.
FIG. 3 is a timing chart for explaining the normal operation of the monitoring circuit 4a.
FIG. 4 is a timing chart for explaining the operation when the monitoring circuit 4a is abnormal.
FIG. 5 is a block diagram showing a conventional example of a conventional control device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,1a Control circuit 2 Address decoder circuit 3 AND circuit 4, 4a Monitoring circuit 5 Switch circuit 6 Match detection circuit 7 Target value setting circuit 8 Timer circuit 100 Data bus 101 Address signal 102 Write enable signal 103 Chip select signal 104, 104a Reset signal 105 Set value signal 106 Target value signal

Claims (5)

In a control device that monitors abnormal operation of a control circuit,
A control circuit that reads a target value signal and outputs a set value signal having the same value as the target value signal;
The target value signal is output to the control circuit, and when the target value signal and the set value signal match, the measurement time is reset and the value of the target value signal is changed. A control device comprising: a monitoring circuit that outputs a reset signal to the control circuit when a predetermined time is reached. A coincidence detection circuit for detecting a coincidence of values between the target value signal and the set value signal;
A target value setting circuit that outputs the target value signal to the control circuit and changes the value of the target value signal based on the output signal of the coincidence detection circuit;
A timer circuit that measures time and outputs the reset signal when the measurement time reaches a certain time, and resets the measurement time by an output signal of the coincidence detection circuit. The control device according to claim 1. 3. The control device according to claim 1, wherein the control circuit monitors a periodic change of the target value signal from the monitoring circuit to determine an abnormality of the monitoring circuit. . 4. The control device according to claim 1, wherein the set value signal and the target value signal are 1-bit signals. 5. The control device according to claim 4, wherein the set value signal and the target value signal are exchanged through an input / output port of the control circuit.

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