JP2002073375A - Software operation monitoring method in system that contains microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a software operation monitoring method to detect an incorrect write memory operation due to software defect in a system that contains a microcomputer. SOLUTION: The monitoring of software operation is made by posting the occurrence of incorrect write operation in the address range specified freely to the microcomputer with an interruption and logging the incorrect write locations in a program.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for improving reliability in a system or an electronic device having a microcomputer.

[0002]

2. Description of the Related Art In a system having a conventional microcomputer, a WDT (Watch) which detects a runaway of a CPU by itself and automatically resets the CPU.
(DogTimer) is known to increase reliability.

[0003]

The above-mentioned prior art includes the following:
It has the following disadvantages.

[0004] (1) If there is a defect in software incorporated in the microcomputer system and there is a defect that the data area on the memory is illegally rewritten,
Although normal operation of the system cannot be guaranteed, the CPU does not run away, and the WDT does not operate at this time.

(2) When the WDT is activated, the CP is automatically
Since U is reset, no trace of software failure remains, and it is difficult to find the cause. An object of the present invention is to solve the above problems (1) and (2).

[0006]

The present invention relates to the above (1).
In order to solve the problem (2), the following is performed. First, regarding the above problem (1), in order to detect unauthorized writing to an arbitrary address, an address range (upper limit value, lower limit value) to be monitored is set in a buffer, and the contents are operated by a microcomputer. The occurrence of writing to the address range is detected by comparing with the address information to be output. Further, when a write operation to the address range is intentional in an application program, by outputting this information, an illegal write operation can be selected.

Second, in order to solve the above problem (2), a means for generating an interrupt to the CPU when an illegal write operation is detected is provided, and a program started when the interrupt is generated is provided. In this program processing, the address of the instruction when the above phenomenon occurs is logged.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. In FIG. 1, reference numeral 10 denotes a microcomputer which outputs information for specifying that this operation is a process intentionally performed when a write operation to an arbitrary address range occurs.
It has an O port and an interrupt input unit for receiving this notification when an illegal write operation is detected. Also, 20
Is an address decoding unit, which is a microcomputer 10
Is a circuit for setting the address upper limit latch 30, the address lower limit latch 40, and the address comparison result storage unit 80.

Reference numeral 30 denotes an address upper limit latch, which can set data from the microcomputer 10. An address lower limit latch 40 can set data from the microcomputer 10. A digital comparator 50 compares the contents of the address upper limit latch 30 with the contents output from the microcomputer 10 on the address bus, and outputs the result. A digital comparator 60 compares the contents of the address lower limit latch 40 with the contents output by the microcomputer 10 on the address bus, and outputs the result.

Reference numeral 70 denotes an address information comparison result determination circuit, which outputs a pulse when the content output from the microcomputer 10 on the address bus satisfies the following conditions.

Address lower limit value ≦ (value on address bus)
.Ltoreq.address upper limit value 80 detects an illegal write operation based on the comparison result of the address information and information indicating the validity of the write operation.
This is a circuit for notifying to. Here, the notification to the microcomputer 10 is an interruption by a level trigger.

FIG. 2 shows an operation procedure of an application program when this embodiment is used. As shown in FIG. 2, when the application program is divided into a plurality of modules A, B, C, etc., the processing 201 of the module B
When data is illegally written into a memory area used by the microcomputer, an interrupt at the time of occurrence of illegal writing is generated in the microcomputer by the hardware configuration shown in FIG.

When this interrupt occurs, as shown in FIG. 3, in the interrupt processing module, the return address of the process 201 of the module B is logged (step 301 in FIG. 3), and then the occurrence of the interrupt is cleared. (Step 302 in FIG. 3). As described above, since the return address of the process 201 of the module B is logged, it is possible to specify an illegal portion of the program.

On the other hand, the writing is performed in the same address range as that of the module A, but no interruption occurs because the validity of the writing is set in the process 103. With the above operation, an illegal write operation can be detected, and the operation of the software can be monitored.

[0015]

As described above, according to the present invention,
In a system having a microcomputer, an illegal write operation due to a defect in software can be detected, which can be used as a tool in software debugging work, and the reliability of the entire system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a flowchart showing an operation procedure of one embodiment of the present invention.

FIG. 3 is a flowchart showing an interrupt procedure according to an embodiment of the present invention.

[Explanation of symbols]

10: microcomputer, 20: address decode circuit, 30 and 40: latch circuit for storing address information, 50 and 60: digital comparator, 70: combination circuit for judging the comparison result of address information, 80: illegal writing occurs A sequential circuit that holds the information when it is done.

Claims (2)

[Claims] In a system having a microcomputer, a latch for address information upper limit value, a latch for address information lower limit value, address information comparing means, means for designating validity / invalidity of the comparison result, and operation Software having a program for collecting status information, wherein when a required address range is illegally accessed, an interrupt is generated to notify the microcomputer and the operating status information at this time is collected. Operation monitoring method. 2. The software operation monitoring method according to claim 1, wherein the latch for the upper limit value of the address information, the latch for the lower limit value of the address information, and means for designating validity / invalidity of the address information comparison result. A software operation monitoring method, wherein information is set from a microcomputer.