JPH11259340A - Reactivation control circuit for computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reactivation control circuit for computer with which a transient malfunction is distinguished from a permanent fault and reactivation is performed corresponding to conditions. SOLUTION: When a cyclic reset command from a CPU 1 is stopped, an overflow signal OVF is outputted from a watchdog timer 11, and an abnormality detecting pulse signal FDP is generated by a monostable circuit 12. The abnormality detecting pulse signal FDP is applied through an output part 18 to the CPU 1 as a reset signal RST, and this CPU 1 is reactivated from a prescribed state. Besides, the abnormality detecting pulse signal FDP is counted by a counter 13. When the overflow of the watchdog timer 11 frequently occurs and reaches a set value V17 within the period specified by a cycle timer 14, a decision signal S16 of a comparator part 16 is turned to 'H', a flip-flop 18a is set and a halt signal HLT is outputted. Then, the CPU 1 is forcedly stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a restart control circuit for detecting a malfunction of a computer and starting the computer from a predetermined state.

[0002]

2. Description of the Related Art As a method of detecting a malfunction such as runaway of a computer and restarting the computer, there is a method using a so-called watch dog timer (hereinafter referred to as "WDT"). FIG. 2 is a schematic configuration diagram of a computer provided with a conventional WDT. The computer includes a central processing unit (hereinafter, referred to as a “CPU”) 1, a memory 2, and various input / output devices 3. The memory 2 includes a program unit 2a storing the control processing contents of the computer,
Data section 2b in which data used in control processing is stored
It is composed of The CPU 1, the memory 2, and the input / output device 3 are connected by a common bus 4, and the CPU 1 sequentially reads programs stored in the program unit 2 a via the common bus 4 to perform control processing. I have.

[0005] The common bus 4 is connected to a WDT 5. The WDT 5 counts, for example, a clock signal of a clock signal line (not shown) in the common bus 4 and outputs an overflow signal OVF when the clock signal reaches a value corresponding to a preset time T1. WDT5
Has a function of resetting its count value to 0 and starting counting again when a reset command is received from the CPU 1 via the common bus 4. WDT
The output side of 5 is connected to the input side of a monostable multivibrator (hereinafter referred to as “monostable circuit”) 6. The monostable circuit 6 outputs a reset signal RST having a constant pulse width in response to a rise of the input overflow signal OVF. Then, the reset signal RST
Is supplied to the reset terminal R of the CPU 1. In such a computer, a reset command for periodically resetting the WDT 5 is output within a certain time T2 (where T2 <T1) during a control processing program stored in the program unit 2a of the memory 2. An instruction to perform the operation is pre-installed.

Therefore, while the CPU 1 is performing a processing operation according to a normal program, the WDT 5 is reset before the count value of the WDT 5 overflows, and the overflow signal OVF is not output.
However, for example, due to noise in the common bus 4 or the like,
When an abnormality occurs in the program control, normal processing is not performed, and a reset command for the WDT 5 is not output. Therefore, the count value of WDT5 overflows, and an overflow signal OVF is output. When the overflow signal OVF is supplied to the monostable circuit 6, the monostable circuit 6 outputs a reset signal RST having a fixed pulse width to the CPU 1. As a result, the CPU 1 is reset, and restarts the process from, for example, address 0. When the reset command is output again due to the restart of the processing of the CPU 1, the WDT 5 is reset and the overflow signal OVF is output.
Is stopped. Thus, with WDT5,
The CPU 1 can be automatically restarted without stopping the operation of the CPU 1 for a transient abnormality due to noise or the like.

[0005]

However, the conventional computer has the following problems. If, for example, there is an error in the processing program instead of a transient error due to noise or the like, the program runs away every time the processing proceeds to the error location after restarting, and the CPU 1 is reset by the WDT 5. become. Since such a state cannot be detected from the outside, there is a problem that the state is left unnoticed without being noticed.

On the other hand, in order to prevent a permanent failure from being overlooked due to repetition of reset and restart, WDT5
Is connected to the halt terminal H of the CPU 1 or to the reset terminal R as shown by a broken line in FIG. In this method, when the WDT 5 overflows, the CPU 1 is stopped by the overflow signal OVF, and the overflow signal OVF remains output, so that the stop of the CPU 1 can be easily detected from the outside. However, in such a method,
Even in the case of a transient error due to noise or the like, there has been a problem that the CPU 1 is stopped and a human must intervene to restart the computer. The present invention solves the problem of the prior art, and in the case of a transient error, automatically restarts the computer and stops the operation when it is determined to be a permanent failure. It provides a start-up control circuit.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a restart control circuit for a computer which detects when a signal to be periodically output from a CPU is interrupted or when an abnormality is detected from the CPU. A pulse generation means for generating an abnormality detection pulse signal when a signal indicating detection is given, and counting the number of the abnormality detection pulse signals generated by the pulse generation means during the period at regular intervals. Counting means, a preset setting value, a comparing means for comparing the count value counted by the counting means, and a comparing / comparing means, wherein it is determined that the count value is smaller than the set value. While you are
A first control signal for forcibly restarting the CPU from a predetermined state based on the abnormality detection pulse signal is output. When the count value is determined to be equal to or greater than the set value, the CPU is forcibly restarted. Control signal output means for outputting a second control signal for stopping the operation.

According to the present invention, since the restart control circuit of the computer is configured as described above, the following operation is performed. For example, when the signal periodically output from the CPU is interrupted, the pulse generation unit outputs an abnormality detection pulse signal. The abnormality detection pulse signal is counted by the counting means, and the CPU is forcibly restarted from a predetermined state based on the abnormality detection pulse signal while the count number within a certain period does not reach a preset number. A first control signal is output from the control signal output means. When the count reaches the set value, the control signal output means outputs a second control signal for forcibly stopping the CPU.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram of a computer showing a first embodiment of the present invention. Elements common to those in FIG. ing. This computer includes a CPU 1, a memory 2, and various input / output devices 3, as in FIG. The memory 2 includes a program section 2a in which the contents of control processing of the computer are stored, and a data section 2b in which data and the like used in the control processing are stored.
The CPU 1, the memory 2, and the input / output device 3 are connected to a common bus 4
Via the common bus 4 and the CPU 1
Are configured to sequentially read out the programs stored in the program section 2a and perform control processing.

A restart control circuit 10 is connected to the common bus 4.
Is connected. The restart control circuit 10 includes pulse generation means (for example, the WDT 11 and the monostable circuit 12), and the WDT 11 is connected to the common bus 4. The WDT 11 is, for example, the CPU 1 within the time interval T2.
When a signal such as a reset command to be periodically output from the CPU is interrupted, an abnormality is detected. WDT
A counter 11 counts a clock signal of a clock signal line (not shown) on the common bus 4 and outputs an overflow signal OVF when a value corresponding to a preset time T1 (where T1> T2) is reached. It has become. Further, when receiving a reset command from the CPU 1 via the common bus 4, the WDT 11 has a function of resetting its count value to 0 and restarting counting.

The output side of the WDT 11 is connected to the input side of the monostable circuit 12. The monostable circuit 12 outputs the abnormality detection pulse signal FD having a constant pulse width (for example, 1 μs) by the rise of the supplied overflow signal OVF.
P is output. The output side of the monostable circuit 12
It is connected to a clock terminal C of a counting means (for example, a counter) 13. The counter 13 has a clock terminal C
Counting the number of abnormality detection pulse signals FDP given to
The counting result is output as a count value C13, and when a reset signal is given to the reset terminal R, the count value C13 is reset to zero. For example, the output side of a 24-hour period timer 14 is connected to the reset terminal R of the counter 13 via a 2-input OR gate (hereinafter referred to as “OR”) 15 for a fixed period (in this case, 24 hours). A reset pulse signal is provided once each time.

The output side of the counter 13 is connected to one input side of a comparing means (for example, a comparing section) 16. A count setting unit 17 is connected to the other input side of the comparison unit 16, and a preset value V set in the count setting unit 17 is set in advance.
17 are provided. When the count value C13 provided from the counter 13 is smaller than the set value V17 provided from the number-of-times setting unit 17, the comparison unit 16 outputs the determination signal S16 at the level “L”, and outputs the count signal C13. When the voltage becomes equal to or higher than V17, the determination signal S16 is set to level "H" and output. An output side of the comparison unit 16 is a set terminal of a FF 18b in a control signal output unit (for example, an output unit) 18 including a set / reset type flip-flop (hereinafter, referred to as “FF”) 18a and a two-input OR 18b. Connected to S.

An external terminal 19 is connected to the reset terminal R of the FF 18a, and an external reset signal ERS is supplied from the external terminal 19. F
F18a outputs "H" from the output terminal Q when the "H" signal is given to the set terminal S, and outputs the reset terminal R
Is supplied with an "H" signal, the output terminal Q outputs "L". Output terminal Q of FF 18a
Is connected to the halt terminal H of the CPU 1, and a halt signal HLT for forcibly stopping the CPU 1 is output. An abnormality detection pulse signal FDP from the monostable circuit 12 and an external reset signal ERS from an external terminal 19 are supplied to the input side of the OR 18b. The output side of the OR 18b is connected to the reset terminal R of the CPU 1, and outputs a reset signal RST for restarting the CPU 1 from address 0, for example.

Next, the operation will be described. For example, external terminal 1
9, the counter 13 and the FF 18a are reset and the CP 13
In U1, the operation from the initial state is started. The programs stored in the program section 2a of the memory 2 are sequentially read from the address 0 and executed by the CPU 1. A command for outputting a reset command for periodically resetting the WDT 11 within a predetermined time T2 is incorporated in the control processing program stored in the program unit 2a. Therefore, according to the normal program, C
While the PU1 is performing the processing operation, the WDT11 is reset before the count value of the WDT11 overflows, and the overflow signal OVF is not output.

Here, it is assumed that an abnormality occurs in program control due to, for example, noise in the common bus 4. Due to the abnormality of the program control, the predetermined processing is not performed, and the reset command for the WDT 11 is not output. Therefore, the count value of the WDT 11 overflows, and an overflow signal OVF is output. The overflow signal OVF is supplied to the monostable circuit 12, and the monostable circuit 12 outputs an abnormality detection pulse signal FDP having a fixed pulse width, and supplies the same to the counter 13. Then, the count value C13 of the counter 13 is counted up to 1. Since the abnormality detection pulse signal FDP is also supplied to the reset terminal R of the CPU 1 via the OR 18b at the same time, the control of the CPU 1 is forcibly moved to the address 0, and the restart processing from the address 0 is started. WD
If the cause of the overflow of T11 is a transient cause such as noise, the overflow of the WDT11 does not occur continuously, and the count value C13 of the counter 13 continuously increases rapidly. Never.
When a pulse signal for resetting, for example, every 24 hours is output from the periodic timer 14, the counter 13
Is reset to 0.

On the other hand, if the cause of the overflow of the WDT 11 is a permanent cause such as a program error,
The overflow of the WDT 11 occurs every time the location of the program error is executed. Each time the WDT 11 overflows, the count value C13
Are sequentially counted up, and a restart process by the CPU 1 is performed. The count value C1 of the counter 13
When 3 is counted up and reaches a set value V17 preset in the number-of-times setting section 17, the determination signal S16 output from the comparing section 16 becomes "H". Thereby, FF
The halt signal HLT output from 18a becomes "H". The halt signal HLT is supplied to the halt terminal H of the CPU 1, and the CPU 1 is forcibly stopped. CPU
1 is maintained in the stopped state until the external reset signal ERS is supplied from the external terminal 19.

As described above, the computer according to the first embodiment includes a counter 13 for counting the number of overflows detected by the WDT 11 within a certain period set by the period timer 14, and a count value C13 of the counter 13.
A comparison unit 16 that compares the value of
And the halt signal HLT based on the determination result of the comparator 16
Alternatively, it has an output unit 18 that outputs a reset signal RST to the CPU 1. As a result, the CPU 1 can be automatically restarted in the case of a transient malfunction, and can be forcibly stopped in the case of a permanent failure, so that recovery processing according to the failure situation can be performed. It has the advantage that it can be done.

Second Embodiment FIG. 3 is a block diagram of a computer showing a second embodiment of the present invention, and the same reference numerals are given to the same components as those in FIG. This computer has a configuration in which a restart control circuit 20 corresponding to a parity error in the memory 2 or the like is added to the computer of FIG. The restart control circuit 20 has a pulse generation unit (for example, a parity error detection unit) 21 connected to the common bus 4. The parity error detector 21 detects that an error signal has been output to a parity signal line (not shown) in the common bus 4 and outputs a parity error signal PEP having a fixed pulse width (for example, 1 μs). is there. The output signal of the parity error detecting section 21 is provided to the interrupt terminal I of the CPU 1 as an interrupt signal INT and also to the clock terminal C of the counting means (for example, a counter) 22.

The counter 22 counts the number of parity error signals PEP supplied to the clock terminal C, outputs the count result as a count value C22, and when a reset signal is supplied to the reset terminal R, the count value C22 is reset to 0. The output terminal of the OR 15 of the restart control circuit 10 is connected to the reset terminal R of the counter 22. The output side of the counter 22 is connected to one input side of a comparison means (for example, a comparison unit) 23. On the other input side of the comparison unit 23,
The number-of-times setting unit 24 is connected, and a preset value V24 is given to the number-of-times setting unit 24. When the count value C22 given from the counter 22 is smaller than the set value V24 given from the number-of-times setting unit 24, the comparing unit 23 sets the determination signal S23 to "L".
When the count value C22 becomes equal to or greater than the set value V24, the determination signal S23 is set to the level "H" and output. The output side of the comparison unit 23 is connected to a set terminal S of a control signal output unit (for example, a set / reset type FF) 25.

An external terminal 19 is connected to the reset terminal R of the FF 25, and an external reset signal ERS is supplied from the external terminal 19. FF
A halt signal HLT for forcibly stopping the CPU 1 is output from the 25 output terminals Q. The output terminal Q of the FF 25 and the output terminal Q of the FF 18a of the restart control circuit 10 are connected to the input side of a two-input OR 26, and the two halt signals H
The logical sum of LT is calculated and applied to the halt terminal H of the CPU 1. Other configurations are the same as those of the computer in FIG. The operation of the restart control circuit 10 in such a computer is the same as the operation of the restart control circuit 10 described in the first embodiment. The operation of the restart control circuit 20 is almost the same as the operation of the restart control circuit 10.

That is, when the parity error detection section 21 detects a parity error, the count value C
22 is incremented by one. The output signal of the parity error detection unit 21 is a C signal as an interrupt signal INT.
It is provided to the interrupt terminal I of PU1. This allows the CPU
In 1, control is forcibly transferred to an interrupt processing program corresponding to the interrupt signal INT, and a predetermined interrupt processing is performed. Then, after the end of the interrupt processing, the CPU 1 returns to the normal processing operation. The interrupt process due to such a parity error is performed until the count value C22 of the counter 22 reaches a set value V24 preset in the number setting unit 24. Then, when the count value C22 reaches the set value V24, it is determined that a permanent failure has occurred in the memory 2 or the like, and the determination signal S23 of the comparison unit 23 becomes “H”. Thereby, F
The halt signal HLT output from F25 becomes “H”. The halt signal HLT is supplied to the halt terminal H of the CPU 1 via the OR 26, and the CPU 1 is forcibly stopped. As described above, the computer of the second embodiment has the same advantages as the computer of the first embodiment in FIG.
Further, since there is a restart control circuit 20 for detecting a parity error and performing restart control, there is an advantage that appropriate restart control can be performed even for a parity error.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (d). (A) The period of the period timer 14 and the number-of-times setting unit 17,
The setting of the 24 set values V17, V24, and the like may be performed from the CPU 1 via the common bus 4. This makes it possible to perform appropriate restart control according to the system and processing contents. (B) The pulse width output from the monostable circuit 12 or the like is
It can be set appropriately according to the system. (C) In the computers shown in FIGS. 1 and 3, the computer is constituted by a positive logic circuit that activates the level “H”, but may be constituted by a negative logic circuit that activates the level “L”. (D) The output unit 18 is configured to individually output the halt signal HLT and the reset signal RST. For example, in the case of the CPU 1 having no halt terminal H, the output unit 18 outputs the halt signal HLT and the reset signal RST. The logical sum may be calculated and applied to the reset terminal R of the CPU 1.

[0023]

As described above in detail, according to the present invention, when the signal periodically output from the CPU is interrupted or when a signal indicating an abnormality is detected from the CPU, the abnormality detection pulse signal is output. , A pulse generating means for outputting an abnormal detection pulse signal at regular intervals, and a CP according to the count number of the counting means.
It has a control signal output means for outputting a first control signal for forcibly restarting U from a predetermined state or a second control signal for forcibly stopping the CPU. As a result, there is an effect that a transient malfunction of the computer and a permanent failure can be distinguished from each other and a restart corresponding to each can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a computer according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a computer including a conventional WDT.

FIG. 3 is a configuration diagram of a computer according to a second embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 CPU 2 memory 4 common bus 10, 20 restart control circuit 11 WDT (watch dog timer) 12 monostable circuit 13, 22 counter 14 period timer 15, 18b, 26 OR (logical sum gate) 16, 23 comparator 17, 24 number setting section 18 output section 18a, 25 FF (flip-flop)

Claims (1)

[Claims] 1. A pulse for generating an abnormality detection pulse signal when a signal to be periodically output from a central processing unit is interrupted or when a signal indicating that an abnormality is detected is given from the central processing unit. Generating means, at regular intervals, a counting means for counting the number of the abnormality detection pulse signals generated by the pulse generating means during the period, a preset set value, and counting by the counting means. Comparing means for comparing the count value with the count value; while the comparing and comparing means determines that the count value is smaller than the set value, forcibly causes the central processing unit based on the abnormality detection pulse signal. Outputting a first control signal for restarting from a predetermined state;
Control signal output means for outputting a second control signal for forcibly stopping the central processing unit when the count value is determined to be equal to or greater than the set value. Restart control circuit.