JPS6349855A - Detecting device for interruption cycle abnormality of cpu - Google Patents

Abstract

PURPOSE:To surely detect the interruption cycle abnormality by using a counter which counts clock pulses to count the interruption cycles produced by an interruption signal generating circuit. CONSTITUTION:A counter 3 counts clock pulses and is reset by the interruption signal produced from an interruption signal generating circuit 2. A CPU 1 discriminates whether the value obtained before the counter 3 is reset is kept within a normal value range or not by the interruption processing carried out by the interruption signal. The counter 3 shows the value equivalent to a period between a reset mode set by the previous interruption signal and a reset mode of this time. Therefore the CPU 1 can detect occurrence of the cycle abnormality of the interruption signal by discriminating the value of the counter 3. While a priority interruption signal is produced to the CPU 1 in case the count value of the counter 3 reaches a specific level before the counter 3 is reset. Thus the CPU 1 detects immediately a fact that no interruption signal is produced within a fixed period of time in a priority processing mode.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a device for detecting an abnormality in the interrupt cycle in a system including an interrupt signal generation circuit that generates periodic interrupt signals to a CPU.

(b) Summary of the Invention This invention provides a CP comprising a microprocessor etc.
In a system including an interrupt signal generation circuit that generates a periodic interrupt signal to the CPU using U,
This invention relates to a method for detecting an abnormality in which interrupt processing is not performed due to an abnormality in the interrupt processing cycle or an abnormality in an interrupt signal generation circuit, when important processing in a system is processed by periodic interrupts.

(C1 Prior Art) In general, devices that use a microprocessor or the like as a CPU often periodically carry out processes that serve as important functions for the entire device.

However, if the system performs an abnormal operation for some reason, it is possible to configure the system to detect the abnormality and take appropriate action to prevent the system from causing a serious failure. is necessary.

Conventionally, for this purpose, a runaway detection circuit called a watchdog timer has been provided to detect abnormal operation of the system and stop the system.

FIG. 5 is a circuit diagram showing an example thereof, and FIG. 6 is a diagram showing the timing of each part thereof. In FIG. 5, a timer 10 is a presettable down counter, and counts down using clock pulses. This clock pulse generation circuit and timer 10 constitute a so-called watchdog timer. The timer 10 counts down, and when the value reaches O, the output becomes "H" level. When the timer 10 becomes "H" level, a reset signal is input to the CPU.

As shown in FIG. 6, when the value to be preset to the timer 10 is M, if the preset is performed by the program operation within the clock period pl x M time, the output of the timer 10 remains "L". In this way, the output of timer 10 is
It is necessary to repeatedly preset the timer 10 by the operation of the program at intervals within the clock period pl x M time so that the timer 10 does not reach the H'' level. If not, the output of the timer 10 becomes "H" level, and the CPU 1 is reset and stops operating.The watchdog timer disable circuit 12 is a circuit that disables the watchdog timer, and when the signal WDE goes "L" If the output level is the same, no reset signal is generated for the CPU 1 regardless of the output level of the timer 10.

fd) Problems to be Solved by the Invention Incidentally, in a system in which a microprocessor is applied to a digital control device, important functions of the sample system are performed by interrupt processing in most cases.

If the interrupt signal generation circuit for performing this interrupt processing operates abnormally and the cycle becomes abnormal, there is a risk of inducing a serious failure in the system.

However, the above-mentioned abnormal operation detection circuit using the watchdog timer is for detecting program runaway, etc., and is only used to detect failures in the interrupt signal generation circuit, etc., when an interrupt signal is not generated at a predetermined period. This invention solves these conventional problems and improves the reliability of the system by monitoring the interrupt processing cycle. The purpose of the present invention is to provide a periodic abnormality detection device.

(e) Means for Solving Problems The present invention provides a system including a CPU and an interrupt signal generation circuit that generates periodic interrupt signals to the CPU, which counts clock pulses and generates the interrupt signal. A counter is provided that is reset based on an interrupt signal generated from a circuit, and generates a priority interrupt signal to the CPU that takes priority over the interrupt signal when the count value reaches a specific value without being reset. means for determining, in interrupt processing, whether the value of the counter before resetting is within a normal value; and means for detecting that the interrupt signal generation circuit is abnormal, in priority interrupt processing using the priority interrupt signal. It is characterized by the following.

(If configured as described above, the counter counts clock pulses and is reset based on the interrupt signal generated from the interrupt signal generation circuit.

The CPU determines whether or not the value of the counter before being reset is within normal values by interrupt processing using an interrupt signal. The counter represents the value corresponding to the time from when it was reset based on the previous interrupt signal until the current cent.
By determining the value of this counter, the CPU can detect an abnormality in the generation cycle of the interrupt signal. Also,
When the counter reaches a certain value without being reset, C
A priority interrupt signal is generated for the PU. In priority interrupt processing, the CPU immediately detects that an interrupt signal has not been generated within a certain period of time.

(g) Embodiment FIG. 1 shows a circuit diagram of a CPU interrupt cycle abnormality detection device according to an embodiment of the present invention, and FIG. 2 shows the timing of each part thereof. Moreover, FIG. 3 is a flowchart showing the processing procedure of the CPU.

The interrupt signal generation circuit 2 generates an interrupt timing signal (A) at a predetermined period. The flip-flop FFa is a circuit that holds the interrupt timing signal (A) at -.When the interrupt timing signal (A) is generated, the flip-flop FFa becomes set state.
Generates an interrupt signal (B) to the CPUI. The CPUI performs interrupt processing in response to this interrupt signal (B).

Counter 3 counts clock pulses, and when it overflows, generates a count-a-knob signal (E) to send flip-flop FFb.

Further, the counter 3 is reset by the interrupt timing signal (A).

When the flip-flop F F b is in the set state, CP
Generates a priority interrupt signal (F) to the UI. This priority interrupt signal (F) has priority over the interrupt signal (B), and the CPUI performs priority interrupt processing.

The launch circuit 4 is a circuit that latches count data of the counter 3 in response to an interrupt timing signal (A), and is connected to the data bus. By generating an input signal to the launch circuit 4, the CPU 1 can read its contents.

The latch circuit 5 is provided to generate a reset signal for the flip-flops FFa and FFb, and
U1 sends data to this latch circuit 5 and generates an output latch signal, thereby controlling the flip-flop FF.
a. Reset FFb. Explain the overall operation of the blowing rod.

Interrupt timing signal (A) from interrupt signal generation circuit 2
When is generated, the launch circuit 4 latches the count data of counter 3 = M
-Reset. After that, the counter 3 (D
), the count starts from 0.

The CPUI receives an interrupt signal generated from FFa,
First, FFa and FFb are reset by resetting/setting the bit corresponding to the interrupt reset signal of the launch circuit 5 and generating an output latch signal (FIG. 3, nl).

The data latched in the latch circuit 4 at this time is count data corresponding to the time from when the previous interrupt timing signal was generated until when the current interrupt timing signal was generated. Therefore, the CPU 1 reads the data of the launch circuit 4 in interrupt processing and determines whether the value is a normal interrupt cycle (n2- in Figure 3).
n3). If the value is normal, perform the interrupt processing that should be performed (n4); if the value is not normal, perform the interrupt abnormal processing (n4).
n3-=n5).

Furthermore, as shown in (D), (E), and (F) of Fig. 2, if the interrupt timing signal (A) is not generated even after a certain period of time or after T, the counter 3 will overflow and the count-up will start. Generate signal (E). As a result, a priority interrupt signal is generated to the CPUI, and the CPUI immediately performs interrupt abnormality processing (n5). For example, it can safely stop the system and display an error message.

In the above embodiment, the counter 3 is reset by the interrupt timing signal, but the interrupt reset signal (C)
The counter 3 may be reset by FIG. 4 shows a part of the circuit diagram in that case. In this case, latch circuit 4
The data latched corresponds to the time during which interrupt processing is actually performed from the start of the previous interrupt processing to the start of the current interrupt processing.

Further, in a system in which important system processing is performed by interrupt processing, a more reliable system can be constructed by using it together with a conventional runaway detection circuit using a watchdog timer.

(h1 Effects of the invention As described above, according to this invention, by counting the interrupt period generated from the interrupt signal generation circuit by a counter that counts clock pulses, the interrupt period of 31 Jl is reduced due to failure of the interrupt signal generation circuit. If an abnormality occurs or if an interrupt signal is no longer generated, this can be reliably detected, thereby preventing the risk of inducing a serious failure in the system.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a CPU interrupt cycle abnormality detection device according to an embodiment of the present invention, Fig. 2 is a diagram showing the timing of each part thereof, Fig. 3 is a flowchart showing the processing procedure of the device, and Fig. 4 5 and 6 show another embodiment, and show a circuit corresponding to a part of FIG. 1. FIGS. 5 and 6 are diagrams showing a conventional abnormality detection circuit and the timing of each part thereof. IcPU. 2-interrupt signal generation circuit, 3-counter.

Claims (1)

[Claims] (1) In a system including a CPU and an interrupt signal generation circuit that generates periodic interrupt signals to the CPU, clock pulses are counted and reset based on the interrupt signal generated from the interrupt signal generation circuit. , a counter is provided that generates a priority interrupt signal to the CPU that takes precedence over the interrupt signal when the count value reaches a specific value without being reset, and when the interrupt processing by the interrupt signal is performed, the value of the counter before being reset is normal. An interrupt cycle abnormality detection device for a CPU, comprising means for determining whether or not the values are within a value, and means for detecting that the interrupt signal generation circuit is abnormal through priority interrupt processing using the priority interrupt signal. .