JPH05241907A - Fault detection circuit - Google Patents

Abstract

PURPOSE:To realize a fault detection circuit which enables complete system down in the case of a fault by eliminating incidental malfunction. CONSTITUTION:This fault detection circuit detects a fault by a watchdog timer(WDT) circuit 4' receiving the output of a CPU 1, and the WDT circuit 4' is provided with a gate 5 to receive the output of the CPU 1 at one input/output terminal, monostable multivibrator 6 to receive the output of the gate 5, and low-pass filter(LPF) 7 to receive the output of the monostable multivibrator 6. The output of the LPF 7 is extracted to the outside as a fault detecting output and connected to the other input/output terminal of the gate 5, and the output of the monostable multivibrator 6 is connected to the reset terminal of the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure detection circuit, and more particularly to a device self-failure detection circuit using a CPU.

[0002]

2. Description of the Related Art In a device using a CPU, a watchdog timer circuit (WDT) is used to detect a failure.
Is commonly used.

FIG. 6 is a block diagram showing a fault detection circuit which has been generally used conventionally. In this figure, 1 is a CPU that controls the entire apparatus, 2 is a bus connected to the CPU, 3 is an output port for outputting the data of the CPU 1, and 4 is a WDT composed of a mono-multivibrator.
Circuit.

The WDT circuit 4 is used by the CPU 1 to confirm that a normal loop passes within a fixed time. Then, as shown in FIG. 6, a WDT constituted by a retriggerable mono multivibrator via the output port 3
By arranging the circuit 4 and periodically triggering it by software, an abnormal loop is detected. However, as it is, there is a possibility that the WDT circuit may be activated and go down due to an accidental malfunction due to noise or the like.

[0005]

Therefore, as shown in FIG. 6, a method of resetting the CPU by the output of the WDT circuit can be considered. However, according to this method, in the event of a true failure, the resetting of the CPU will continue forever, and it will not completely go down. Therefore, there is a possibility that the true failure cannot be detected.

The present invention has been made in view of the above problems of the prior art, and an object thereof is to provide a failure detection circuit capable of eliminating accidental malfunction and completely shutting down the system in the event of a failure. It is to be realized.

[0007]

Means for solving the above-mentioned problems is a failure detection circuit for detecting a failure by a watchdog timer circuit which receives an output from a CPU. It is equipped with a gate that receives the output at one input terminal, a mono-multivibrator that receives the output of the gate, and a low-pass filter that receives the output of the mono-multivibrator, and the output of the low-pass filter is output to the outside as a failure detection output. , Is connected to the other input terminal of the gate, and the output of the mono-multivibrator is connected to the reset terminal of the CPU.

[0008]

In the present invention, the CPU is reset by the output of the mono-multivibrator at the time of accidental failure. In the case of an unrecoverable failure, the gate receiving the output of the low-pass filter is closed, the input to the mono-multivibrator is cut off, the failure detection output holds the failure state, and the reset to the CPU is not performed. Therefore,
The system does not go down due to an accidental failure due to noise, etc., and the system is stopped when a true failure occurs.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a configuration diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a configuration diagram showing FIG. 1 in more detail, FIG. 3 is a waveform diagram in normal operation, FIG. 4 is a waveform diagram in case of accidental malfunction, FIG. 5 is a waveform diagram in the case of failure.

In these figures, 1 is a CPU that controls the entire apparatus, 2 is a bus connected to the CPU, 3 is an output port for outputting data from the CPU to the outside via the bus 2, and 4 '. Is a watchdog timer (WDT)
Reference numeral 5 designates an AND gate which receives data from the output port 3 and the output of the WDT circuit 4 ', and 6 designates an AND gate 6
Is a mono multivibrator that receives the output of
A low-pass filter that receives the output of the multi-vibrator 6, 8 is another mono-multivibrator that receives the output of the mono-multivibrator 6, 9 is an inverter with an open collector that receives the output of the mono-multivibrator 8, and 10 is a power-on reset signal For generating a power-on reset circuit, 11 for a power-on reset circuit 10
Open collector inverter that receives the output of D
Is a diode for initializing the capacitor of the low-pass filter 7 when a power-on reset occurs.

The operation of the apparatus of this embodiment thus configured is as follows. The description will be given separately for each case. <Normal operation after power-on reset> When the power of the device is turned on, the output RST of the power-on reset circuit 10 becomes "H" level as shown in FIG.
Is reset. Then, after a certain period of time, a pulse is output to the output PO of the output port 3 by the software of the CPU. At this time, since the "H" level RST signal is applied to the LPF 7 through the diode D, the LP
The output VO of F is also at "H" level. Therefore, the output PO of the output port 3 passes through the gate 5, and the "H" level pulse is also output to the gate output GO. this"
The GO pulse of H "level causes the mono-multivibrator 6 to go to the" H "level. Since the output MO of the mono-multivibrator 6 is at the" L "level immediately after reset, the voltage of the capacitor in the LPF 7 is CR. It descends with a constant, but when CPU1 starts the trigger of PO, M
O becomes "H" level, and the voltage at the VI point also becomes stable at "H" level. Therefore, the fault output VO is "H"
It is a level (normal state).

<Accidental Malfunction> When the CPU 1 goes out of control or enters an error process due to an accidental malfunction, FIG.
As shown in, the CPU 1 outputs the output PO to the WDT circuit 4 '.
To stop. When the PO stops, the mono-multivibrator MO becomes "L" level. With this as a trigger, the reset signal RST bar is activated from the mono / multivibrator 8 and the inverter 9. This allows
CPU1 is reset. Then, after a lapse of time similar to that in the case of the power-on reset, the normal operation is restored. Therefore, the fault output VO is at "H" level (normal state)
It remains.

<Fatal Failure> When an unrecoverable fatal failure occurs, the CPU 1 is reset in the same procedure as in the case of the accidental malfunction. However, the CPU 1 cannot continue normal operation every time it is reset,
The output PO to the WDT circuit 4'is not continuously output.

In the example shown in FIG. 5, a time chart is shown as an example in which the output to the WDT circuit 4'is output only once after reset. The voltage VI is a value obtained by integrating the voltage of the output MO of the mono-multivibrator, and therefore gradually decreases. Then, when the voltage VI becomes equal to or lower than the threshold voltage of the Schmitt trigger circuit 7c,
The fault output VO turns to "L" level (fault state). Then, the gate 5 is turned off and becomes independent of the operation of the CPU 1, and the trigger to the mono-multivibrator 6 is not input. Therefore, the fault output VO is "L"
Holds the level (fault state).

As described above in several cases, the WDT circuit 4'for detecting a failure is provided with a circuit for resetting the CPU 1 for a certain period of time and thereafter prohibiting it. The system does not go down due to an accidental failure due to noise, etc., and the system can be stopped when a true failure occurs. That is, it is possible to realize a failure detection circuit capable of eliminating accidental malfunction and completely shutting down the system in case of failure.

[0016]

As described above in detail with the embodiments, the WDT circuit for detecting a failure resets the CPU for a certain period of time, and a circuit for inhibiting the CPU is added thereafter, so that accidental malfunction is eliminated. However, it is possible to realize a failure detection circuit that can completely bring down the system in the event of a failure.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram showing the configuration of FIG. 1 in detail.

FIG. 3 is a waveform diagram showing an operation in one embodiment of the present invention.

FIG. 4 is a waveform diagram showing an operation in one embodiment of the present invention.

FIG. 5 is a waveform diagram showing an operation in one embodiment of the present invention.

FIG. 6 is a configuration diagram showing a configuration of a conventional device.

[Explanation of symbols]

 1 CPU 2 Bus 3 Output Port 4'WDT Circuit 5 Gate 6 Mono Multivibrator 7 Low Pass Filter

Claims (1)

[Claims] 1. A failure detection circuit for detecting a failure by a watchdog timer (4 ') receiving an output from the CPU (1), wherein the watchdog timer circuit (4') is provided from the CPU (1). A gate (5) that receives an output at one input terminal, a mono-multivibrator (6) that receives the output of the gate (5), and a low-pass filter (7) that receives the output of the mono-multivibrator (6) are provided. , The output of the low-pass filter (7) is taken out as a failure detection output and is connected to the other input terminal of the gate (5), and the output of the mono-multivibrator (6) is the CPU (1).
Failure detection circuit characterized in that it is connected to the reset terminal of.