JPH01200442A - Cpu resetting circuit with protection - Google Patents

Cpu resetting circuit with protection

Info

Publication number
JPH01200442A
JPH01200442A JP63025078A JP2507888A JPH01200442A JP H01200442 A JPH01200442 A JP H01200442A JP 63025078 A JP63025078 A JP 63025078A JP 2507888 A JP2507888 A JP 2507888A JP H01200442 A JPH01200442 A JP H01200442A
Authority
JP
Japan
Prior art keywords
pulse
cpu
abnormality
circuit
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63025078A
Other languages
Japanese (ja)
Inventor
Masumi Takeuchi
竹内　真清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63025078A priority Critical patent/JPH01200442A/en
Publication of JPH01200442A publication Critical patent/JPH01200442A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To prevent the malfunctions due to the noises by resetting a CPU after protecting it in the prescribed frequency when the CPU has abnormality. CONSTITUTION:A CPU normal action pulse is supplied to a pulse cut-off detecting circuit 1 and a CPU abnormality informing pulse is sent to a terminal 102 in case said normal action pulse is not received for a fixed period of time or longer. When an abnormality pulse generating circuit 2 receives the abnormality informing pulse, sends an abnormality detecting pulse having the prescribed fixed time width to a terminal 103. A resetting signal output circuit 3 supplies the CPU abnormality informing pulse via the terminal 102 and at the same time supplies the abnormality detecting pulse via the terminal 103. Then a CPU resetting signal is sent to a terminal 104 when the CPU abnormality pulse is turned on by the prescribed frequency while the abnormality detecting pulse is kept turned on.

Description

【発明の詳細な説明】 （産業上の利用分野〕 本発明はリセット回路の改良に関し、特にＣＰＵ暴走時
のリセット回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a reset circuit, and particularly to a reset circuit when a CPU runs out of control.

（従来の技術） 従来、この種のリセット回路はＣＰＵの動作の異常を検
出すると、即時に回路をリセットするものであった。(Prior Art) Conventionally, this type of reset circuit resets the circuit immediately upon detecting an abnormality in the operation of the CPU.

（発明が解決しようとする課題） 上述し次従来のリセット回路は、ノイズなどによる誤動
作でもリセット状態に入ってしまうと云う欠点がある。(Problems to be Solved by the Invention) The conventional reset circuit described above has a drawback in that it enters a reset state even if it malfunctions due to noise or the like.

本発明の目的は、ＣＰＵの正常動作が一定時間以上にわ
たって確保されないとＣＰＵ異常異常通知パルスを出力
し、さらにＣＰＵ異常通知パルスが出力されたときに、
ある−足時間の幅の異常検知パルスを出力できるように
しておき、県営検知パルスの入力中にＣＰＵ異常通知パ
ルスを連続して予め設定された回数だけ検出するとＣＰ
Ｕリセット信号を出力することにより上記欠点を除去し
、ノイズなどによる誤動作を防ぐことができるようにＳ
成した保護付きＣＰＵすセット回路を提供することにあ
る。An object of the present invention is to output a CPU abnormality notification pulse if normal operation of the CPU is not ensured for a certain period of time or more, and further, when the CPU abnormality notification pulse is output,
If the CPU abnormality notification pulse is continuously detected a preset number of times while the prefectural detection pulse is being input, the CP will be activated.
By outputting the U reset signal, the above drawbacks can be removed and the S
The object of the present invention is to provide a protected CPU set circuit.

（課題を解決するための手段） 本発明による保護付きＣＰＵリセット回路はパルス切断
検出回路と、異常パルス発生回路と、リセット信号出力
回路とを具備して構成したものである。(Means for Solving the Problems) A protected CPU reset circuit according to the present invention includes a pulse cutoff detection circuit, an abnormal pulse generation circuit, and a reset signal output circuit.

パルス切断検出回路は、第１の一定時間以上にわたって
ＣＰＵが正常動作中であることを示す正常動作パルスが
入力されないと、ＣＰＵ異常通知パルスを出力するため
のものである。The pulse disconnection detection circuit outputs a CPU abnormality notification pulse if a normal operation pulse indicating that the CPU is in normal operation is not input for a first predetermined period of time or more.

異常パルス発生回路は、ＣＰＵ異常通知パルスが入力さ
れると第２の一定時間の幅を有する異常検知パルスを出
力するためのものである。　゛リセット信号出力回路は
、ＣＰＵ異常通知パルスと異常検知パルスとを入力し、
異常検知パルスの入力中にＣＰＵ異常通知パルスを連続
して予め決められた回数だけ検出するとＣＰＵＩＪセッ
ト借号を出力するためのものである。The abnormality pulse generation circuit is for outputting an abnormality detection pulse having a width of a second fixed time when the CPU abnormality notification pulse is input.゛The reset signal output circuit inputs the CPU abnormality notification pulse and the abnormality detection pulse,
This is for outputting a CPU IJ set signature when a CPU abnormality notification pulse is continuously detected a predetermined number of times during input of an abnormality detection pulse.

（実施　例） 次に１本発明について図面を参照して説明する。(Example) Next, one embodiment of the present invention will be explained with reference to the drawings.

第１図は１本発明による保護付きＣＰＵリセット回路の
一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of a protected CPU reset circuit according to the present invention.

第１図において、１はパルス切断検出回路、２は異常パ
ルス発生回路、３はリセット信号出力回路である。In FIG. 1, 1 is a pulse cutoff detection circuit, 2 is an abnormal pulse generation circuit, and 3 is a reset signal output circuit.

パルス切断検出回路１には端子１０１を経由してＣＰＵ
正常動作パルスが入力され、予め定められた一定時間（
↑）以上にわたってＣＰＵ正常動作パルスが入力されな
いと、ＣＰＵ異常通知パルスを端子１０２上に出力する
。異常パルス発生回路２は端子１０２を経由してＣＰＵ
異常通知パルスを入力すると、予め定められた一定時間
（ｋ）の幅を有する異常検知パルスを端子１０３上に出
力する。The pulse disconnection detection circuit 1 is connected to the CPU via the terminal 101.
A normal operation pulse is input, and a predetermined period of time (
↑) If the CPU normal operation pulse is not input for the above period, a CPU abnormality notification pulse is outputted to the terminal 102. The abnormal pulse generation circuit 2 is connected to the CPU via the terminal 102.
When an abnormality notification pulse is input, an abnormality detection pulse having a width of a predetermined constant time (k) is outputted onto the terminal 103.

リセット信号出力回路３は端子１０２を経由してＣＰＵ
異常通知パルスを入力するとともに、端子１０３を経由
して異常検知パルスを入力し、異常検知パルスがオンの
ときにＣＰ　Ｕ異常パルスが予め定められた回数（ｎ）
だけオンになると、端子１０４にＣＰＵリセット信号を
出力する。The reset signal output circuit 3 is connected to the CPU via the terminal 102.
In addition to inputting an abnormality notification pulse, an abnormality detection pulse is input via terminal 103, and when the abnormality detection pulse is on, the CPU abnormality pulse is sent a predetermined number of times (n).
When the CPU is turned on, a CPU reset signal is output to the terminal 104.

第２図は、第１囚に示す保護付きＣＰ　Ｕ　ＩＪ上セツ
ト路の各部の動作波形を示すタイミング図である。信号
線２０１上にパルスが入力され、一定時間で以上にわた
って次のパルスが入力されないと、信号線２０２上にＣ
ＰＵ異常通知ノくルスが発生する。そこで、信号線２０
３上の異常検知パルス信号の状態が変化し　ｆ１号線２
０４上にＣＰＵリセット信号が得られる。FIG. 2 is a timing chart showing operation waveforms of various parts of the set path on the protected CPU IJ shown in the first prisoner. When a pulse is input on the signal line 201 and the next pulse is not input for a certain period of time, a C signal is input on the signal line 202.
A PU error notification error occurs. Therefore, the signal line 20
The state of the abnormality detection pulse signal on f1 line 2 changes.
A CPU reset signal is available on 04.

（発明の効果） 本発明は以上説明したように、ＣＰＵの異常時に予め定
められた回数の保護をとってＣＰＵをリセットすること
により、ＣＰＵが自動復旧しやすいリセット方式を簡単
な回路で実現できると云う効果がある。(Effects of the Invention) As explained above, the present invention makes it possible to realize a reset method that facilitates automatic recovery of the CPU with a simple circuit by resetting the CPU after taking protection a predetermined number of times when the CPU is abnormal. There is an effect called.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は１本発明による保護付きＣＰ　Ｕ　ＩＪ上セツ
ト路の一実施例を示すブロック図である。 第２図は、第１囚に示す保護付きＣＰ　Ｕ　ＩＪ上セツ
ト路の各部動作波形を示すタイミング図である。 ｌ・・・パルス切断検出回路 ２・・・異常パルス発生回路 ３・・・リセット信号出力回路 １０１〜１０４・・・端子 ２０１〜２０４・・・信号線 特許出願人　　日本電気株式会社FIG. 1 is a block diagram illustrating one embodiment of a protected CPU IJ set path according to the present invention. FIG. 2 is a timing diagram showing operation waveforms of each part of the set path on the protected CPU IJ shown in the first prisoner. l...Pulse disconnection detection circuit 2...Abnormal pulse generation circuit 3...Reset signal output circuit 101-104...Terminals 201-204...Signal line Patent applicant NEC Corporation

Claims (1)

【特許請求の範囲】[Claims] 第１の一定時間以上にわたつてＣＰＵが正常動作中であ
ることを示す正常動作パルスが入力されないとＣＰＵ異
常通知パルスを出力するためのパルス切断検出回路と、
前記ＣＰＵ異常通知パルスが入力されると第２の一定時
間の幅を有する異常検知パルスを出力するための異常パ
ルス発生回路と、前記ＣＰＵ異常通知パルスと前記異常
検知パルスとを入力して、前記異常検知パルスの入力中
に前記ＣＰＵ異常通知パルスを連続して予め決められた
回数だけ検出するとＣＰＵリセット信号を出力するため
のリセット信号出力回路とを具備して構成したことを特
徴とする保護付きＣＰＵリセット回路。a pulse disconnection detection circuit for outputting a CPU abnormality notification pulse if a normal operation pulse indicating that the CPU is in normal operation is not input for a first certain period of time or more;
an abnormality pulse generation circuit for outputting an abnormality detection pulse having a second fixed time width when the CPU abnormality notification pulse is input; A protection system characterized by comprising a reset signal output circuit for outputting a CPU reset signal when the CPU abnormality notification pulse is continuously detected a predetermined number of times during input of the abnormality detection pulse. CPU reset circuit.
JP63025078A 1988-02-05 1988-02-05 Cpu resetting circuit with protection Pending JPH01200442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63025078A JPH01200442A (en) 1988-02-05 1988-02-05 Cpu resetting circuit with protection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63025078A JPH01200442A (en) 1988-02-05 1988-02-05 Cpu resetting circuit with protection

Publications (1)

Publication Number Publication Date
JPH01200442A true JPH01200442A (en) 1989-08-11

Family

ID=12155888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63025078A Pending JPH01200442A (en) 1988-02-05 1988-02-05 Cpu resetting circuit with protection

Country Status (1)

Country Link
JP (1) JPH01200442A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011147058A (en) * 2010-01-18 2011-07-28 Fujitsu Ltd Clock device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011147058A (en) * 2010-01-18 2011-07-28 Fujitsu Ltd Clock device
US8564355B2 (en) 2010-01-18 2013-10-22 Fujitsu Limited Clock device

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