JPH0276049A - Bus error detecting circuit for microprocessor - Google Patents

Abstract

PURPOSE:To prevent abnormal operation even when a bus error is generated by providing a time window circuit, a change point detecting circuit, an AND gate and a reset pulse generating circuit. CONSTITUTION:When the bus error is generated by an external noise, a positive signal is outputted from a time window circuit 3 on a signal line 13 during timing t1-t2 to obtain a stable value, which is determined in advance, according to a control signal on a signal line 11. Then, when a pass data signal on a signal line 10 inverts a polarity at a time t3 during the time t1-t2 by the external noise, the positive signal of constant pulse width is outputted from a change point detecting circuit 2 on a signal line 12 at the time t3 and inputted to an AND gate 4 and a signal is generated on a signal line 14. When this signal is inputted to a reset pulse generating circuit 5, the reset signal of the constant pulse width having a rise at the time t3 is outputted on a signal line 15 and inputted to a microprocessor 1. Thus, the abnormal operation can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprocessor system, and more particularly to a path error detection circuit that detects the occurrence of a path error and resets a microprocessor.

(Prior Art) Conventionally, path errors in microprocessor systems have been detected using an indirect method of approximately detecting a button using a power interruption detection circuit.

(Problem to be Solved by the Invention) With the conventional indirect path error detection method described above, it is not possible to detect higher abnormal voltages other than W14@ caused by power surges, and a path error occurs and 4 cannot be detected. There is a drawback.

An object of the present invention is to detect a path error in a microprocessor and generate a microprocessor input signal.
It is an object of the present invention to provide a path error detection circuit for a microprocessor that is configured to eliminate the above-mentioned drawbacks and to easily detect path errors.

(Top Means for Solving the Problem) The path error detection circuit of the microprocessor according to the present invention includes a time window circuit, a change point detection circuit, and an AND
It is configured to include a gate and a reset pulse generation circuit.

The time window circuit is a ninth circuit that outputs a positive signal only during the timing period when the path data signal output from the microprocessor takes a stable value.

The change point detection circuit is the sixth one that outputs a positive signal having a constant pulse width at the six rising edges and six falling edges of the pass data signal.

The AND gate is for inputting the output of the change point detection circuit and the output of the time window 9 circuit and performing an AND operation.

The reset pulse generation circuit is for outputting a positive pulse signal having a necessary reset width to the microprocessor in response to the rise of the output signal of the AND gate.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a path error detection circuit for a microprocessor according to the present invention.

In FIG. 1, 1 is a microprocessor, 2 is a change point detection circuit, 3 is a time window circuit, 4 is an AND gate, and S is a reset pulse generation circuit.

The path data signal outputted from the microprocessor 1 onto the signal line 10 is input to the change point detection circuit 2, and the change point detection circuit 2 generates a positive pulse having a constant pulse width at the rise and fall of the path data signal. Generate a signal and connect signal line 1
Output on 2. The path data timing control signal outputted from the microprocessor 1 onto the signal line 11 is input to the time window circuit 3.
Then, during the time when the path data signal takes a stable value, a positive signal is generated and output onto the signal line 13.

The positive signal on the signal line 12 and the positive signal on the signal line 13 are input to the AND gate 4, and the output signal is input to the reset pulse generation circuit S via the signal line 14. Signal line 1
At the rising timing of the output signal 4, the reset pulse generating circuit 5 generates a reset signal having a constant pulse width and outputs it onto the signal line 1S.

Hereinafter, the operation of the present invention will be explained in detail.

Generally, the microprocessor 1 outputs a bus signal and a control signal for notifying peripheral circuits of the timing at which the path signal takes a stable value. Bus signals generally include an address bus signal, a data bus signal, or an address data bus signal that is a multiplex of an address signal and a data bus signal, and control signals include an address latch enable signal, a read pulse signal, and a write pulse signal. There is.

Furthermore, in order for the microprocessor 1 to operate normally,
The bus signal is required to take a stable value at a predetermined timing.

The operation when the signal cannot take a stable value due to external noise at the timing when it is required to take a stable value will be explained with reference to FIG.

As is clear from FIG. 2, a positive signal is transmitted from the time window circuit 3 onto the signal line 13 between timings t1 and t when a stable value predetermined by the control signal on the signal line 11 must be taken. is output to. time t
1~t! When the path data signal on the signal line 10 is inverted at time t3 due to Jf, the polarity is reversed at the same time t.
, a positive signal with a constant pulse width is output from the change point detection circuit 2 onto the signal line 12. , signal lines 12 and 13 are both input to AND gate 4, a signal is generated on signal line 14. , @When the signal on the return line 14 is input to the reset pulse generation circuit 6, time t occurs.

A reset signal with a constant pulse width with a rising edge is sent to signal line 1.
Output on S. The reset signal is input to the microprocessor 1 via the signal line 1S.

As mentioned above, when a path error occurs due to one external noise,
A reset signal is output to the microprocessor 1.

(Effects of the Invention) As explained above, the present invention detects a path error in a microprocessor and generates a microgross processor reset signal. This has the effect of being able to be reset before the abnormal operation starts, and preventing the abnormal operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a path error detection circuit for a microprocessor according to the present invention. FIG. 2 is an explanatory diagram showing an example of the operation of the path error detection circuit shown in FIG. 1. 1.Φ.Microprocessor 2...Changing point detection circuit 3...Time window 9 circuit 4...AND gate 5...Reset pulse generation circuit 10-15...Signal line

Claims (1)

[Claims] a time window circuit for outputting a positive signal only during the period when the path data signal output from the microprocessor takes a stable value; and a time window circuit for outputting a positive signal having a constant pulse width at the rise and fall of the bus data signal a change point detection circuit for outputting a signal; an AND gate for inputting and ANDing the output of the change point detection circuit and the output of the time window circuit; 1. A path error detection circuit for a microprocessor, comprising a reset pulse generation circuit for outputting a positive pulse signal having a necessary reset width to the microprocessor.