JPH01298424A - Stop detecting circuit for clock signal - Google Patents

Abstract

PURPOSE:To detect the stop of a clock signal regardless of the cause due to a trouble or a control means by providing a delaying circuit, a first F/F and a second F/F. CONSTITUTION:A clock signal 1 of synchronization tau is respectively connected to data input terminals 3b and 4b of an F/F 3 and an F/F 4 and the input terminal of a delaying circuit 2 and the delaying circuit 2 is delayed by (n+1/4)tau the clock signal 1. The through signal of a delaying clock is connected to a clock terminal 3a of a first F/F 3 and a complement signal is connected to a clock terminal 4a of a second F/F 4 respectively. When an input clock signal 1 is stopped at a 0 level, the output of the F/F 3 becomes the 0 level, when it is stopped by a 1 level, the output of the F/F 4 becomes the 0 level, and therefore, the output of an AND circuit 5 becomes a logic 0 level in any cases. Thus, without searching the trouble of other part, the abnormality of the input clock signal can be immediately known.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit that detects that a clock signal used in an information processing device has stopped.

(Prior Art) In an information processing device, when a clock signal is stopped using a control means, a control signal indicating the stop is generally output.

(Problem to be Solved by the Invention) However, if clock generation is interrupted due to a failure, no control signal is output.

Therefore, when a clock signal is stopped due to a failure in a clock signal line or the like, the control signal is not output even though the nature of the failure is widespread, so it takes a lot of time to locate the failure.

It is an object of the present invention that if the clock signal stops, whether due to a failure or due to control means,
By detecting all of this.

The object of the present invention is to provide a clock signal stop detection circuit 1 that can solve the above drawbacks.

(Means for Solving the Problems) In order to achieve the above object, the clock signal stop detection circuit according to the present invention inputs a clock signal with a period τ that repeats logic 0°1 every audience time, ) a delay circuit that allows a τ time delay, a first F/F whose clock terminal is connected to the output of the delay circuit and whose data input terminal is connected to the clock signal, and whose clock terminal is connected to the complement output of the delay circuit. a second F/F whose data input terminal is connected to the clock signal; and a second F/F connected to the first F/F.
It consists of an AND circuit whose inputs are the F/F output and the complement output of the second F/F.

(Example) The present invention will be explained in more detail below with reference to one drawing.

FIG. 1 is a block diagram showing an embodiment of a clock signal stop detection circuit according to the present invention.

Figure 2 shows the operation of Figure 1'! This is a timing chart for explaining ``i1''.

The signal line that supplies clock signal 1 with period τ is connected to the first F/
The data input terminals 3b and 4b of F3 and second F/F4 are connected to the input terminal of delay circuit 2, respectively. In this embodiment, n=1, so the delay circuit 2 delays the clock signal by 5/4τ.

The through signal of the delayed clock is connected to the clock terminal 3a of the first F/F 3, and the complement signal is connected to the clock terminal 4a of the second F/F 4.

The arrow 6 of the output waveform of the delay circuit 2 in FIG. 2 indicates the timing at which the first F/F 3 and the second F/F 4 operate.

As is clear from FIG. 2, the first F/F 3 operates only when the clock signal 1 input to the data terminal 3b is at logic "1".

Similarly, the second F/F 4 operates only when the clock signal 1 input to the data terminal 4a is logic ``0''.

The first F/F 3 is for detecting a failure when the input clock signal l is at the logic "'0" level, and the operation timing in this state is shown in FIG.

The second F/F 4 is for detecting a failure when the input clock signal 1 is at the logic "1" level, and the operation timing in this state is shown in FIG.

Both the through output of the first F/P 3 and the complement output of the second F/F 4 become logic "1" when the input clock signal 1 is normal, so the output of the AND circuit 5 also becomes logic "1". becomes.

When the input clock signal 1 stops at the 1()'' level as shown in Figure 3, the output of the first F/F 3 becomes ``0''.
Since the output of the AND circuit 5 becomes the logic "U" level, it is possible to determine whether the input clock signal 1 has stopped.

Also, the input clock signal 1 is "1" as shown in FIG.
If it stops at the level, the output of the second F/F 4 becomes the "υ" level, so the output of the QAND circuit 5 becomes the logic "0" level, and similarly the input clock signal 1
The stoppage can be determined.

(Effects of the Invention) As explained above, the present invention delays an input clock signal by (n+'/4)τ (an integer greater than or equal to n-1) using a delay circuit, and converts the input clock signal using the delayed clock signal. By setting F/F# as all data, it is possible to detect the stop of the input clock signal.

Therefore, when the clock signal is stopped by another control means, the control signal for notifying the clock stoppage can be omitted, and when a failure occurs in the device, there is no need to search for a failure in other parts.

It is possible to immediately know that there is an abnormality in the input clock signal.

[Brief explanation of the drawing]

The second reason is a block diagram showing an embodiment of the clock signal stop detection circuit according to the present invention, and FIG. 2 is a timing chart for explaining the OK operation when the input clock signal is normal.
Figure 3 explains the operation when the input clock signal fails at the 10''level;
The figure is a timing chart for explaining the operation when the input clock signal fails at the "'1" level. 1... Clock signal 2... Delay circuit 3... First F/F 4... Second F/F 5... AND circuit Patent applicant NEC Corporation Agent Patent attorney Ino B ° 21st figure F22 size Φ outside, 3 tomoe

Claims (1)

[Claims] Logical U. every τ/2 hours. a delay circuit which inputs a clock signal with a period τ for repeating I and delays it by (n+1/4)τ time; and a first circuit whose clock terminal is connected to the output of the delay circuit and whose data input terminal is connected to the clock signal. F
/F, a second F/F whose clock terminal is connected to the complement output of the delay circuit and whose data input terminal is connected to the clock signal, and the first F/F output and the second F/F. A clock signal stop detection circuit comprising an AND circuit whose input is a complement output of an F/F.